46103 lines
2.9 MiB
46103 lines
2.9 MiB
; --------------------------------------------------------------------------------
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; @Title: F2838XX On-Chip Peripherals
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; @Props: Released
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; @Author: KWI
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; @Changelog: 2020-05-28 KWI
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; @Manufacturer: TI - Texas Instruments
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; @Doc: XML generated (TIXML2PER), based on:
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; f28384d.xml (Ver. 2), f28384s.xml (Ver. 2), f28386d.xml (Ver. 2),
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; f28386s.xml (Ver. 2), f28388d.xml (Ver. 2), f28388s.xml (Ver. 2)
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; @Core: C28x, Cortex-M4
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; @Chip: F28384D, F28386D, F28386S, F28388D, F28388S, F28384S
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; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertms320f2838xx.per 14763 2022-05-16 10:22:27Z kwisniewski $
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config 16. 8.
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sif (CORENAME()=="CORTEXM4")
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tree.close "Core Registers (Cortex-M4)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.ON center tree
|
|
tree "System Control"
|
|
tree "AccessProtectionRegs"
|
|
width 16.
|
|
rgroup.long (d:0x0005F500+0x00)++0x03
|
|
line.long 0x00 "NMAVFLG,Non-Master Access Violation Flag Register"
|
|
bitfld.long 0x00 10. " DMAREAD ,Non Master DMA read Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 6. " CLA1FETCH ,Non Master CLA1 Fetch Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 5. " CLA1WRITE ,Non Master CLA1 Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 4. " CLA1READ ,Non Master CLA1 Read Access Violation Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMAWRITE ,Non Master DMA Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 2. " CPUFETCH ,Non Master CPU Fetch Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Non Master CPU Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 0. " CPUREAD ,Non Master CPU Read Access Violation Flag" "0,1"
|
|
group.long (d:0x0005F500+0x02)++0x03
|
|
line.long 0x00 "NMAVSET,Non-Master Access Violation Flag Set Register"
|
|
bitfld.long 0x00 10. " DMAREAD ,Non Master DMA read Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 6. " CLA1FETCH ,Non Master CLA1 Fetch Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 5. " CLA1WRITE ,Non Master CLA1 Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 4. " CLA1READ ,Non Master CLA1 Read Access Violation Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMAWRITE ,Non Master DMA Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 2. " CPUFETCH ,Non Master CPU Fetch Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Non Master CPU Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " CPUREAD ,Non Master CPU Read Access Violation Flag Set" "0,1"
|
|
group.long (d:0x0005F500+0x04)++0x03
|
|
line.long 0x00 "NMAVCLR,Non-Master Access Violation Flag Clear Register"
|
|
bitfld.long 0x00 10. " DMAREAD ,Non Master DMA read Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 6. " CLA1FETCH ,Non Master CLA1 Fetch Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 5. " CLA1WRITE ,Non Master CLA1 Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 4. " CLA1READ ,Non Master CLA1 Read Access Violation Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMAWRITE ,Non Master DMA Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 2. " CPUFETCH ,Non Master CPU Fetch Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Non Master CPU Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " CPUREAD ,Non Master CPU Read Access Violation Flag Clear" "0,1"
|
|
group.long (d:0x0005F500+0x06)++0x03
|
|
line.long 0x00 "NMAVINTEN,Non-Master Access Violation Interrupt Enable Register"
|
|
bitfld.long 0x00 10. " DMAREAD ,Non Master DMA Read Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 6. " CLA1FETCH ,Non Master CLA1 Fetch Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 5. " CLA1WRITE ,Non Master CLA1 Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 4. " CLA1READ ,Non Master CLA1 Read Access Violation Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMAWRITE ,Non Master DMA Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. " CPUFETCH ,Non Master CPU Fetch Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Non Master CPU Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. " CPUREAD ,Non Master CPU Read Access Violation Interrupt Enable" "0,1"
|
|
rgroup.long (d:0x0005F500+0x08)++0x03
|
|
line.long 0x00 "NMCPURDAVADDR,Non-Master CPU Read Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x0A)++0x03
|
|
line.long 0x00 "NMCPUWRAVADDR,Non-Master CPU Write Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x0C)++0x03
|
|
line.long 0x00 "NMCPUFAVADDR,Non-Master CPU Fetch Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x0E)++0x03
|
|
line.long 0x00 "NMDMAWRAVADDR,Non-Master DMA Write Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x10)++0x03
|
|
line.long 0x00 "NMCLA1RDAVADDR,Non-Master CLA1 Read Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x12)++0x03
|
|
line.long 0x00 "NMCLA1WRAVADDR,Non-Master CLA1 Write Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x14)++0x03
|
|
line.long 0x00 "NMCLA1FAVADDR,Non-Master CLA1 Fetch Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x1C)++0x03
|
|
line.long 0x00 "NMDMARDAVADDR,Non-Master DMA Read Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x20)++0x03
|
|
line.long 0x00 "MAVFLG,Master Access Violation Flag Register"
|
|
bitfld.long 0x00 2. " DMAWRITE ,Master DMA Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Master CPU Write Access Violation Flag" "0,1"
|
|
bitfld.long 0x00 0. " CPUFETCH ,Master CPU Fetch Access Violation Flag" "0,1"
|
|
group.long (d:0x0005F500+0x22)++0x03
|
|
line.long 0x00 "MAVSET,Master Access Violation Flag Set Register"
|
|
bitfld.long 0x00 2. " DMAWRITE ,Master DMA Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Master CPU Write Access Violation Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " CPUFETCH ,Master CPU Fetch Access Violation Flag Set" "0,1"
|
|
group.long (d:0x0005F500+0x24)++0x03
|
|
line.long 0x00 "MAVCLR,Master Access Violation Flag Clear Register"
|
|
bitfld.long 0x00 2. " DMAWRITE ,Master DMA Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Master CPU Write Access Violation Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " CPUFETCH ,Master CPU Fetch Access Violation Flag Clear" "0,1"
|
|
group.long (d:0x0005F500+0x26)++0x03
|
|
line.long 0x00 "MAVINTEN,Master Access Violation Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " DMAWRITE ,Master DMA Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRITE ,Master CPU Write Access Violation Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. " CPUFETCH ,Master CPU Fetch Access Violation Interrupt Enable" "0,1"
|
|
rgroup.long (d:0x0005F500+0x28)++0x03
|
|
line.long 0x00 "MCPUFAVADDR,Master CPU Fetch Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x2A)++0x03
|
|
line.long 0x00 "MCPUWRAVADDR,Master CPU Write Access Violation Address"
|
|
rgroup.long (d:0x0005F500+0x2C)++0x03
|
|
line.long 0x00 "MDMAWRAVADDR,Master DMA Write Access Violation Address"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ClkCfgRegs"
|
|
width 16.
|
|
group.long (d:0x0005D200+0x00)++0x03
|
|
line.long 0x00 "CLKSEM,Clock Control Semaphore Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x00 0.--1. " SEM ,Semaphore for CLKCFG Ownership by CPU1 or CPU2" "0,1,2,3"
|
|
group.long (d:0x0005D200+0x02)++0x03
|
|
line.long 0x00 "CLKCFGLOCK1,Lock bit for CLKCFG registers"
|
|
bitfld.long 0x00 18. " CMCLKCTL ,Lock bit for CMCLKCTL register" "0,1"
|
|
bitfld.long 0x00 17. " ETHERCATCLKCTL ,Lock bit for ETHERCATCLKCTL register" "0,1"
|
|
bitfld.long 0x00 16. " XTALCR ,Lock bit for XTALCR register" "0,1"
|
|
bitfld.long 0x00 15. " LOSPCP ,Lock bit for LOSPCP register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " CLBCLKCTL ,Lock bit for CLBCLKCTL register" "0,1"
|
|
bitfld.long 0x00 13. " PERCLKDIVSEL ,Lock bit for PERCLKDIVSEL register" "0,1"
|
|
bitfld.long 0x00 12. " AUXCLKDIVSEL ,Lock bit for AUXCLKDIVSEL register" "0,1"
|
|
bitfld.long 0x00 11. " SYSCLKDIVSEL ,Lock bit for SYSCLKDIVSEL register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " AUXPLLMULT ,Lock bit for AUXPLLMULT register" "0,1"
|
|
bitfld.long 0x00 7. " AUXPLLCTL1 ,Lock bit for AUXPLLCTL1 register" "0,1"
|
|
bitfld.long 0x00 6. " SYSPLLMULT ,Lock bit for SYSPLLMULT register" "0,1"
|
|
bitfld.long 0x00 5. " SYSPLLCTL3 ,Lock bit for SYSPLLCTL3 register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " SYSPLLCTL2 ,Lock bit for SYSPLLCTL2 register" "0,1"
|
|
bitfld.long 0x00 3. " SYSPLLCTL1 ,Lock bit for SYSPLLCTL1 register" "0,1"
|
|
bitfld.long 0x00 2. " CLKSRCCTL3 ,Lock bit for CLKSRCCTL3 register" "0,1"
|
|
bitfld.long 0x00 1. " CLKSRCCTL2 ,Lock bit for CLKSRCCTL2 register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " CLKSRCCTL1 ,Lock bit for CLKSRCCTL1 register" "0,1"
|
|
group.long (d:0x0005D200+0x08)++0x03
|
|
line.long 0x00 "CLKSRCCTL1,Clock Source Control register-1"
|
|
bitfld.long 0x00 4. " XTALOFF ,Crystal (External) Oscillator Off Bit" "0,1"
|
|
bitfld.long 0x00 3. " INTOSC2OFF ,Internal Oscillator 2 Off Bit" "0,1"
|
|
bitfld.long 0x00 0.--1. " OSCCLKSRCSEL ,OSCCLK Source Select Bit" "0,1,2,3"
|
|
group.long (d:0x0005D200+0x0A)++0x03
|
|
line.long 0x00 "CLKSRCCTL2,Clock Source Control register-2"
|
|
bitfld.long 0x00 10.--11. " MCANABITCLKSEL ,MCAN (global) Bit-Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CANBBCLKSEL ,CANB Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " CANABCLKSEL ,CANA Clock Source Select Bit" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AUXOSCCLKSRCSEL ,AUXOSCCLK Source Select Bit" "0,1,2,3"
|
|
group.long (d:0x0005D200+0x0C)++0x03
|
|
line.long 0x00 "CLKSRCCTL3,Clock Source Control register-3"
|
|
bitfld.long 0x00 0.--3. " XCLKOUTSEL ,XCLKOUT Source Select Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005D200+0x0E)++0x03
|
|
line.long 0x00 "SYSPLLCTL1,SYSPLL Control register-1"
|
|
bitfld.long 0x00 1. " PLLCLKEN ,SYSPLL bypassed or included in the PLLSYSCLK path" "0,1"
|
|
bitfld.long 0x00 0. " PLLEN ,SYSPLL enable/disable bit" "0,1"
|
|
group.long (d:0x0005D200+0x14)++0x03
|
|
line.long 0x00 "SYSPLLMULT,SYSPLL Multiplier register"
|
|
bitfld.long 0x00 24.--28. " REFDIV ,Reference Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " ODIV ,Output Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--7. 1. "IMULT,SYSPLL Integer Multiplier"
|
|
rgroup.long (d:0x0005D200+0x16)++0x03
|
|
line.long 0x00 "SYSPLLSTS,SYSPLL Status register"
|
|
bitfld.long 0x00 1. " SLIPS ,SYSPLL Slip Status Bit" "0,1"
|
|
bitfld.long 0x00 0. " LOCKS ,SYSPLL Lock Status Bit" "0,1"
|
|
group.long (d:0x0005D200+0x18)++0x03
|
|
line.long 0x00 "AUXPLLCTL1,AUXPLL Control register-1"
|
|
bitfld.long 0x00 1. " PLLCLKEN ,AUXPLL bypassed or included in the AUXPLLCLK path" "0,1"
|
|
bitfld.long 0x00 0. " PLLEN ,AUXPLL enable/disable bit" "0,1"
|
|
group.long (d:0x0005D200+0x1E)++0x03
|
|
line.long 0x00 "AUXPLLMULT,AUXPLL Multiplier register"
|
|
bitfld.long 0x00 24.--28. " REFDIV ,Reference Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " ODIV ,Output Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long 0x00 0.--7. 1. "IMULT,AUXPLL Integer Multiplier"
|
|
rgroup.long (d:0x0005D200+0x20)++0x03
|
|
line.long 0x00 "AUXPLLSTS,AUXPLL Status register"
|
|
bitfld.long 0x00 1. " SLIPS ,AUXPLL Slip Status Bit" "0,1"
|
|
bitfld.long 0x00 0. " LOCKS ,AUXPLL Lock Status Bit" "0,1"
|
|
group.long (d:0x0005D200+0x22)++0x03
|
|
line.long 0x00 "SYSCLKDIVSEL,System Clock Divider Select register"
|
|
bitfld.long 0x00 0.--5. " PLLSYSCLKDIV ,PLLSYSCLK Divide Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005D200+0x24)++0x03
|
|
line.long 0x00 "AUXCLKDIVSEL,Auxillary Clock Divider Select register"
|
|
bitfld.long 0x00 8.--12. " MCANCLKDIV ,Divider between CANFD Source Clock and CANFD Bit CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " AUXPLLDIV ,AUXPLLCLK Divide Select" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x0005D200+0x26)++0x03
|
|
line.long 0x00 "PERCLKDIVSEL,Peripheral Clock Divider Selet register"
|
|
bitfld.long 0x00 6. " EMIF2CLKDIV ,EMIF2 Clock Divide Select" "0,1"
|
|
bitfld.long 0x00 4. " EMIF1CLKDIV ,EMIF1 Clock Divide Select" "0,1"
|
|
bitfld.long 0x00 0.--1. " EPWMCLKDIV ,EPWM Clock Divide Select" "0,1,2,3"
|
|
group.long (d:0x0005D200+0x28)++0x03
|
|
line.long 0x00 "XCLKOUTDIVSEL,XCLKOUT Divider Select register"
|
|
bitfld.long 0x00 0.--1. " XCLKOUTDIV ,XCLKOUT Divide Select" "0,1,2,3"
|
|
group.long (d:0x0005D200+0x2A)++0x03
|
|
line.long 0x00 "CLBCLKCTL,CLB Clocking Control Register"
|
|
bitfld.long 0x00 23. " CLKMODECLB8 ,Clock mode of CLB8" "0,1"
|
|
bitfld.long 0x00 22. " CLKMODECLB7 ,Clock mode of CLB7" "0,1"
|
|
bitfld.long 0x00 21. " CLKMODECLB6 ,Clock mode of CLB6" "0,1"
|
|
bitfld.long 0x00 20. " CLKMODECLB5 ,Clock mode of CLB5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLKMODECLB4 ,Clock mode of CLB4" "0,1"
|
|
bitfld.long 0x00 18. " CLKMODECLB3 ,Clock mode of CLB3" "0,1"
|
|
bitfld.long 0x00 17. " CLKMODECLB2 ,Clock mode of CLB2" "0,1"
|
|
bitfld.long 0x00 16. " CLKMODECLB1 ,Clock mode of CLB1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " TILECLKDIV ,CLB Tile clock divider configuration." "0,1"
|
|
bitfld.long 0x00 0.--2. " CLBCLKDIV ,CLB clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x0005D200+0x2C)++0x03
|
|
line.long 0x00 "LOSPCP,Low Speed Clock Source Prescalar"
|
|
bitfld.long 0x00 0.--2. " LSPCLKDIV ,LSPCLK Divide Select" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x0005D200+0x2E)++0x03
|
|
line.long 0x00 "MCDCR,Missing Clock Detect Control Register"
|
|
bitfld.long 0x00 3. " OSCOFF ,Oscillator Clock Off Bit" "0,1"
|
|
bitfld.long 0x00 2. " MCLKOFF ,Missing Clock Detect Off Bit" "0,1"
|
|
bitfld.long 0x00 1. " MCLKCLR ,Missing Clock Clear Bit" "0,1"
|
|
rbitfld.long 0x00 0. " MCLKSTS ,Missing Clock Status Bit" "0,1"
|
|
group.long (d:0x0005D200+0x30)++0x03
|
|
line.long 0x00 "X1CNT,10-bit Counter on X1 Clock"
|
|
bitfld.long 0x00 16. " CLR ,X1 Counter Clear" "0,1"
|
|
hexmask.long 0x00 0.--9. 1. "X1CNT,X1 Counter"
|
|
group.long (d:0x0005D200+0x32)++0x03
|
|
line.long 0x00 "XTALCR,XTAL Control Register"
|
|
bitfld.long 0x00 1. " SE ,XTAL Oscilator in Single-Ended mode" "0,1"
|
|
bitfld.long 0x00 0. " OSCOFF ,XTAL Oscillator powered-down" "0,1"
|
|
group.long (d:0x0005D200+0x36)++0x03
|
|
line.long 0x00 "ETHERCATCLKCTL,ETHERCATCLKCTL"
|
|
bitfld.long 0x00 8. " PHYCLKEN ,etherCAT PHY clock enable" "0,1"
|
|
bitfld.long 0x00 1.--3. " ECATDIV ,etherCAT clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " DIVSRCSEL ,Clock source select for the etherCAT clock divider." "0,1"
|
|
group.long (d:0x0005D200+0x38)++0x03
|
|
line.long 0x00 "CMCLKCTL,CMCLKCTL"
|
|
bitfld.long 0x00 5.--7. " ETHDIV ,Ethernet clock divider configuration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. " ETHDIVSRCSEL ,Clock source select for the etherNET clock divider." "0,1"
|
|
bitfld.long 0x00 1.--3. " CMCLKDIV ,CM clock divider configuration." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " CMDIVSRCSEL ,Clock source select for the CM clock divider." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CmConfRegs"
|
|
width 19.
|
|
group.long (d:0x0005DC00+0x00)++0x03
|
|
line.long 0x00 "CMRESCTL,CM Reset Control Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key value"
|
|
rbitfld.long 0x00 1. " RESETSTS ,CM Reset status" "0,1"
|
|
bitfld.long 0x00 0. " RESET ,Software reset to CM" "0,1"
|
|
group.long (d:0x0005DC00+0x02)++0x03
|
|
line.long 0x00 "CMTOCPU1NMICTL,CM To CPU1 NMI Control register"
|
|
bitfld.long 0x00 2. " CMNMIWDRST ,CMNMIWDRST NMI enable bit, enables nmi generation to C28x" "0,1"
|
|
group.long (d:0x0005DC00+0x04)++0x03
|
|
line.long 0x00 "CMTOCPU1INTCTL,CM To CPU1 interrupt Control register"
|
|
bitfld.long 0x00 2. " CMNMIWDRST ,CMNMIWDRST Interrupt enable bit, enables interrupt to C28x" "0,1"
|
|
bitfld.long 0x00 1. " SYSRESETREQ ,SYSRESETREQ Interrupt enable bit, enables interrupt to C28x" "0,1"
|
|
bitfld.long 0x00 0. " VECTRESET ,VECTRESET Interrupt enable bit, enables interrupt to C28x" "0,1"
|
|
group.long (d:0x0005DC00+0x20)++0x03
|
|
line.long 0x00 "PALLOCATE0,CM Peripheral Allocation Register."
|
|
bitfld.long 0x00 3. " CAN_B ,Allocate CANB to CM" "0,1"
|
|
bitfld.long 0x00 2. " CAN_A ,Allocate CANA to CM" "0,1"
|
|
bitfld.long 0x00 1. " ETHERCAT ,Allocate ETHERCAT to CM" "0,1"
|
|
bitfld.long 0x00 0. " USB_A ,Allocate USB_A to CM" "0,1"
|
|
group.long (d:0x0005DC00+0x3FE)++0x03
|
|
line.long 0x00 "CM_CONF_REGS_LOCK,CM Configuration Registers Lock"
|
|
bitfld.long 0x00 0. " LOCK ,Lock one time CM configuration registers." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CpuSysRegs"
|
|
width 13.
|
|
group.long (d:0x0005D300+0x00)++0x03
|
|
line.long 0x00 "CPUSYSLOCK1,Lock bit for CPUSYS registers"
|
|
bitfld.long 0x00 30. " PCLKCR23 ,Lock bit for PCLKCR23 Register" "0,1"
|
|
bitfld.long 0x00 29. " PCLKCR22 ,Lock bit for PCLKCR22 Register" "0,1"
|
|
bitfld.long 0x00 28. " PCLKCR21 ,Lock bit for PCLKCR21 Register" "0,1"
|
|
bitfld.long 0x00 27. " PCLKCR20 ,Lock bit for PCLKCR20 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " PCLKCR18 ,Lock bit for PCLKCR18 Register" "0,1"
|
|
bitfld.long 0x00 24. " PCLKCR17 ,Lock bit for PCLKCR17 Register" "0,1"
|
|
bitfld.long 0x00 23. " GPIOLPMSEL1 ,Lock bit for GPIOLPMSEL1 Register" "0,1"
|
|
bitfld.long 0x00 22. " GPIOLPMSEL0 ,Lock bit for GPIOLPMSEL0 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " LPMCR ,Lock bit for LPMCR Register" "0,1"
|
|
bitfld.long 0x00 19. " PCLKCR16 ,Lock bit for PCLKCR16 Register" "0,1"
|
|
bitfld.long 0x00 17. " PCLKCR14 ,Lock bit for PCLKCR14 Register" "0,1"
|
|
bitfld.long 0x00 16. " PCLKCR13 ,Lock bit for PCLKCR13 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " PCLKCR11 ,Lock bit for PCLKCR11 Register" "0,1"
|
|
bitfld.long 0x00 13. " PCLKCR10 ,Lock bit for PCLKCR10 Register" "0,1"
|
|
bitfld.long 0x00 12. " PCLKCR9 ,Lock bit for PCLKCR9 Register" "0,1"
|
|
bitfld.long 0x00 11. " PCLKCR8 ,Lock bit for PCLKCR8 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " PCLKCR7 ,Lock bit for PCLKCR7 Register" "0,1"
|
|
bitfld.long 0x00 9. " PCLKCR6 ,Lock bit for PCLKCR6 Register" "0,1"
|
|
bitfld.long 0x00 7. " PCLKCR4 ,Lock bit for PCLKCR4 Register" "0,1"
|
|
bitfld.long 0x00 6. " PCLKCR3 ,Lock bit for PCLKCR3 Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " PCLKCR2 ,Lock bit for PCLKCR2 Register" "0,1"
|
|
bitfld.long 0x00 4. " PCLKCR1 ,Lock bit for PCLKCR1 Register" "0,1"
|
|
bitfld.long 0x00 3. " PCLKCR0 ,Lock bit for PCLKCR0 Register" "0,1"
|
|
bitfld.long 0x00 2. " PIEVERRADDR ,Lock bit for PIEVERRADDR Register" "0,1"
|
|
group.long (d:0x0005D300+0x02)++0x03
|
|
line.long 0x00 "CPUSYSLOCK2,Lock bit for CPUSYS registers"
|
|
bitfld.long 0x00 0. " ETHERCATCTL ,Lock bit for ETHERCATCTL register" "0,1"
|
|
group.long (d:0x0005D300+0x0A)++0x03
|
|
line.long 0x00 "PIEVERRADDR,PIE Vector Fetch Error Address register"
|
|
hexmask.long 0x00 0.--21. 1. "ADDR,PIE Vector Fetch Error Handler Routine Address"
|
|
group.long (d:0x0005D300+0x0C)++0x03
|
|
line.long 0x00 "ETHERCATCTL,ETHERCAT control register."
|
|
bitfld.long 0x00 0. " I2CLOOPBACK ,Loopback I2C port of etherCAT IP to I2C_A." "0,1"
|
|
group.long (d:0x0005D300+0x22)++0x03
|
|
line.long 0x00 "PCLKCR0,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 24. " ERAD ,ERAD module clock enable" "0,1"
|
|
bitfld.long 0x00 19. " GTBCLKSYNC ,EPWM Time Base Clock Global sync" "0,1"
|
|
bitfld.long 0x00 18. " TBCLKSYNC ,EPWM Time Base Clock sync" "0,1"
|
|
bitfld.long 0x00 16. " HRCAL ,HRCAL Clock Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " CLA1BGCRC ,CLA1BGCRC Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 13. " CPUBGCRC ,CPUBGCRC Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 5. " CPUTIMER2 ,CPUTIMER2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 4. " CPUTIMER1 ,CPUTIMER1 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CPUTIMER0 ,CPUTIMER0 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " DMA ,DMA Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " CLA1 ,CLA1 Clock Enable Bit" "0,1"
|
|
group.long (d:0x0005D300+0x24)++0x03
|
|
line.long 0x00 "PCLKCR1,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 1. " EMIF2 ,EMIF2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " EMIF1 ,EMIF1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x26)++0x03
|
|
line.long 0x00 "PCLKCR2,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 15. " EPWM16 ,EPWM16 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 14. " EPWM15 ,EPWM15 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 13. " EPWM14 ,EPWM14 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 12. " EPWM13 ,EPWM13 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EPWM12 ,EPWM12 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 10. " EPWM11 ,EPWM11 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 9. " EPWM10 ,EPWM10 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 8. " EPWM9 ,EPWM9 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EPWM8 ,EPWM8 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 6. " EPWM7 ,EPWM7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 5. " EPWM6 ,EPWM6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 4. " EPWM5 ,EPWM5 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EPWM4 ,EPWM4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " EPWM3 ,EPWM3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " EPWM2 ,EPWM2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " EPWM1 ,EPWM1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x28)++0x03
|
|
line.long 0x00 "PCLKCR3,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 6. " ECAP7 ,ECAP7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 5. " ECAP6 ,ECAP6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 4. " ECAP5 ,ECAP5 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 3. " ECAP4 ,ECAP4 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ECAP3 ,ECAP3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " ECAP2 ,ECAP2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " ECAP1 ,ECAP1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x2A)++0x03
|
|
line.long 0x00 "PCLKCR4,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 2. " EQEP3 ,EQEP3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " EQEP2 ,EQEP2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " EQEP1 ,EQEP1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x2E)++0x03
|
|
line.long 0x00 "PCLKCR6,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 1. " SD2 ,SD2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " SD1 ,SD1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x30)++0x03
|
|
line.long 0x00 "PCLKCR7,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 3. " SCI_D ,SCI_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " SCI_C ,SCI_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " SCI_B ,SCI_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " SCI_A ,SCI_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x32)++0x03
|
|
line.long 0x00 "PCLKCR8,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 3. " SPI_D ,SPI_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " SPI_C ,SPI_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " SPI_B ,SPI_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " SPI_A ,SPI_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x34)++0x03
|
|
line.long 0x00 "PCLKCR9,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 1. " I2C_B ,I2C_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " I2C_A ,I2C_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x36)++0x03
|
|
line.long 0x00 "PCLKCR10,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 1. " CAN_B ,CAN_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " CAN_A ,CAN_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x38)++0x03
|
|
line.long 0x00 "PCLKCR11,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 16. " USB_A ,USB_A Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " McBSP_B ,McBSP_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " McBSP_A ,McBSP_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x3C)++0x03
|
|
line.long 0x00 "PCLKCR13,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 3. " ADC_D ,ADC_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " ADC_C ,ADC_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " ADC_B ,ADC_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " ADC_A ,ADC_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x3E)++0x03
|
|
line.long 0x00 "PCLKCR14,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 7. " CMPSS8 ,CMPSS8 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 6. " CMPSS7 ,CMPSS7 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 5. " CMPSS6 ,CMPSS6 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 4. " CMPSS5 ,CMPSS5 Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CMPSS4 ,CMPSS4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " CMPSS3 ,CMPSS3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " CMPSS2 ,CMPSS2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " CMPSS1 ,CMPSS1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x42)++0x03
|
|
line.long 0x00 "PCLKCR16,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 18. " DAC_C ,Buffered_DAC12_3 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 17. " DAC_B ,Buffered_DAC12_2 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 16. " DAC_A ,Buffered_DAC12_1 Clock Enable Bit" "0,1"
|
|
group.long (d:0x0005D300+0x44)++0x03
|
|
line.long 0x00 "PCLKCR17,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 3. " CLB4 ,CLB4 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 2. " CLB3 ,CLB3 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 1. " CLB2 ,CLB2 Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " CLB1 ,CLB1 Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x46)++0x03
|
|
line.long 0x00 "PCLKCR18,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 23. " FSIRX_H ,FSIRX_H Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 22. " FSIRX_G ,FSIRX_G Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 21. " FSIRX_F ,FSIRX_F Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 20. " FSIRX_E ,FSIRX_E Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " FSIRX_D ,FSIRX_D Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 18. " FSIRX_C ,FSIRX_C Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 17. " FSIRX_B ,FSIRX_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 16. " FSIRX_A ,FSIRX_A Clock Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FSITX_B ,FSITX_B Clock Enable bit" "0,1"
|
|
bitfld.long 0x00 0. " FSITX_A ,FSITX_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x4A)++0x03
|
|
line.long 0x00 "PCLKCR20,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 0. " PMBUS_A ,PMBUS_A Clock Enable bit" "0,1"
|
|
group.long (d:0x0005D300+0x4C)++0x03
|
|
line.long 0x00 "PCLKCR21,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 2. " DCC2 ,DCC2 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 1. " DCC1 ,DCC1 Clock Enable Bit" "0,1"
|
|
bitfld.long 0x00 0. " DCC0 ,DCC0 Clock Enable Bit" "0,1"
|
|
group.long (d:0x0005D300+0x4E)++0x03
|
|
line.long 0x00 "PCLKCR22,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 0. " PBISTCLK ,PBISTCLK Clock Enable Bit" "0,1"
|
|
group.long (d:0x0005D300+0x50)++0x03
|
|
line.long 0x00 "PCLKCR23,Peripheral Clock Gating Registers"
|
|
bitfld.long 0x00 0. " ETHERCAT ,ETHERCAT Clock Enable Bit" "0,1"
|
|
group.long (d:0x0005D300+0x70)++0x03
|
|
line.long 0x00 "SIMRESET,Simulated Reset Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key value"
|
|
bitfld.long 0x00 1. " XRSn ,Generates a simulated XRSn" "0,1"
|
|
bitfld.long 0x00 0. " CPU1RSn ,Generates a reset to CPU" "0,1"
|
|
group.long (d:0x0005D300+0x76)++0x03
|
|
line.long 0x00 "LPMCR,LPM Control Register"
|
|
bitfld.long 0x00 15. " WDINTE ,Enable for WDINT wakeup from STANDBY" "0,1"
|
|
bitfld.long 0x00 2.--7. " QUALSTDBY ,STANDBY Wakeup Pin Qualification Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. " LPM ,Low Power Mode setting" "0,1,2,3"
|
|
group.long (d:0x0005D300+0x78)++0x03
|
|
line.long 0x00 "GPIOLPMSEL0,GPIO LPM Wakeup select registers"
|
|
bitfld.long 0x00 31. " GPIO31 ,GPIO31 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,GPIO30 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,GPIO29 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,GPIO28 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,GPIO27 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,GPIO26 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,GPIO25 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,GPIO24 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,GPIO23 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,GPIO22 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,GPIO21 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,GPIO20 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,GPIO19 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,GPIO18 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,GPIO17 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,GPIO16 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,GPIO15 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,GPIO14 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,GPIO13 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,GPIO12 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,GPIO11 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,GPIO10 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,GPIO9 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,GPIO8 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,GPIO7 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,GPIO6 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,GPIO5 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,GPIO4 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,GPIO3 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,GPIO2 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,GPIO1 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,GPIO0 Enable for LPM Wakeup" "0,1"
|
|
group.long (d:0x0005D300+0x7A)++0x03
|
|
line.long 0x00 "GPIOLPMSEL1,GPIO LPM Wakeup select registers"
|
|
bitfld.long 0x00 31. " GPIO63 ,GPIO63 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,GPIO62 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,GPIO61 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,GPIO60 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,GPIO59 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,GPIO58 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,GPIO57 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,GPIO56 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,GPIO55 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,GPIO54 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,GPIO53 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,GPIO52 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,GPIO51 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,GPIO50 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,GPIO49 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,GPIO48 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,GPIO47 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,GPIO46 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,GPIO45 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,GPIO44 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,GPIO43 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,GPIO42 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,GPIO41 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,GPIO40 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,GPIO39 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,GPIO38 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,GPIO37 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,GPIO36 Enable for LPM Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,GPIO35 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,GPIO34 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,GPIO33 Enable for LPM Wakeup" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,GPIO32 Enable for LPM Wakeup" "0,1"
|
|
group.long (d:0x0005D300+0x7C)++0x03
|
|
line.long 0x00 "TMR2CLKCTL,Timer2 Clock Measurement functionality control register"
|
|
bitfld.long 0x00 3.--5. " TMR2CLKPRESCALE ,CPU Timer 2 Clock Pre-Scale Value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TMR2CLKSRCSEL ,CPU Timer 2 Clock Source Select Bit" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x0005D300+0x7E)++0x03
|
|
line.long 0x00 "RESCCLR,Reset Cause Clear Register"
|
|
bitfld.long 0x00 11. " SIMRESET_XRSn ,SIMRESET_XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 10. " SIMRESET_CPU1RSn ,SIMRESET_CPU1RSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 9. " ECAT_RESET_OUT ,ECAT_RESET_OUT Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 8. " SCCRESETn ,SCCRESETn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " HWBISTn ,HWBISTn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 3. " NMIWDRSn ,NMIWDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 2. " WDRSn ,WDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 1. " XRSn ,XRSn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " POR ,POR Reset Cause Indication Bit" "0,1"
|
|
group.long (d:0x0005D300+0x80)++0x03
|
|
line.long 0x00 "RESC,Reset Cause register"
|
|
rbitfld.long 0x00 31. " TRSTn_pin_status ,TRSTn Status" "0,1"
|
|
rbitfld.long 0x00 30. " XRSn_pin_status ,XRSN Pin Status" "0,1"
|
|
bitfld.long 0x00 11. " SIMRESET_XRSn ,SIMRESET_XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 10. " SIMRESET_CPU1RSn ,SIMRESET_CPU1RSn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " ECAT_RESET_OUT ,ECAT_RESET_OUT Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 8. " SCCRESETn ,SCCRESETn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 5. " HWBISTn ,HWBISTn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 3. " NMIWDRSn ,NMIWDRSn Reset Cause Indication Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " WDRSn ,WDRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 1. " XRSn ,XRSn Reset Cause Indication Bit" "0,1"
|
|
bitfld.long 0x00 0. " POR ,POR Reset Cause Indication Bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CpuTimer0Regs"
|
|
width 6.
|
|
group.long (d:0x00000C00+0x00)++0x03
|
|
line.long 0x00 "TIM,CPU-Timer, Counter Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
group.long (d:0x00000C00+0x02)++0x03
|
|
line.long 0x00 "PRD,CPU-Timer, Period Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word (d:0x00000C00+0x04)++0x01
|
|
line.word 0x00 "TCR,CPU-Timer, Control Register"
|
|
bitfld.word 0x00 15. " TIF ,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x00 14. " TIE ,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x00 11. " FREE ,Emulation modes" "0,1"
|
|
bitfld.word 0x00 10. " SOFT ,Emulation modes" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRB ,Timer reload" "0,1"
|
|
bitfld.word 0x00 4. " TSS ,CPU-Timer stop status bit." "0,1"
|
|
group.word (d:0x00000C00+0x06)++0x01
|
|
line.word 0x00 "TPR,CPU-Timer, Prescale Register"
|
|
hexmask.word 0x00 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
group.word (d:0x00000C00+0x07)++0x01
|
|
line.word 0x00 "TPRH,CPU-Timer, Prescale Register High"
|
|
hexmask.word 0x00 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
width 0x0B
|
|
tree.end
|
|
tree "CpuTimer1Regs"
|
|
width 6.
|
|
group.long (d:0x00000C08+0x00)++0x03
|
|
line.long 0x00 "TIM,CPU-Timer, Counter Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
group.long (d:0x00000C08+0x02)++0x03
|
|
line.long 0x00 "PRD,CPU-Timer, Period Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word (d:0x00000C08+0x04)++0x01
|
|
line.word 0x00 "TCR,CPU-Timer, Control Register"
|
|
bitfld.word 0x00 15. " TIF ,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x00 14. " TIE ,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x00 11. " FREE ,Emulation modes" "0,1"
|
|
bitfld.word 0x00 10. " SOFT ,Emulation modes" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRB ,Timer reload" "0,1"
|
|
bitfld.word 0x00 4. " TSS ,CPU-Timer stop status bit." "0,1"
|
|
group.word (d:0x00000C08+0x06)++0x01
|
|
line.word 0x00 "TPR,CPU-Timer, Prescale Register"
|
|
hexmask.word 0x00 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
group.word (d:0x00000C08+0x07)++0x01
|
|
line.word 0x00 "TPRH,CPU-Timer, Prescale Register High"
|
|
hexmask.word 0x00 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
width 0x0B
|
|
tree.end
|
|
tree "CpuTimer2Regs"
|
|
width 6.
|
|
group.long (d:0x00000C10+0x00)++0x03
|
|
line.long 0x00 "TIM,CPU-Timer, Counter Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Counter Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Counter Registers"
|
|
group.long (d:0x00000C10+0x02)++0x03
|
|
line.long 0x00 "PRD,CPU-Timer, Period Register"
|
|
hexmask.long 0x00 16.--31. 1. "MSW,CPU-Timer Period Registers High"
|
|
hexmask.long 0x00 0.--15. 1. "LSW,CPU-Timer Period Registers"
|
|
group.word (d:0x00000C10+0x04)++0x01
|
|
line.word 0x00 "TCR,CPU-Timer, Control Register"
|
|
bitfld.word 0x00 15. " TIF ,CPU-Timer Interrupt Flag." "0,1"
|
|
bitfld.word 0x00 14. " TIE ,CPU-Timer Interrupt Enable." "0,1"
|
|
bitfld.word 0x00 11. " FREE ,Emulation modes" "0,1"
|
|
bitfld.word 0x00 10. " SOFT ,Emulation modes" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRB ,Timer reload" "0,1"
|
|
bitfld.word 0x00 4. " TSS ,CPU-Timer stop status bit." "0,1"
|
|
group.word (d:0x00000C10+0x06)++0x01
|
|
line.word 0x00 "TPR,CPU-Timer, Prescale Register"
|
|
hexmask.word 0x00 8.--15. 1. "PSC,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDR,CPU-Timer Divide-Down."
|
|
group.word (d:0x00000C10+0x07)++0x01
|
|
line.word 0x00 "TPRH,CPU-Timer, Prescale Register High"
|
|
hexmask.word 0x00 8.--15. 1. "PSCH,CPU-Timer Prescale Counter."
|
|
hexmask.word 0x00 0.--7. 1. "TDDRH,CPU-Timer Divide-Down."
|
|
width 0x0B
|
|
tree.end
|
|
tree "DevCfgRegs"
|
|
width 13.
|
|
group.long (d:0x0005D000+0x00)++0x03
|
|
line.long 0x00 "DEVCFGLOCK1,Lock bit for DEVCFG registers"
|
|
bitfld.long 0x00 25. " CPUSEL25 ,Lock bit for CPUSEL25 register" "0,1"
|
|
bitfld.long 0x00 18. " CPUSEL18 ,Lock bit for CPUSEL18 register" "0,1"
|
|
bitfld.long 0x00 16. " CPUSEL16 ,Lock bit for CPUSEL16 register" "0,1"
|
|
bitfld.long 0x00 15. " CPUSEL15 ,Lock bit for CPUSEL15 register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " CPUSEL14 ,Lock bit for CPUSEL14 register" "0,1"
|
|
bitfld.long 0x00 12. " CPUSEL12 ,Lock bit for CPUSEL12 register" "0,1"
|
|
bitfld.long 0x00 11. " CPUSEL11 ,Lock bit for CPUSEL11 register" "0,1"
|
|
bitfld.long 0x00 9. " CPUSEL9 ,Lock bit for CPUSEL9 register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " CPUSEL8 ,Lock bit for CPUSEL8 register" "0,1"
|
|
bitfld.long 0x00 7. " CPUSEL7 ,Lock bit for CPUSEL7 register" "0,1"
|
|
bitfld.long 0x00 6. " CPUSEL6 ,Lock bit for CPUSEL6 register" "0,1"
|
|
bitfld.long 0x00 5. " CPUSEL5 ,Lock bit for CPUSEL5 register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CPUSEL4 ,Lock bit for CPUSEL4 register" "0,1"
|
|
bitfld.long 0x00 2. " CPUSEL2 ,Lock bit for CPUSEL2 register" "0,1"
|
|
bitfld.long 0x00 1. " CPUSEL1 ,Lock bit for CPUSEL1 register" "0,1"
|
|
bitfld.long 0x00 0. " CPUSEL0 ,Lock bit for CPUSEL0 register" "0,1"
|
|
hgroup.long (d:0x0005D000+0x02)++0x03
|
|
hide.long 0x00 "DEVCFGLOCK2,Lock bit for DEVCFG registers"
|
|
group.long (d:0x0005D000+0x08)++0x03
|
|
line.long 0x00 "PARTIDL,Lower 32-bit of Device PART Identification Number"
|
|
bitfld.long 0x00 28.--31. " PARTID_FORMAT_REVISION ,Revision of the PARTID format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 16.--23. 1. "FLASH_SIZE,Flash size in KB"
|
|
bitfld.long 0x00 13.--14. " INSTASPIN ,Motorware feature set" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. " PIN_COUNT ,Device Pin Count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " QUAL ,Qualification Status" "0,1,2,3"
|
|
group.long (d:0x0005D000+0x0A)++0x03
|
|
line.long 0x00 "PARTIDH,Upper 32-bit of Device PART Identification Number"
|
|
hexmask.long 0x00 24.--31. 1. "DEVICE_CLASS_ID,Device class ID"
|
|
hexmask.long 0x00 16.--23. 1. "PARTNO,Device part number"
|
|
hexmask.long 0x00 8.--15. 1. "FAMILY,Device family"
|
|
rgroup.long (d:0x0005D000+0x0C)++0x03
|
|
line.long 0x00 "REVID,Device Revision Number"
|
|
hexmask.long 0x00 0.--15. 1. "REVID,Device Revision ID. This is specific to the Device"
|
|
group.long (d:0x0005D000+0x60)++0x03
|
|
line.long 0x00 "PERCNF1,Peripheral Configuration register"
|
|
bitfld.long 0x00 16. " USB_A_PHY ,USB_A_PHY enable/disable bit" "0,1"
|
|
bitfld.long 0x00 3. " ADC_D_MODE ,ADC Wrapper-4 mode setting bit" "0,1"
|
|
bitfld.long 0x00 2. " ADC_C_MODE ,ADC Wrapper-3 mode setting bit" "0,1"
|
|
bitfld.long 0x00 1. " ADC_B_MODE ,ADC Wrapper-2 mode setting bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " ADC_A_MODE ,ADC Wrapper-1 mode setting bit" "0,1"
|
|
rgroup.long (d:0x0005D000+0x74)++0x03
|
|
line.long 0x00 "FUSEERR,e-Fuse error Status register"
|
|
bitfld.long 0x00 5. " ERR ,Efuse Self Test Error Status" "0,1"
|
|
bitfld.long 0x00 0.--4. " ALERR ,Efuse Autoload Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x0005D000+0x82)++0x03
|
|
line.long 0x00 "SOFTPRES0,Processing Block Software Reset register"
|
|
bitfld.long 0x00 25. " CPU2_ERAD ,ERAD Module reset bit" "0,1"
|
|
bitfld.long 0x00 24. " CPU1_ERAD ,ERAD Module reset bit" "0,1"
|
|
bitfld.long 0x00 17. " CPU2_CLA1BGCRC ,CLA1BGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x00 16. " CPU2_CPUBGCRC ,CPUBGCRC Module reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " CPU1_CLA1BGCRC ,CLA1BGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x00 13. " CPU1_CPUBGCRC ,CPUBGCRC Module reset bit" "0,1"
|
|
bitfld.long 0x00 2. " CPU2_CLA1 ,CPU2_CLA1 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " CPU1_CLA1 ,CPU1_CLA1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x84)++0x03
|
|
line.long 0x00 "SOFTPRES1,EMIF Software Reset register"
|
|
bitfld.long 0x00 1. " EMIF2 ,EMIF2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " EMIF1 ,EMIF1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x86)++0x03
|
|
line.long 0x00 "SOFTPRES2,Peripheral Software Reset register"
|
|
bitfld.long 0x00 15. " EPWM16 ,EPWM16 software reset bit" "0,1"
|
|
bitfld.long 0x00 14. " EPWM15 ,EPWM15 software reset bit" "0,1"
|
|
bitfld.long 0x00 13. " EPWM14 ,EPWM14 software reset bit" "0,1"
|
|
bitfld.long 0x00 12. " EPWM13 ,EPWM13 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EPWM12 ,EPWM12 software reset bit" "0,1"
|
|
bitfld.long 0x00 10. " EPWM11 ,EPWM11 software reset bit" "0,1"
|
|
bitfld.long 0x00 9. " EPWM10 ,EPWM10 software reset bit" "0,1"
|
|
bitfld.long 0x00 8. " EPWM9 ,EPWM9 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EPWM8 ,EPWM8 software reset bit" "0,1"
|
|
bitfld.long 0x00 6. " EPWM7 ,EPWM7 software reset bit" "0,1"
|
|
bitfld.long 0x00 5. " EPWM6 ,EPWM6 software reset bit" "0,1"
|
|
bitfld.long 0x00 4. " EPWM5 ,EPWM5 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EPWM4 ,EPWM4 software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " EPWM3 ,EPWM3 software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " EPWM2 ,EPWM2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " EPWM1 ,EPWM1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x88)++0x03
|
|
line.long 0x00 "SOFTPRES3,Peripheral Software Reset register"
|
|
bitfld.long 0x00 6. " ECAP7 ,ECAP7 software reset bit" "0,1"
|
|
bitfld.long 0x00 5. " ECAP6 ,ECAP6 software reset bit" "0,1"
|
|
bitfld.long 0x00 4. " ECAP5 ,ECAP5 software reset bit" "0,1"
|
|
bitfld.long 0x00 3. " ECAP4 ,ECAP4 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ECAP3 ,ECAP3 software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " ECAP2 ,ECAP2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " ECAP1 ,ECAP1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x8A)++0x03
|
|
line.long 0x00 "SOFTPRES4,Peripheral Software Reset register"
|
|
bitfld.long 0x00 2. " EQEP3 ,EQEP3 software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " EQEP2 ,EQEP2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " EQEP1 ,EQEP1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x8E)++0x03
|
|
line.long 0x00 "SOFTPRES6,Peripheral Software Reset register"
|
|
bitfld.long 0x00 1. " SD2 ,SD2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " SD1 ,SD1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x90)++0x03
|
|
line.long 0x00 "SOFTPRES7,Peripheral Software Reset register"
|
|
bitfld.long 0x00 3. " SCI_D ,SCI_D software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " SCI_C ,SCI_C software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " SCI_B ,SCI_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " SCI_A ,SCI_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x92)++0x03
|
|
line.long 0x00 "SOFTPRES8,Peripheral Software Reset register"
|
|
bitfld.long 0x00 3. " SPI_D ,SPI_D software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " SPI_C ,SPI_C software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " SPI_B ,SPI_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " SPI_A ,SPI_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x94)++0x03
|
|
line.long 0x00 "SOFTPRES9,Peripheral Software Reset register"
|
|
bitfld.long 0x00 1. " I2C_B ,I2C_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " I2C_A ,I2C_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x96)++0x03
|
|
line.long 0x00 "SOFTPRES10,Peripheral Software Reset register"
|
|
bitfld.long 0x00 1. " CAN_B ,CAN_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " CAN_A ,CAN_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x98)++0x03
|
|
line.long 0x00 "SOFTPRES11,Peripheral Software Reset register"
|
|
bitfld.long 0x00 16. " USB_A ,USB_A software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " McBSP_B ,McBSP_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " McBSP_A ,McBSP_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x9C)++0x03
|
|
line.long 0x00 "SOFTPRES13,Peripheral Software Reset register"
|
|
bitfld.long 0x00 3. " ADC_D ,ADC_D software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " ADC_C ,ADC_C software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " ADC_B ,ADC_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " ADC_A ,ADC_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0x9E)++0x03
|
|
line.long 0x00 "SOFTPRES14,Peripheral Software Reset register"
|
|
bitfld.long 0x00 7. " CMPSS8 ,CMPSS8 software reset bit" "0,1"
|
|
bitfld.long 0x00 6. " CMPSS7 ,CMPSS7 software reset bit" "0,1"
|
|
bitfld.long 0x00 5. " CMPSS6 ,CMPSS6 software reset bit" "0,1"
|
|
bitfld.long 0x00 4. " CMPSS5 ,CMPSS5 software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CMPSS4 ,CMPSS4 software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " CMPSS3 ,CMPSS3 software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " CMPSS2 ,CMPSS2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " CMPSS1 ,CMPSS1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xA2)++0x03
|
|
line.long 0x00 "SOFTPRES16,Peripheral Software Reset register"
|
|
bitfld.long 0x00 18. " DAC_C ,Buffered_DAC12_3 software reset bit" "0,1"
|
|
bitfld.long 0x00 17. " DAC_B ,Buffered_DAC12_2 software reset bit" "0,1"
|
|
bitfld.long 0x00 16. " DAC_A ,Buffered_DAC12_1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xA4)++0x03
|
|
line.long 0x00 "SOFTPRES17,Reserved Peripheral Software Reset register"
|
|
bitfld.long 0x00 3. " CLB4 ,CLB4 software reset bit" "0,1"
|
|
bitfld.long 0x00 2. " CLB3 ,CLB3 software reset bit" "0,1"
|
|
bitfld.long 0x00 1. " CLB2 ,CLB2 software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " CLB1 ,CLB1 software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xA6)++0x03
|
|
line.long 0x00 "SOFTPRES18,Reserved Peripheral Software Reset register"
|
|
bitfld.long 0x00 23. " FSIRX_H ,FSIRX_H software reset bit" "0,1"
|
|
bitfld.long 0x00 22. " FSIRX_G ,FSIRX_G software reset bit" "0,1"
|
|
bitfld.long 0x00 21. " FSIRX_F ,FSIRX_F software reset bit" "0,1"
|
|
bitfld.long 0x00 20. " FSIRX_E ,FSIRX_E software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " FSIRX_D ,FSIRX_D software reset bit" "0,1"
|
|
bitfld.long 0x00 18. " FSIRX_C ,FSIRX_C software reset bit" "0,1"
|
|
bitfld.long 0x00 17. " FSIRX_B ,FSIRX_B software reset bit" "0,1"
|
|
bitfld.long 0x00 16. " FSIRX_A ,FSIRX_A software reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FSITX_B ,FSITX_B software reset bit" "0,1"
|
|
bitfld.long 0x00 0. " FSITX_A ,FSITX_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xAA)++0x03
|
|
line.long 0x00 "SOFTPRES20,Peripheral Software Reset register"
|
|
bitfld.long 0x00 0. " PMBUS_A ,PMBUS_A software reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xAC)++0x03
|
|
line.long 0x00 "SOFTPRES21,Peripheral Software Reset register"
|
|
bitfld.long 0x00 2. " DCC2 ,DCC2 Module reset bit" "0,1"
|
|
bitfld.long 0x00 1. " DCC1 ,DCC1 Module reset bit" "0,1"
|
|
bitfld.long 0x00 0. " DCC0 ,DCC0 Module reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xB0)++0x03
|
|
line.long 0x00 "SOFTPRES23,Peripheral Software Reset register"
|
|
bitfld.long 0x00 0. " ETHERCAT ,ETHERCAT Module reset bit" "0,1"
|
|
group.long (d:0x0005D000+0xD6)++0x03
|
|
line.long 0x00 "CPUSEL0,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 15. " EPWM16 ,EPWM16 CPU select bit" "0,1"
|
|
bitfld.long 0x00 14. " EPWM15 ,EPWM15 CPU select bit" "0,1"
|
|
bitfld.long 0x00 13. " EPWM14 ,EPWM14 CPU select bit" "0,1"
|
|
bitfld.long 0x00 12. " EPWM13 ,EPWM13 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EPWM12 ,EPWM12 CPU select bit" "0,1"
|
|
bitfld.long 0x00 10. " EPWM11 ,EPWM11 CPU select bit" "0,1"
|
|
bitfld.long 0x00 9. " EPWM10 ,EPWM10 CPU select bit" "0,1"
|
|
bitfld.long 0x00 8. " EPWM9 ,EPWM9 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EPWM8 ,EPWM8 CPU select bit" "0,1"
|
|
bitfld.long 0x00 6. " EPWM7 ,EPWM7 CPU select bit" "0,1"
|
|
bitfld.long 0x00 5. " EPWM6 ,EPWM6 CPU select bit" "0,1"
|
|
bitfld.long 0x00 4. " EPWM5 ,EPWM5 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EPWM4 ,EPWM4 CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " EPWM3 ,EPWM3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " EPWM2 ,EPWM2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " EPWM1 ,EPWM1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xD8)++0x03
|
|
line.long 0x00 "CPUSEL1,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 6. " ECAP7 ,ECAP7 CPU select bit" "0,1"
|
|
bitfld.long 0x00 5. " ECAP6 ,ECAP6 CPU select bit" "0,1"
|
|
bitfld.long 0x00 4. " ECAP5 ,ECAP5 CPU select bit" "0,1"
|
|
bitfld.long 0x00 3. " ECAP4 ,ECAP4 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ECAP3 ,ECAP3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " ECAP2 ,ECAP2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " ECAP1 ,ECAP1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xDA)++0x03
|
|
line.long 0x00 "CPUSEL2,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 2. " EQEP3 ,EQEP3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " EQEP2 ,EQEP2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " EQEP1 ,EQEP1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xDE)++0x03
|
|
line.long 0x00 "CPUSEL4,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 1. " SD2 ,SD2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " SD1 ,SD1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xE0)++0x03
|
|
line.long 0x00 "CPUSEL5,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 3. " SCI_D ,SCI_D CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " SCI_C ,SCI_C CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " SCI_B ,SCI_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " SCI_A ,SCI_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xE2)++0x03
|
|
line.long 0x00 "CPUSEL6,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 3. " SPI_D ,SPI_D CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " SPI_C ,SPI_C CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " SPI_B ,SPI_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " SPI_A ,SPI_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xE4)++0x03
|
|
line.long 0x00 "CPUSEL7,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 1. " I2C_B ,I2C_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " I2C_A ,I2C_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xE6)++0x03
|
|
line.long 0x00 "CPUSEL8,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 1. " CAN_B ,CAN_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " CAN_A ,CAN_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xE8)++0x03
|
|
line.long 0x00 "CPUSEL9,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 1. " McBSP_B ,McBSP_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " McBSP_A ,McBSP_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xEC)++0x03
|
|
line.long 0x00 "CPUSEL11,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 3. " ADC_D ,ADC_D CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " ADC_C ,ADC_C CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " ADC_B ,ADC_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " ADC_A ,ADC_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xEE)++0x03
|
|
line.long 0x00 "CPUSEL12,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 7. " CMPSS8 ,CMPSS8 CPU select bit" "0,1"
|
|
bitfld.long 0x00 6. " CMPSS7 ,CMPSS7 CPU select bit" "0,1"
|
|
bitfld.long 0x00 5. " CMPSS6 ,CMPSS6 CPU select bit" "0,1"
|
|
bitfld.long 0x00 4. " CMPSS5 ,CMPSS5 CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CMPSS4 ,CMPSS4 CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " CMPSS3 ,CMPSS3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " CMPSS2 ,CMPSS2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " CMPSS1 ,CMPSS1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xF2)++0x03
|
|
line.long 0x00 "CPUSEL14,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 18. " DAC_C ,Buffered_DAC12_3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 17. " DAC_B ,Buffered_DAC12_2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 16. " DAC_A ,Buffered_DAC12_1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xF4)++0x03
|
|
line.long 0x00 "CPUSEL15,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 3. " CLB4 ,CLB4 CPU select bit" "0,1"
|
|
bitfld.long 0x00 2. " CLB3 ,CLB3 CPU select bit" "0,1"
|
|
bitfld.long 0x00 1. " CLB2 ,CLB2 CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " CLB1 ,CLB1 CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xF6)++0x03
|
|
line.long 0x00 "CPUSEL16,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 23. " FSIRX_H ,FSIRX_H CPU select bit" "0,1"
|
|
bitfld.long 0x00 22. " FSIRX_G ,FSIRX_G CPU select bit" "0,1"
|
|
bitfld.long 0x00 21. " FSIRX_F ,FSIRX_F CPU select bit" "0,1"
|
|
bitfld.long 0x00 20. " FSIRX_E ,FSIRX_E CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " FSIRX_D ,FSIRX_D CPU select bit" "0,1"
|
|
bitfld.long 0x00 18. " FSIRX_C ,FSIRX_C CPU select bit" "0,1"
|
|
bitfld.long 0x00 17. " FSIRX_B ,FSIRX_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 16. " FSIRX_A ,FSIRX_A CPU select bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FSITX_B ,FSITX_B CPU select bit" "0,1"
|
|
bitfld.long 0x00 0. " FSITX_A ,FSITX_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0xFA)++0x03
|
|
line.long 0x00 "CPUSEL18,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 0. " PMBUS_A ,PMBUS_A CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0x108)++0x03
|
|
line.long 0x00 "CPUSEL25,CPU Select register for common peripherals"
|
|
bitfld.long 0x00 0. " HRCAL ,HRCAL CPU select bit" "0,1"
|
|
group.long (d:0x0005D000+0x122)++0x03
|
|
line.long 0x00 "CPU2RESCTL,CPU2 Reset Control Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x00 0. " RESET ,CPU2 Reset Control bit" "0,1"
|
|
group.word (d:0x0005D000+0x124)++0x01
|
|
line.word 0x00 "RSTSTAT,Reset Status register for secondary C28x CPUs"
|
|
bitfld.word 0x00 2.--3. " CPU2HWBISTRST ,Tells whether a HWBIST reset was issued to CPU2 or not" "0,1,2,3"
|
|
bitfld.word 0x00 1. " CPU2NMIWDRST ,Tells whether a CPU2.NMIWD reset was issued to CPU2 or not" "0,1"
|
|
rbitfld.word 0x00 0. " CPU2RES ,CPU2 Reset Status bit" "0,1"
|
|
rgroup.word (d:0x0005D000+0x125)++0x01
|
|
line.word 0x00 "LPMSTAT,LPM Status Register for secondary C28x CPUs"
|
|
bitfld.word 0x00 0.--1. " CPU2LPMSTAT ,CPU2 LPM Status" "0,1,2,3"
|
|
group.long (d:0x0005D000+0x184)++0x03
|
|
line.long 0x00 "BANKSEL,Configures the bank to programmed by CPU1."
|
|
bitfld.long 0x00 0.--1. " SEL ,Selects the BANK to be programmed by CPU1 FMC." "0,1,2,3"
|
|
group.word (d:0x0005D000+0x19A)++0x01
|
|
line.word 0x00 "USBTYPE,Configures USB Type for the device"
|
|
bitfld.word 0x00 15. " LOCK ,Lock bit" "0,1"
|
|
bitfld.word 0x00 0.--1. " TYPE ,Configure USB type" "0,1,2,3"
|
|
group.word (d:0x0005D000+0x19B)++0x01
|
|
line.word 0x00 "ECAPTYPE,Configures ECAP Type for the device"
|
|
bitfld.word 0x00 15. " LOCK ,Lock bit" "0,1"
|
|
bitfld.word 0x00 0.--1. " TYPE ,Configure ECAP type" "0,1,2,3"
|
|
group.word (d:0x0005D000+0x19C)++0x01
|
|
line.word 0x00 "SDFMTYPE,Configures SDFM Type for the device"
|
|
bitfld.word 0x00 15. " LOCK ,Lock bit" "0,1"
|
|
bitfld.word 0x00 0.--1. " TYPE ,Configure SDFM type" "0,1,2,3"
|
|
group.word (d:0x0005D000+0x19E)++0x01
|
|
line.word 0x00 "MEMMAPTYPE,Configures Memory Map Type for the device"
|
|
bitfld.word 0x00 15. " LOCK ,Lock bit" "0,1"
|
|
bitfld.word 0x00 0.--1. " TYPE ,Configures system specific features related to memory map." "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DmaClaSrcSelRegs"
|
|
width 20.
|
|
group.long (d:0x00007980+0x00)++0x03
|
|
line.long 0x00 "CLA1TASKSRCSELLOCK,CLA1 Task Trigger Source Select Lock Register"
|
|
bitfld.long 0x00 1. " CLA1TASKSRCSEL2 ,CLA1TASKSRCSEL2 Register Lock bit" "0,1"
|
|
bitfld.long 0x00 0. " CLA1TASKSRCSEL1 ,CLA1TASKSRCSEL1 Register Lock bit" "0,1"
|
|
group.long (d:0x00007980+0x04)++0x03
|
|
line.long 0x00 "DMACHSRCSELLOCK,DMA Channel Triger Source Select Lock Register"
|
|
bitfld.long 0x00 1. " DMACHSRCSEL2 ,DMACHSRCSEL2 Register Lock bit" "0,1"
|
|
bitfld.long 0x00 0. " DMACHSRCSEL1 ,DMACHSRCSEL1 Register Lock bit" "0,1"
|
|
group.long (d:0x00007980+0x06)++0x03
|
|
line.long 0x00 "CLA1TASKSRCSEL1,CLA1 Task Trigger Source Select Register-1"
|
|
hexmask.long 0x00 24.--31. 1. "TASK4,Selects the Trigger Source for TASK4 of CLA1"
|
|
hexmask.long 0x00 16.--23. 1. "TASK3,Selects the Trigger Source for TASK3 of CLA1"
|
|
hexmask.long 0x00 8.--15. 1. "TASK2,Selects the Trigger Source for TASK2 of CLA1"
|
|
hexmask.long 0x00 0.--7. 1. "TASK1,Selects the Trigger Source for TASK1 of CLA1"
|
|
group.long (d:0x00007980+0x08)++0x03
|
|
line.long 0x00 "CLA1TASKSRCSEL2,CLA1 Task Trigger Source Select Register-2"
|
|
hexmask.long 0x00 24.--31. 1. "TASK8,Selects the Trigger Source for TASK8 of CLA1"
|
|
hexmask.long 0x00 16.--23. 1. "TASK7,Selects the Trigger Source for TASK7 of CLA1"
|
|
hexmask.long 0x00 8.--15. 1. "TASK6,Selects the Trigger Source for TASK6 of CLA1"
|
|
hexmask.long 0x00 0.--7. 1. "TASK5,Selects the Trigger Source for TASK5 of CLA1"
|
|
group.long (d:0x00007980+0x16)++0x03
|
|
line.long 0x00 "DMACHSRCSEL1,DMA Channel Trigger Source Select Register-1"
|
|
hexmask.long 0x00 24.--31. 1. "CH4,Selects the Trigger and Sync Source CH4 of DMA"
|
|
hexmask.long 0x00 16.--23. 1. "CH3,Selects the Trigger and Sync Source CH3 of DMA"
|
|
hexmask.long 0x00 8.--15. 1. "CH2,Selects the Trigger and Sync Source CH2 of DMA"
|
|
hexmask.long 0x00 0.--7. 1. "CH1,Selects the Trigger and Sync Source CH1 of DMA"
|
|
group.long (d:0x00007980+0x18)++0x03
|
|
line.long 0x00 "DMACHSRCSEL2,DMA Channel Trigger Source Select Register-2"
|
|
hexmask.long 0x00 8.--15. 1. "CH6,Selects the Trigger and Sync Source CH6 of DMA"
|
|
hexmask.long 0x00 0.--7. 1. "CH5,Selects the Trigger and Sync Source CH5 of DMA"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MemCfgRegs"
|
|
width 23.
|
|
group.long (d:0x0005F400+0x00)++0x03
|
|
line.long 0x00 "DxLOCK,Dedicated RAM Config Lock Register"
|
|
bitfld.long 0x00 3. " LOCK_D1 ,D1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_D0 ,D0 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_M1 ,M1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_M0 ,M0 RAM Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x02)++0x03
|
|
line.long 0x00 "DxCOMMIT,Dedicated RAM Config Lock Commit Register"
|
|
bitfld.long 0x00 3. " COMMIT_D1 ,D1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " COMMIT_D0 ,D0 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " COMMIT_M1 ,M1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " COMMIT_M0 ,M0 RAM Permanent Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x08)++0x03
|
|
line.long 0x00 "DxACCPROT0,Dedicated RAM Config Register"
|
|
bitfld.long 0x00 25. " CPUWRPROT_D1 ,CPU WR Protection For D1 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_D1 ,Fetch Protection For D1 RAM" "0,1"
|
|
bitfld.long 0x00 17. " CPUWRPROT_D0 ,CPU WR Protection For D0 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_D0 ,Fetch Protection For D0 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CPUWRPROT_M1 ,CPU WR Protection For M1 RAM" "0,1"
|
|
bitfld.long 0x00 8. " FETCHPROT_M1 ,Fetch Protection For M1 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_M0 ,CPU WR Protection For M0 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_M0 ,Fetch Protection For M0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x10)++0x03
|
|
line.long 0x00 "DxTEST,Dedicated RAM TEST Register"
|
|
bitfld.long 0x00 6.--7. " TEST_D1 ,Selects the different modes for D1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_D0 ,Selects the different modes for D0 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_M1 ,Selects the different modes for M1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_M0 ,Selects the different modes for M0 RAM" "0,1,2,3"
|
|
group.long (d:0x0005F400+0x12)++0x03
|
|
line.long 0x00 "DxINIT,Dedicated RAM Init Register"
|
|
bitfld.long 0x00 3. " INIT_D1 ,RAM Initialization control for D1 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INIT_D0 ,RAM Initialization control for D0 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INIT_M1 ,RAM Initialization control for M1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INIT_M0 ,RAM Initialization control for M0 RAM." "0,1"
|
|
rgroup.long (d:0x0005F400+0x14)++0x03
|
|
line.long 0x00 "DxINITDONE,Dedicated RAM InitDone Status Register"
|
|
bitfld.long 0x00 3. " INITDONE_D1 ,RAM Initialization status for D1 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_D0 ,RAM Initialization status for D0 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_M1 ,RAM Initialization status for M1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_M0 ,RAM Initialization status for M0 RAM." "0,1"
|
|
group.long (d:0x0005F400+0x16)++0x03
|
|
line.long 0x00 "DxRAMTEST_LOCK,Lock register to Dx RAM TEST registers"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 3. " D1 ,DxTEST.TEST_D1 LOCK" "0,1"
|
|
bitfld.long 0x00 2. " D0 ,DxTEST.TEST_D0 LOCK" "0,1"
|
|
bitfld.long 0x00 1. " M1 ,DxTEST.TEST_M1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " M0 ,DxTEST.TEST_M0 LOCK" "0,1"
|
|
group.long (d:0x0005F400+0x20)++0x03
|
|
line.long 0x00 "LSxLOCK,Local Shared RAM Config Lock Register"
|
|
bitfld.long 0x00 7. " LOCK_LS7 ,LS7 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 6. " LOCK_LS6 ,LS6 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 5. " LOCK_LS5 ,LS5 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 4. " LOCK_LS4 ,LS4 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " LOCK_LS3 ,LS3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_LS2 ,LS2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_LS1 ,LS1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_LS0 ,LS0 RAM Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x22)++0x03
|
|
line.long 0x00 "LSxCOMMIT,Local Shared RAM Config Lock Commit Register"
|
|
bitfld.long 0x00 7. " COMMIT_LS7 ,LS7 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 6. " COMMIT_LS6 ,LS6 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 5. " COMMIT_LS5 ,LS5 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 4. " COMMIT_LS4 ,LS4 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " COMMIT_LS3 ,LS3 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " COMMIT_LS2 ,LS2 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " COMMIT_LS1 ,LS1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " COMMIT_LS0 ,LS0 RAM Permanent Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x24)++0x03
|
|
line.long 0x00 "LSxMSEL,Local Shared RAM Master Sel Register"
|
|
bitfld.long 0x00 14.--15. " MSEL_LS7 ,Master Select for LS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MSEL_LS6 ,Master Select for LS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MSEL_LS5 ,Master Select for LS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MSEL_LS4 ,Master Select for LS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MSEL_LS3 ,Master Select for LS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MSEL_LS2 ,Master Select for LS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MSEL_LS1 ,Master Select for LS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MSEL_LS0 ,Master Select for LS0 RAM" "0,1,2,3"
|
|
group.long (d:0x0005F400+0x26)++0x03
|
|
line.long 0x00 "LSxCLAPGM,Local Shared RAM Prog/Exe control Register"
|
|
bitfld.long 0x00 7. " CLAPGM_LS7 ,Selects LS7 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 6. " CLAPGM_LS6 ,Selects LS6 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 5. " CLAPGM_LS5 ,Selects LS5 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 4. " CLAPGM_LS4 ,Selects LS4 RAM as program vs data memory for CLA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CLAPGM_LS3 ,Selects LS3 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 2. " CLAPGM_LS2 ,Selects LS2 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 1. " CLAPGM_LS1 ,Selects LS1 RAM as program vs data memory for CLA" "0,1"
|
|
bitfld.long 0x00 0. " CLAPGM_LS0 ,Selects LS0 RAM as program vs data memory for CLA" "0,1"
|
|
group.long (d:0x0005F400+0x28)++0x03
|
|
line.long 0x00 "LSxACCPROT0,Local Shared RAM Config Register 0"
|
|
bitfld.long 0x00 25. " CPUWRPROT_LS3 ,CPU WR Protection For LS3 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_LS3 ,Fetch Protection For LS3 RAM" "0,1"
|
|
bitfld.long 0x00 17. " CPUWRPROT_LS2 ,CPU WR Protection For LS2 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_LS2 ,Fetch Protection For LS2 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CPUWRPROT_LS1 ,CPU WR Protection For LS1 RAM" "0,1"
|
|
bitfld.long 0x00 8. " FETCHPROT_LS1 ,Fetch Protection For LS1 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_LS0 ,CPU WR Protection For LS0 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_LS0 ,Fetch Protection For LS0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x2A)++0x03
|
|
line.long 0x00 "LSxACCPROT1,Local Shared RAM Config Register 1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_LS7 ,CPU WR Protection For LS7 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_LS7 ,Fetch Protection For LS7 RAM" "0,1"
|
|
bitfld.long 0x00 17. " CPUWRPROT_LS6 ,CPU WR Protection For LS6 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_LS6 ,Fetch Protection For LS6 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CPUWRPROT_LS5 ,CPU WR Protection For LS5 RAM" "0,1"
|
|
bitfld.long 0x00 8. " FETCHPROT_LS5 ,Fetch Protection For LS5 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_LS4 ,CPU WR Protection For LS4 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_LS4 ,Fetch Protection For LS4 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x30)++0x03
|
|
line.long 0x00 "LSxTEST,Local Shared RAM TEST Register"
|
|
bitfld.long 0x00 14.--15. " TEST_LS7 ,Selects the different modes for LS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TEST_LS6 ,Selects the different modes for LS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TEST_LS5 ,Selects the different modes for LS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TEST_LS4 ,Selects the different modes for LS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TEST_LS3 ,Selects the different modes for LS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_LS2 ,Selects the different modes for LS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_LS1 ,Selects the different modes for LS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_LS0 ,Selects the different modes for LS0 RAM" "0,1,2,3"
|
|
group.long (d:0x0005F400+0x32)++0x03
|
|
line.long 0x00 "LSxINIT,Local Shared RAM Init Register"
|
|
bitfld.long 0x00 7. " INIT_LS7 ,RAM Initialization control for LS7 RAM." "0,1"
|
|
bitfld.long 0x00 6. " INIT_LS6 ,RAM Initialization control for LS6 RAM." "0,1"
|
|
bitfld.long 0x00 5. " INIT_LS5 ,RAM Initialization control for LS5 RAM." "0,1"
|
|
bitfld.long 0x00 4. " INIT_LS4 ,RAM Initialization control for LS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INIT_LS3 ,RAM Initialization control for LS3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INIT_LS2 ,RAM Initialization control for LS2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INIT_LS1 ,RAM Initialization control for LS1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INIT_LS0 ,RAM Initialization control for LS0 RAM." "0,1"
|
|
rgroup.long (d:0x0005F400+0x34)++0x03
|
|
line.long 0x00 "LSxINITDONE,Local Shared RAM InitDone Status Register"
|
|
bitfld.long 0x00 7. " INITDONE_LS7 ,RAM Initialization status for LS7 RAM." "0,1"
|
|
bitfld.long 0x00 6. " INITDONE_LS6 ,RAM Initialization status for LS6 RAM." "0,1"
|
|
bitfld.long 0x00 5. " INITDONE_LS5 ,RAM Initialization status for LS5 RAM." "0,1"
|
|
bitfld.long 0x00 4. " INITDONE_LS4 ,RAM Initialization status for LS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INITDONE_LS3 ,RAM Initialization status for LS3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_LS2 ,RAM Initialization status for LS2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_LS1 ,RAM Initialization status for LS1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_LS0 ,RAM Initialization status for LS0 RAM." "0,1"
|
|
group.long (d:0x0005F400+0x36)++0x03
|
|
line.long 0x00 "LSxRAMTEST_LOCK,Lock register to LSx RAM TEST registers"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 7. " LS7 ,LSxTEST.TEST_LS7 LOCK" "0,1"
|
|
bitfld.long 0x00 6. " LS6 ,LSxTEST.TEST_LS6 LOCK" "0,1"
|
|
bitfld.long 0x00 5. " LS5 ,LSxTEST.TEST_LS5 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " LS4 ,LSxTEST.TEST_LS4 LOCK" "0,1"
|
|
bitfld.long 0x00 3. " LS3 ,LSxTEST.TEST_LS3 LOCK" "0,1"
|
|
bitfld.long 0x00 2. " LS2 ,LSxTEST.TEST_LS2 LOCK" "0,1"
|
|
bitfld.long 0x00 1. " LS1 ,LSxTEST.TEST_LS1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " LS0 ,LSxTEST.TEST_LS0 LOCK" "0,1"
|
|
group.long (d:0x0005F400+0x40)++0x03
|
|
line.long 0x00 "GSxLOCK,Global Shared RAM Config Lock Register"
|
|
bitfld.long 0x00 15. " LOCK_GS15 ,GS15 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 14. " LOCK_GS14 ,GS14 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 13. " LOCK_GS13 ,GS13 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 12. " LOCK_GS12 ,GS12 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " LOCK_GS11 ,GS11 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 10. " LOCK_GS10 ,GS10 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 9. " LOCK_GS9 ,GS9 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 8. " LOCK_GS8 ,GS8 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " LOCK_GS7 ,GS7 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 6. " LOCK_GS6 ,GS6 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 5. " LOCK_GS5 ,GS5 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 4. " LOCK_GS4 ,GS4 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " LOCK_GS3 ,GS3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_GS2 ,GS2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_GS1 ,GS1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_GS0 ,GS0 RAM Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x42)++0x03
|
|
line.long 0x00 "GSxCOMMIT,Global Shared RAM Config Lock Commit Register"
|
|
bitfld.long 0x00 15. " COMMIT_GS15 ,GS15 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 14. " COMMIT_GS14 ,GS14 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 13. " COMMIT_GS13 ,GS13 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 12. " COMMIT_GS12 ,GS12 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " COMMIT_GS11 ,GS11 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 10. " COMMIT_GS10 ,GS10 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 9. " COMMIT_GS9 ,GS9 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 8. " COMMIT_GS8 ,GS8 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " COMMIT_GS7 ,GS7 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 6. " COMMIT_GS6 ,GS6 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 5. " COMMIT_GS5 ,GS5 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 4. " COMMIT_GS4 ,GS4 RAM Permanent Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " COMMIT_GS3 ,GS3 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " COMMIT_GS2 ,GS2 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " COMMIT_GS1 ,GS1 RAM Permanent Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " COMMIT_GS0 ,GS0 RAM Permanent Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x44)++0x03
|
|
line.long 0x00 "GSxMSEL,Global Shared RAM Master Sel Register"
|
|
bitfld.long 0x00 15. " MSEL_GS15 ,Master Select for GS15 RAM" "0,1"
|
|
bitfld.long 0x00 14. " MSEL_GS14 ,Master Select for GS14 RAM" "0,1"
|
|
bitfld.long 0x00 13. " MSEL_GS13 ,Master Select for GS13 RAM" "0,1"
|
|
bitfld.long 0x00 12. " MSEL_GS12 ,Master Select for GS12 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MSEL_GS11 ,Master Select for GS11 RAM" "0,1"
|
|
bitfld.long 0x00 10. " MSEL_GS10 ,Master Select for GS10 RAM" "0,1"
|
|
bitfld.long 0x00 9. " MSEL_GS9 ,Master Select for GS9 RAM" "0,1"
|
|
bitfld.long 0x00 8. " MSEL_GS8 ,Master Select for GS8 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MSEL_GS7 ,Master Select for GS7 RAM" "0,1"
|
|
bitfld.long 0x00 6. " MSEL_GS6 ,Master Select for GS6 RAM" "0,1"
|
|
bitfld.long 0x00 5. " MSEL_GS5 ,Master Select for GS5 RAM" "0,1"
|
|
bitfld.long 0x00 4. " MSEL_GS4 ,Master Select for GS4 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MSEL_GS3 ,Master Select for GS3 RAM" "0,1"
|
|
bitfld.long 0x00 2. " MSEL_GS2 ,Master Select for GS2 RAM" "0,1"
|
|
bitfld.long 0x00 1. " MSEL_GS1 ,Master Select for GS1 RAM" "0,1"
|
|
bitfld.long 0x00 0. " MSEL_GS0 ,Master Select for GS0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x48)++0x03
|
|
line.long 0x00 "GSxACCPROT0,Global Shared RAM Access Protection Register 0"
|
|
bitfld.long 0x00 26. " DMAWRPROT_GS3 ,DMA WR Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_GS3 ,CPU WR Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_GS3 ,Fetch Protection For GS3 RAM" "0,1"
|
|
bitfld.long 0x00 18. " DMAWRPROT_GS2 ,DMA WR Protection For GS2 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " CPUWRPROT_GS2 ,CPU WR Protection For GS2 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_GS2 ,Fetch Protection For GS2 RAM" "0,1"
|
|
bitfld.long 0x00 10. " DMAWRPROT_GS1 ,DMA WR Protection For GS1 RAM" "0,1"
|
|
bitfld.long 0x00 9. " CPUWRPROT_GS1 ,CPU WR Protection For GS1 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " FETCHPROT_GS1 ,Fetch Protection For GS1 RAM" "0,1"
|
|
bitfld.long 0x00 2. " DMAWRPROT_GS0 ,DMA WR Protection For GS0 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_GS0 ,CPU WR Protection For GS0 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_GS0 ,Fetch Protection For GS0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x4A)++0x03
|
|
line.long 0x00 "GSxACCPROT1,Global Shared RAM Access Protection Register 1"
|
|
bitfld.long 0x00 26. " DMAWRPROT_GS7 ,DMA WR Protection For GS7RAM" "0,1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_GS7 ,CPU WR Protection For GS7 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_GS7 ,Fetch Protection For GS7 RAM" "0,1"
|
|
bitfld.long 0x00 18. " DMAWRPROT_GS6 ,DMA WR Protection For GS6RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " CPUWRPROT_GS6 ,CPU WR Protection For GS6 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_GS6 ,Fetch Protection For GS6 RAM" "0,1"
|
|
bitfld.long 0x00 10. " DMAWRPROT_GS5 ,DMA WR Protection For GS5RAM" "0,1"
|
|
bitfld.long 0x00 9. " CPUWRPROT_GS5 ,CPU WR Protection For GS5 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " FETCHPROT_GS5 ,Fetch Protection For GS5 RAM" "0,1"
|
|
bitfld.long 0x00 2. " DMAWRPROT_GS4 ,DMA WR Protection For GS4 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_GS4 ,CPU WR Protection For GS4 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_GS4 ,Fetch Protection For GS4 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x4C)++0x03
|
|
line.long 0x00 "GSxACCPROT2,Global Shared RAM Access Protection Register 2"
|
|
bitfld.long 0x00 26. " DMAWRPROT_GS11 ,DMA WR Protection For GS11RAM" "0,1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_GS11 ,CPU WR Protection For GS11 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_GS11 ,Fetch Protection For GS11 RAM" "0,1"
|
|
bitfld.long 0x00 18. " DMAWRPROT_GS10 ,DMA WR Protection For GS10RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " CPUWRPROT_GS10 ,CPU WR Protection For GS10 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_GS10 ,Fetch Protection For GS10 RAM" "0,1"
|
|
bitfld.long 0x00 10. " DMAWRPROT_GS9 ,DMA WR Protection For GS9RAM" "0,1"
|
|
bitfld.long 0x00 9. " CPUWRPROT_GS9 ,CPU WR Protection For GS9 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " FETCHPROT_GS9 ,Fetch Protection For GS9 RAM" "0,1"
|
|
bitfld.long 0x00 2. " DMAWRPROT_GS8 ,DMA WR Protection For GS8 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_GS8 ,CPU WR Protection For GS8 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_GS8 ,Fetch Protection For GS8 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x4E)++0x03
|
|
line.long 0x00 "GSxACCPROT3,Global Shared RAM Access Protection Register 3"
|
|
bitfld.long 0x00 26. " DMAWRPROT_GS15 ,DMA WR Protection For GS15RAM" "0,1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_GS15 ,CPU WR Protection For GS15 RAM" "0,1"
|
|
bitfld.long 0x00 24. " FETCHPROT_GS15 ,Fetch Protection For GS15 RAM" "0,1"
|
|
bitfld.long 0x00 18. " DMAWRPROT_GS14 ,DMA WR Protection For GS14RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " CPUWRPROT_GS14 ,CPU WR Protection For GS14 RAM" "0,1"
|
|
bitfld.long 0x00 16. " FETCHPROT_GS14 ,Fetch Protection For GS14 RAM" "0,1"
|
|
bitfld.long 0x00 10. " DMAWRPROT_GS13 ,DMA WR Protection For GS13RAM" "0,1"
|
|
bitfld.long 0x00 9. " CPUWRPROT_GS13 ,CPU WR Protection For GS13 RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " FETCHPROT_GS13 ,Fetch Protection For GS13 RAM" "0,1"
|
|
bitfld.long 0x00 2. " DMAWRPROT_GS12 ,DMA WR Protection For GS12 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_GS12 ,CPU WR Protection For GS12 RAM" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_GS12 ,Fetch Protection For GS12 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x50)++0x03
|
|
line.long 0x00 "GSxTEST,Global Shared RAM TEST Register"
|
|
bitfld.long 0x00 30.--31. " TEST_GS15 ,Selects the different modes for GS15 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " TEST_GS14 ,Selects the different modes for GS14 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " TEST_GS13 ,Selects the different modes for GS13 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " TEST_GS12 ,Selects the different modes for GS12 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " TEST_GS11 ,Selects the different modes for GS11 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TEST_GS10 ,Selects the different modes for GS10 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " TEST_GS9 ,Selects the different modes for GS9 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TEST_GS8 ,Selects the different modes for GS8 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TEST_GS7 ,Selects the different modes for GS7 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TEST_GS6 ,Selects the different modes for GS6 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TEST_GS5 ,Selects the different modes for GS5 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TEST_GS4 ,Selects the different modes for GS4 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TEST_GS3 ,Selects the different modes for GS3 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_GS2 ,Selects the different modes for GS2 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_GS1 ,Selects the different modes for GS1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_GS0 ,Selects the different modes for GS0 RAM" "0,1,2,3"
|
|
group.long (d:0x0005F400+0x52)++0x03
|
|
line.long 0x00 "GSxINIT,Global Shared RAM Init Register"
|
|
bitfld.long 0x00 15. " INIT_GS15 ,RAM Initialization control for GS15 RAM." "0,1"
|
|
bitfld.long 0x00 14. " INIT_GS14 ,RAM Initialization control for GS14 RAM." "0,1"
|
|
bitfld.long 0x00 13. " INIT_GS13 ,RAM Initialization control for GS13 RAM." "0,1"
|
|
bitfld.long 0x00 12. " INIT_GS12 ,RAM Initialization control for GS12 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " INIT_GS11 ,RAM Initialization control for GS11 RAM." "0,1"
|
|
bitfld.long 0x00 10. " INIT_GS10 ,RAM Initialization control for GS10 RAM." "0,1"
|
|
bitfld.long 0x00 9. " INIT_GS9 ,RAM Initialization control for GS9 RAM." "0,1"
|
|
bitfld.long 0x00 8. " INIT_GS8 ,RAM Initialization control for GS8 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " INIT_GS7 ,RAM Initialization control for GS7 RAM." "0,1"
|
|
bitfld.long 0x00 6. " INIT_GS6 ,RAM Initialization control for GS6 RAM." "0,1"
|
|
bitfld.long 0x00 5. " INIT_GS5 ,RAM Initialization control for GS5 RAM." "0,1"
|
|
bitfld.long 0x00 4. " INIT_GS4 ,RAM Initialization control for GS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INIT_GS3 ,RAM Initialization control for GS3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INIT_GS2 ,RAM Initialization control for GS2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INIT_GS1 ,RAM Initialization control for GS1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INIT_GS0 ,RAM Initialization control for GS0 RAM." "0,1"
|
|
rgroup.long (d:0x0005F400+0x54)++0x03
|
|
line.long 0x00 "GSxINITDONE,Global Shared RAM InitDone Status Register"
|
|
bitfld.long 0x00 15. " INITDONE_GS15 ,RAM Initialization status for GS15 RAM." "0,1"
|
|
bitfld.long 0x00 14. " INITDONE_GS14 ,RAM Initialization status for GS14 RAM." "0,1"
|
|
bitfld.long 0x00 13. " INITDONE_GS13 ,RAM Initialization status for GS13 RAM." "0,1"
|
|
bitfld.long 0x00 12. " INITDONE_GS12 ,RAM Initialization status for GS12 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " INITDONE_GS11 ,RAM Initialization status for GS11 RAM." "0,1"
|
|
bitfld.long 0x00 10. " INITDONE_GS10 ,RAM Initialization status for GS10 RAM." "0,1"
|
|
bitfld.long 0x00 9. " INITDONE_GS9 ,RAM Initialization status for GS9 RAM." "0,1"
|
|
bitfld.long 0x00 8. " INITDONE_GS8 ,RAM Initialization status for GS8 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " INITDONE_GS7 ,RAM Initialization status for GS7 RAM." "0,1"
|
|
bitfld.long 0x00 6. " INITDONE_GS6 ,RAM Initialization status for GS6 RAM." "0,1"
|
|
bitfld.long 0x00 5. " INITDONE_GS5 ,RAM Initialization status for GS5 RAM." "0,1"
|
|
bitfld.long 0x00 4. " INITDONE_GS4 ,RAM Initialization status for GS4 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INITDONE_GS3 ,RAM Initialization status for GS3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_GS2 ,RAM Initialization status for GS2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_GS1 ,RAM Initialization status for GS1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_GS0 ,RAM Initialization status for GS0 RAM." "0,1"
|
|
group.long (d:0x0005F400+0x56)++0x03
|
|
line.long 0x00 "GSxRAMTEST_LOCK,Lock register to GSx RAM TEST registers"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 15. " GS15 ,GSxTEST.TEST_GS15 LOCK" "0,1"
|
|
bitfld.long 0x00 14. " GS14 ,GSxTEST.TEST_GS14 LOCK" "0,1"
|
|
bitfld.long 0x00 13. " GS13 ,GSxTEST.TEST_GS13 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " GS12 ,GSxTEST.TEST_GS12 LOCK" "0,1"
|
|
bitfld.long 0x00 11. " GS11 ,GSxTEST.TEST_GS11 LOCK" "0,1"
|
|
bitfld.long 0x00 10. " GS10 ,GSxTEST.TEST_GS10 LOCK" "0,1"
|
|
bitfld.long 0x00 9. " GS9 ,GSxTEST.TEST_GS9 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " GS8 ,GSxTEST.TEST_GS8 LOCK" "0,1"
|
|
bitfld.long 0x00 7. " GS7 ,GSxTEST.TEST_GS7 LOCK" "0,1"
|
|
bitfld.long 0x00 6. " GS6 ,GSxTEST.TEST_GS6 LOCK" "0,1"
|
|
bitfld.long 0x00 5. " GS5 ,GSxTEST.TEST_GS5 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GS4 ,GSxTEST.TEST_GS4 LOCK" "0,1"
|
|
bitfld.long 0x00 3. " GS3 ,GSxTEST.TEST_GS3 LOCK" "0,1"
|
|
bitfld.long 0x00 2. " GS2 ,GSxTEST.TEST_GS2 LOCK" "0,1"
|
|
bitfld.long 0x00 1. " GS1 ,GSxTEST.TEST_GS1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GS0 ,GSxTEST.TEST_GS0 LOCK" "0,1"
|
|
group.long (d:0x0005F400+0x60)++0x03
|
|
line.long 0x00 "MSGxLOCK,Message RAM Config Lock Register"
|
|
bitfld.long 0x00 11. " LOCK_DMATOCLA2 ,Lock bit of DMA to CLA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x00 10. " LOCK_CLA2TODMA ,Lock bit of CLA to DMA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x00 9. " LOCK_CPUTOCM_MSGRAM1 ,Lock bit of CPU to CM MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x00 8. " LOCK_CPUTOCM_MSGRAM0 ,Lock bit of CPU to CM MSG RAM0 control fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " LOCK_CPUTOCPU_MSGRAM1 ,Lock bit of CPU to CPU MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x00 6. " LOCK_DMATOCLA1 ,DMATOCLA1 RAM control fields lock bit" "0,1"
|
|
bitfld.long 0x00 5. " LOCK_CLA1TODMA ,CLA1TODMA RAM control fields lock bit" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_CLA1TOCPU ,CLA1TOCPU RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " LOCK_CPUTOCLA1 ,CPUTOCLA1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_CPUTOCPU_MSGRAM0 ,CPUTOCPU RAM Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0x62)++0x03
|
|
line.long 0x00 "MSGxCOMMIT,Message RAM Config Lock Commit Register"
|
|
bitfld.long 0x00 11. " COMMIT_DMATOCLA_MSGRAM1 ,Commint bit of DMA to CLA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x00 10. " COMMIT_CLATODMA_MSGRAM0 ,Commint bit of CLA to DMA MSG RAM control fields" "0,1"
|
|
bitfld.long 0x00 9. " COMMIT_CPUTOCM_MSGRAM1 ,Commint bit of CPU to CM MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x00 8. " COMMIT_CPUTOCM_MSGRAM0 ,Commint bit of CPU to CM MSG RAM0 control fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " COMMIT_CPUTOCPU_MSGRAM1 ,Commint bit of CPU to CPU MSG RAM1 control fields" "0,1"
|
|
bitfld.long 0x00 6. " COMMIT_DMATOCLA1 ,DMATOCLA1 RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x00 5. " COMMIT_CLA1TODMA ,CLA1TODMA RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x00 2. " COMMIT_CLA1TOCPU ,CLA1TOCPU RAM control fields COMMIT bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " COMMIT_CPUTOCLA1 ,CPUTOCLA1 RAM control fields COMMIT bit" "0,1"
|
|
bitfld.long 0x00 0. " COMMIT_CPUTOCPU_MSGRAM0 ,CPUTOCPU RAM control fields COMMIT bit" "0,1"
|
|
group.long (d:0x0005F400+0x68)++0x03
|
|
line.long 0x00 "MSGxACCPROT0,Message RAM Access Protection Register 0"
|
|
bitfld.long 0x00 2. " DMAWRPROT_CPUTOCPU_MSGRAM0 ,DMA WR Protection For CPUTOCPU_MSGRAM0 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_CPUTOCPU_MSGRAM0 ,CPU WR Protection For CPUTOCPU_MSGRAM0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x6A)++0x03
|
|
line.long 0x00 "MSGxACCPROT1,Message RAM Access Protection Register 1"
|
|
bitfld.long 0x00 26. " DMAWRPROT_CPUTOCPU_MSGRAM1 ,DMA WR Protection For CPUTOCPU_MSGRAM1RAM" "0,1"
|
|
bitfld.long 0x00 25. " CPUWRPROT_CPUTOCPU_MSGRAM1 ,CPU WR Protection For CPUTOCPU_MSGRAM1 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x6C)++0x03
|
|
line.long 0x00 "MSGxACCPROT2,Message RAM Access Protection Register 2"
|
|
bitfld.long 0x00 10. " DMAWRPROT_CPUTOCM_MSGRAM1 ,DMA WR Protection For CPUTOCM_MSGRAM1RAM" "0,1"
|
|
bitfld.long 0x00 9. " CPUWRPROT_CPUTOCM_MSGRAM1 ,CPU WR Protection For CPUTOCM_MSGRAM1 RAM" "0,1"
|
|
bitfld.long 0x00 2. " DMAWRPROT_CPUTOCM_MSGRAM0 ,DMA WR Protection For CPUTOCM_MSGRAM0 RAM" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_CPUTOCM_MSGRAM0 ,CPU WR Protection For CPUTOCM_MSGRAM0 RAM" "0,1"
|
|
group.long (d:0x0005F400+0x70)++0x03
|
|
line.long 0x00 "MSGxTEST,Message RAM TEST Register"
|
|
bitfld.long 0x00 18.--19. " TEST_CPUTOCM_MSGRAM1 ,CPU to CM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TEST_CPUTOCM_MSGRAM0 ,CPU to CM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " TEST_CPUTOCPU_MSGRAM1 ,CPU to CPU Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TEST_DMATOCLA1 ,DMA to CLA1 MSG RAM Mode Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " TEST_CLA1TODMA ,CLA1 to DMA MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_CLA1TOCPU ,CLA1 to CPU MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_CPUTOCLA1 ,CPU to CLA1 MSG RAM Mode Select" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_CPUTOCPU_MSGRAM0 ,CPU to CPU Mode Select" "0,1,2,3"
|
|
group.long (d:0x0005F400+0x72)++0x03
|
|
line.long 0x00 "MSGxINIT,Message RAM Init Register"
|
|
bitfld.long 0x00 9. " INIT_CPUTOCM_MSGRAM1 ,Initialization control for CPU to CM MSG RAM1" "0,1"
|
|
bitfld.long 0x00 8. " INIT_CPUTOCM_MSGRAM0 ,Initialization control for CPU to CM MSG RAM0" "0,1"
|
|
bitfld.long 0x00 7. " INIT_CPUTOCPU_MSGRAM1 ,Initialization control for CPU to CPU MSG RAM1" "0,1"
|
|
bitfld.long 0x00 6. " INIT_DMATOCLA1 ,Initialization control for DMA to CLA1 MSG RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " INIT_CLA1TODMA ,Initialization control for CLA1 to DMA MSG RAM" "0,1"
|
|
bitfld.long 0x00 2. " INIT_CLA1TOCPU ,Initialization control for CLA1TOCPU MSG RAM" "0,1"
|
|
bitfld.long 0x00 1. " INIT_CPUTOCLA1 ,Initialization control for CPUTOCLA1 MSG RAM" "0,1"
|
|
bitfld.long 0x00 0. " INIT_CPUTOCPU_MSGRAM0 ,Initialization control for CPU to CPU MSG RAM0" "0,1"
|
|
rgroup.long (d:0x0005F400+0x74)++0x03
|
|
line.long 0x00 "MSGxINITDONE,Message RAM InitDone Status Register"
|
|
bitfld.long 0x00 9. " INITDONE_CPUTOCM_MSGRAM1 ,Initialization status for CPU to CM MSG RAM1" "0,1"
|
|
bitfld.long 0x00 8. " INITDONE_CPUTOCM_MSGRAM0 ,Initialization status for CPU to CM MSG RAM0" "0,1"
|
|
bitfld.long 0x00 7. " INITDONE_CPUTOCPU_MSGRAM1 ,Initialization status for CPU to CPU MSG RAM1" "0,1"
|
|
bitfld.long 0x00 6. " INITDONE_DMATOCLA1 ,Initialization status for DMA to CLA1 MSG RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " INITDONE_CLA1TODMA ,Initialization status for CLA1 to DMA MSG RAM" "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_CLA1TOCPU ,Initialization status for CLA1 to CPU MSG RAM" "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_CPUTOCLA1 ,Initialization status for CPU to CLA1 MSG RAM" "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_CPUTOCPU_MSGRAM0 ,Initialization status for CPU to CPU MSG RAM" "0,1"
|
|
group.long (d:0x0005F400+0x76)++0x03
|
|
line.long 0x00 "MSGxRAMTEST_LOCK,Lock register to MSGx RAM TEST registers"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 11. " DMATOCLA2 ,MSGxTEST.TEST_DMATOCLA2 LOCK" "0,1"
|
|
bitfld.long 0x00 10. " CLA2TODMA ,MSGxTEST.TEST_CLA2TODMA LOCK" "0,1"
|
|
bitfld.long 0x00 9. " CPUTOCM_MSGRAM1 ,MSGxTEST.TEST_CPUTOCM_MSGRAM1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " CPUTOCM_MSGRAM0 ,MSGxTEST.TEST_CPUTOCM_MSGRAM0 LOCK" "0,1"
|
|
bitfld.long 0x00 7. " CPUTOCPU_MSGRAM1 ,MSGxTEST.TEST_CPUTOCPU_MSGRAM1 LOCK" "0,1"
|
|
bitfld.long 0x00 6. " DMATOCLA1 ,MSGxTEST.TEST_DMATOCLA1 LOCK" "0,1"
|
|
bitfld.long 0x00 5. " CLA1TODMA ,MSGxTEST.TEST_CLA1TODMA LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CLA2TOCPU ,MSGxTEST.TEST_CLA2TOCPU LOCK" "0,1"
|
|
bitfld.long 0x00 3. " CPUTOCLA2 ,MSGxTEST.TEST_CPUTOCLA2 LOCK" "0,1"
|
|
bitfld.long 0x00 2. " CLA1TOCPU ,MSGxTEST.TEST_CLA1TOCPU LOCK" "0,1"
|
|
bitfld.long 0x00 1. " CPUTOCLA1 ,MSGxTEST.TEST_CPUTOCLA1 LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " CPUTOCPU_MSGRAM0 ,MSGxTEST.TEST_CPUTOCPU_MSGRAM0 LOCK" "0,1"
|
|
group.long (d:0x0005F400+0xA0)++0x03
|
|
line.long 0x00 "ROM_LOCK,ROM Config Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 2. " LOCK_CLADATAROM ,CLADATAROM Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_SECUREROM ,SECUREROM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_BOOTROM ,BOOTROM Lock bits" "0,1"
|
|
group.long (d:0x0005F400+0xA2)++0x03
|
|
line.long 0x00 "ROM_TEST,ROM TEST Register"
|
|
bitfld.long 0x00 4.--5. " TEST_CLADATAROM ,Selects the different modes for CLADATAROM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_SECUREROM ,Selects the different modes for SECUREROM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_BOOTROM ,Selects the different modes for BOOTROM" "0,1,2,3"
|
|
group.long (d:0x0005F400+0xA4)++0x03
|
|
line.long 0x00 "ROM_FORCE_ERROR,ROM Force Error register"
|
|
bitfld.long 0x00 2. " FORCE_CLADATAROM_ERROR ,Force CLADATAROM Parity Error" "0,1"
|
|
bitfld.long 0x00 1. " FORCE_SECUREROM_ERROR ,Force SECUREROM Parity Error" "0,1"
|
|
bitfld.long 0x00 0. " FORCE_BOOTROM_ERROR ,Force Bootrom Parity Error" "0,1"
|
|
group.long (d:0x0005F400+0xAA)++0x03
|
|
line.long 0x00 "PERI_MEM_TEST_LOCK,Peripheral Memory Test Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 0. " LOCK_PERI_MEM_TEST_CONTROL ,PERI_MEM_TEST_CONTROL Lock bit" "0,1"
|
|
group.long (d:0x0005F400+0xAC)++0x03
|
|
line.long 0x00 "PERI_MEM_TEST_CONTROL,Peripheral Memory Test control Register"
|
|
bitfld.long 0x00 5. " EtherCAT_MEM_FORCE_ERROR ,Force Parity Error on EtherCAT RAM" "0,1"
|
|
bitfld.long 0x00 4. " EtherCAT_TEST_ENABLE ,EtherCAT Test mode enable" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MemoryErrorRegs"
|
|
width 15.
|
|
rgroup.long (d:0x0005F540+0x00)++0x03
|
|
line.long 0x00 "UCERRFLG,Uncorrectable Error Flag Register"
|
|
bitfld.long 0x00 4. " ECATRAMRDERR ,ECAT RAM Read Error Flag" "0,1"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Uncorrectable Read Error Flag" "0,1"
|
|
group.long (d:0x0005F540+0x02)++0x03
|
|
line.long 0x00 "UCERRSET,Uncorrectable Error Flag Set Register"
|
|
bitfld.long 0x00 4. " ECATRAMRDERR ,ECAT RAM Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Uncorrectable Read Error Flag Set" "0,1"
|
|
group.long (d:0x0005F540+0x04)++0x03
|
|
line.long 0x00 "UCERRCLR,Uncorrectable Error Flag Clear Register"
|
|
bitfld.long 0x00 4. " ECATRAMRDERR ,ECAT RAM Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Uncorrectable Read Error Flag Clear" "0,1"
|
|
rgroup.long (d:0x0005F540+0x06)++0x03
|
|
line.long 0x00 "UCCPUREADDR,Uncorrectable CPU Read Error Address"
|
|
rgroup.long (d:0x0005F540+0x08)++0x03
|
|
line.long 0x00 "UCDMAREADDR,Uncorrectable DMA Read Error Address"
|
|
rgroup.long (d:0x0005F540+0x0A)++0x03
|
|
line.long 0x00 "UCCLA1READDR,Uncorrectable CLA1 Read Error Address"
|
|
rgroup.long (d:0x0005F540+0x0E)++0x03
|
|
line.long 0x00 "UCECATRAMADDR,Uncorrectable etherCAT RAM Read Error Address"
|
|
rgroup.long (d:0x0005F540+0x20)++0x03
|
|
line.long 0x00 "CERRFLG,Correctable Error Flag Register"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Correctable Read Error Flag" "0,1"
|
|
group.long (d:0x0005F540+0x22)++0x03
|
|
line.long 0x00 "CERRSET,Correctable Error Flag Set Register"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Correctable Read Error Flag Set" "0,1"
|
|
group.long (d:0x0005F540+0x24)++0x03
|
|
line.long 0x00 "CERRCLR,Correctable Error Flag Clear Register"
|
|
bitfld.long 0x00 2. " CLA1RDERR ,CLA1 Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " DMARDERR ,DMA Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " CPURDERR ,CPU Correctable Read Error Flag Clear" "0,1"
|
|
rgroup.long (d:0x0005F540+0x26)++0x03
|
|
line.long 0x00 "CCPUREADDR,Correctable CPU Read Error Address"
|
|
rgroup.long (d:0x0005F540+0x2A)++0x03
|
|
line.long 0x00 "CCLA1READDR,Correctable CLA1 Read Error Address"
|
|
group.long (d:0x0005F540+0x2E)++0x03
|
|
line.long 0x00 "CERRCNT,Correctable Error Count Register"
|
|
hexmask.long 0x00 0.--15. 1. "CERRCNT,Correctable error count."
|
|
group.long (d:0x0005F540+0x30)++0x03
|
|
line.long 0x00 "CERRTHRES,Correctable Error Threshold Value Register"
|
|
hexmask.long 0x00 0.--15. 1. "CERRTHRES,Correctable error threshold."
|
|
rgroup.long (d:0x0005F540+0x32)++0x03
|
|
line.long 0x00 "CEINTFLG,Correctable Error Interrupt Flag Status Register"
|
|
bitfld.long 0x00 0. " CEINTFLAG ,Total corrected error count exceeded threshold flag." "0,1"
|
|
group.long (d:0x0005F540+0x34)++0x03
|
|
line.long 0x00 "CEINTCLR,Correctable Error Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 0. " CEINTCLR ,CPU Corrected Error Threshold Exceeded Error Clear." "0,1"
|
|
group.long (d:0x0005F540+0x36)++0x03
|
|
line.long 0x00 "CEINTSET,Correctable Error Interrupt Flag Set Register"
|
|
bitfld.long 0x00 0. " CEINTSET ,Total corrected error count exceeded flag set." "0,1"
|
|
group.long (d:0x0005F540+0x38)++0x03
|
|
line.long 0x00 "CEINTEN,Correctable Error Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " CEINTEN ,CPU/DMA/CLA Correctable Error Interrupt Enable." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NmiIntruptRegs"
|
|
width 13.
|
|
group.word (d:0x00007060+0x00)++0x01
|
|
line.word 0x00 "NMICFG,NMI Configuration Register"
|
|
bitfld.word 0x00 0. " NMIE ,Global NMI Enable" "0,1"
|
|
rgroup.word (d:0x00007060+0x01)++0x01
|
|
line.word 0x00 "NMIFLG,NMI Flag Register (SYSRsn Clear)"
|
|
bitfld.word 0x00 14. " CRC_FAIL ,CRC calculation failed." "0,1"
|
|
bitfld.word 0x00 13. " ECATNMIn ,NMI from EtherCAT reset out" "0,1"
|
|
bitfld.word 0x00 12. " CMNMIWDRSn ,CM NMI watch dog has timed out." "0,1"
|
|
bitfld.word 0x00 10. " CPU2NMIWDRSn ,CPU2 NMIWDRSn Reset Indication Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CPU2WDRSn ,CPU2 WDRSn Reset Indication Flag" "0,1"
|
|
bitfld.word 0x00 8. " CLBNMI ,Configurable Logic Block NMI Flag" "0,1"
|
|
bitfld.word 0x00 7. " ERADNMI ,ERAD Module NMI Flag" "0,1"
|
|
bitfld.word 0x00 6. " PIEVECTERR ,PIE Vector Fetch Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " CPU2HWBISTERR ,HW BIST Error NMI Flag" "0,1"
|
|
bitfld.word 0x00 4. " CPU1HWBISTERR ,HW BIST Error NMI Flag" "0,1"
|
|
bitfld.word 0x00 3. " FLUNCERR ,Flash Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.word 0x00 2. " RAMUNCERR ,RAM Uncorrectable Error NMI Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " CLOCKFAIL ,Clock Fail Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " NMIINT ,NMI Interrupt Flag" "0,1"
|
|
group.word (d:0x00007060+0x02)++0x01
|
|
line.word 0x00 "NMIFLGCLR,NMI Flag Clear Register"
|
|
bitfld.word 0x00 14. " CRC_FAIL ,CRC_FAIL flag clear" "0,1"
|
|
bitfld.word 0x00 13. " ECATNMIn ,ECATNMIn flag clear" "0,1"
|
|
bitfld.word 0x00 12. " CMNMIWDRSn ,DCDCOLF Flag Clear" "0,1"
|
|
bitfld.word 0x00 10. " CPU2NMIWDRSn ,CPU2NMIWDRSn Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CPU2WDRSn ,CPU2WDRSn Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " CLBNMI ,CLBNMI Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " ERADNMI ,ERADNMI Flag Clear" "0,1"
|
|
bitfld.word 0x00 6. " PIEVECTERR ,PIEVECTERR Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " CPU2HWBISTERR ,CPU2HWBISTERR Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " CPU1HWBISTERR ,CPU1HWBISTERR Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " FLUNCERR ,FLUNCERR Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " RAMUNCERR ,RAMUNCERR Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " CLOCKFAIL ,CLOCKFAIL Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " NMIINT ,NMIINT Flag Clear" "0,1"
|
|
group.word (d:0x00007060+0x03)++0x01
|
|
line.word 0x00 "NMIFLGFRC,NMI Flag Force Register"
|
|
bitfld.word 0x00 14. " CRC_FAIL ,CRC_FAIL flag force" "0,1"
|
|
bitfld.word 0x00 13. " ECATNMIn ,ECATNMIn flag force" "0,1"
|
|
bitfld.word 0x00 12. " CMNMIWDRSn ,DCDCOLF Flag Force" "0,1"
|
|
bitfld.word 0x00 10. " CPU2NMIWDRSn ,CPU2NMIWDRSn Flag Force" "0,1"
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|
newline
|
|
bitfld.word 0x00 9. " CPU2WDRSn ,CPU2WDRSn Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " CLBNMI ,CLBNMI Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " ERADNMI ,ERADNMI Flag Force" "0,1"
|
|
bitfld.word 0x00 6. " PIEVECTERR ,PIEVECTERR Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " CPU2HWBISTERR ,CPU2HWBISTERR Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " CPU1HWBISTERR ,CPU1HWBISTERR Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " FLUNCERR ,FLUNCERR Flag Force" "0,1"
|
|
bitfld.word 0x00 2. " RAMUNCERR ,RAMUNCERR Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " CLOCKFAIL ,CLOCKFAIL Flag Force" "0,1"
|
|
rgroup.word (d:0x00007060+0x04)++0x01
|
|
line.word 0x00 "NMIWDCNT,NMI Watchdog Counter Register"
|
|
group.word (d:0x00007060+0x05)++0x01
|
|
line.word 0x00 "NMIWDPRD,NMI Watchdog Period Register"
|
|
rgroup.word (d:0x00007060+0x06)++0x01
|
|
line.word 0x00 "NMISHDFLG,NMI Shadow Flag Register"
|
|
bitfld.word 0x00 14. " CRC_FAIL ,CRC_FAIL flag" "0,1"
|
|
bitfld.word 0x00 13. " ECATNMIn ,ECATNMIn flag" "0,1"
|
|
bitfld.word 0x00 12. " CMNMIWDRSn ,Shadow DCDCOLF Flag" "0,1"
|
|
bitfld.word 0x00 10. " CPU2NMIWDRSn ,Shadow CPU2NMIWDRSn Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CPU2WDRSn ,Shadow CPU2WDRSn Flag" "0,1"
|
|
bitfld.word 0x00 8. " CLBNMI ,Shadow CLBNMI Flag" "0,1"
|
|
bitfld.word 0x00 7. " ERADNMI ,Shadow ERADNMI Flag" "0,1"
|
|
bitfld.word 0x00 6. " PIEVECTERR ,Shadow PIEVECTERR Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " CPU2HWBISTERR ,Shadow CPU2HWBISTERR Flag" "0,1"
|
|
bitfld.word 0x00 4. " CPU1HWBISTERR ,Shadow CPU1HWBISTERR Flag" "0,1"
|
|
bitfld.word 0x00 3. " FLUNCERR ,Shadow FLUNCERR Flag" "0,1"
|
|
bitfld.word 0x00 2. " RAMUNCERR ,Shadow RAMUNCERR Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " CLOCKFAIL ,Shadow CLOCKFAIL Flag" "0,1"
|
|
rgroup.word (d:0x00007060+0x07)++0x01
|
|
line.word 0x00 "ERRORSTS,Error pin status"
|
|
bitfld.word 0x00 1. " PINSTS ,Error pin status." "0,1"
|
|
bitfld.word 0x00 0. " ERROR ,Error flag." "0,1"
|
|
group.word (d:0x00007060+0x08)++0x01
|
|
line.word 0x00 "ERRORSTSCLR,ERRORSTS clear register"
|
|
bitfld.word 0x00 0. " ERROR ,ERRORFLG.ERROR clear bit" "0,1"
|
|
group.word (d:0x00007060+0x09)++0x01
|
|
line.word 0x00 "ERRORSTSFRC,ERRORSTS force register"
|
|
bitfld.word 0x00 0. " ERROR ,ERRORSTS.ERROR pin force." "0,1"
|
|
group.word (d:0x00007060+0x0A)++0x01
|
|
line.word 0x00 "ERRORCTL,Error pin control register"
|
|
bitfld.word 0x00 0. " ERRORPOLSEL ,ERROR pin polarity select" "0,1"
|
|
group.word (d:0x00007060+0x0B)++0x01
|
|
line.word 0x00 "ERRORLOCK,Lock register to Error pin registers."
|
|
bitfld.word 0x00 0. " ERRORCTL ,ERRORCTL Lock bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PieCtrlRegs"
|
|
width 10.
|
|
group.word (d:0x00000CE0+0x00)++0x01
|
|
line.word 0x00 "PIECTRL,ePIE Control Register"
|
|
hexmask.word 0x00 1.--15. 1. "PIEVECT,PIE Vector Address"
|
|
bitfld.word 0x00 0. " ENPIE ,PIE Enable" "0,1"
|
|
group.word (d:0x00000CE0+0x01)++0x01
|
|
line.word 0x00 "PIEACK,Interrupt Acknowledge Register"
|
|
bitfld.word 0x00 11. " ACK12 ,Acknowledge PIE Interrupt Group 12" "0,1"
|
|
bitfld.word 0x00 10. " ACK11 ,Acknowledge PIE Interrupt Group 11" "0,1"
|
|
bitfld.word 0x00 9. " ACK10 ,Acknowledge PIE Interrupt Group 10" "0,1"
|
|
bitfld.word 0x00 8. " ACK9 ,Acknowledge PIE Interrupt Group 9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " ACK8 ,Acknowledge PIE Interrupt Group 8" "0,1"
|
|
bitfld.word 0x00 6. " ACK7 ,Acknowledge PIE Interrupt Group 7" "0,1"
|
|
bitfld.word 0x00 5. " ACK6 ,Acknowledge PIE Interrupt Group 6" "0,1"
|
|
bitfld.word 0x00 4. " ACK5 ,Acknowledge PIE Interrupt Group 5" "0,1"
|
|
newline
|
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bitfld.word 0x00 3. " ACK4 ,Acknowledge PIE Interrupt Group 4" "0,1"
|
|
bitfld.word 0x00 2. " ACK3 ,Acknowledge PIE Interrupt Group 3" "0,1"
|
|
bitfld.word 0x00 1. " ACK2 ,Acknowledge PIE Interrupt Group 2" "0,1"
|
|
bitfld.word 0x00 0. " ACK1 ,Acknowledge PIE Interrupt Group 1" "0,1"
|
|
group.word (d:0x00000CE0+0x02)++0x01
|
|
line.word 0x00 "PIEIER1,Interrupt Group 1 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 1.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 1.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 1.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 1.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 1.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 1.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 1.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 1.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 1.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 1.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 1.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 1.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 1.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 1.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 1.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 1.1" "0,1"
|
|
group.word (d:0x00000CE0+0x03)++0x01
|
|
line.word 0x00 "PIEIFR1,Interrupt Group 1 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 1.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 1.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 1.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 1.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 1.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 1.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 1.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 1.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 1.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 1.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 1.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 1.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 1.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 1.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 1.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 1.1" "0,1"
|
|
group.word (d:0x00000CE0+0x04)++0x01
|
|
line.word 0x00 "PIEIER2,Interrupt Group 2 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 2.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 2.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 2.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 2.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 2.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 2.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 2.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 2.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 2.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 2.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 2.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 2.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 2.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 2.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 2.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 2.1" "0,1"
|
|
group.word (d:0x00000CE0+0x05)++0x01
|
|
line.word 0x00 "PIEIFR2,Interrupt Group 2 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 2.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 2.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 2.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 2.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 2.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 2.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 2.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 2.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 2.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 2.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 2.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 2.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 2.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 2.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 2.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 2.1" "0,1"
|
|
group.word (d:0x00000CE0+0x06)++0x01
|
|
line.word 0x00 "PIEIER3,Interrupt Group 3 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 3.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 3.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 3.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 3.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 3.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 3.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 3.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 3.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 3.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 3.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 3.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 3.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 3.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 3.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 3.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 3.1" "0,1"
|
|
group.word (d:0x00000CE0+0x07)++0x01
|
|
line.word 0x00 "PIEIFR3,Interrupt Group 3 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 3.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 3.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 3.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 3.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 3.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 3.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 3.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 3.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 3.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 3.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 3.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 3.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 3.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 3.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 3.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 3.1" "0,1"
|
|
group.word (d:0x00000CE0+0x08)++0x01
|
|
line.word 0x00 "PIEIER4,Interrupt Group 4 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 4.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 4.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 4.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 4.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 4.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 4.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 4.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 4.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 4.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 4.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 4.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 4.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 4.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 4.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 4.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 4.1" "0,1"
|
|
group.word (d:0x00000CE0+0x09)++0x01
|
|
line.word 0x00 "PIEIFR4,Interrupt Group 4 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 4.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 4.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 4.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 4.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 4.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 4.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 4.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 4.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 4.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 4.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 4.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 4.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 4.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 4.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 4.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 4.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0A)++0x01
|
|
line.word 0x00 "PIEIER5,Interrupt Group 5 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 5.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 5.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 5.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 5.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 5.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 5.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 5.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 5.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 5.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 5.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 5.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 5.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 5.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 5.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 5.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 5.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0B)++0x01
|
|
line.word 0x00 "PIEIFR5,Interrupt Group 5 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 5.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 5.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 5.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 5.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 5.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 5.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 5.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 5.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 5.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 5.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 5.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 5.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 5.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 5.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 5.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 5.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0C)++0x01
|
|
line.word 0x00 "PIEIER6,Interrupt Group 6 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 6.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 6.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 6.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 6.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 6.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 6.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 6.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 6.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 6.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 6.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 6.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 6.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 6.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 6.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 6.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 6.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0D)++0x01
|
|
line.word 0x00 "PIEIFR6,Interrupt Group 6 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 6.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 6.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 6.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 6.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 6.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 6.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 6.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 6.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 6.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 6.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 6.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 6.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 6.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 6.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 6.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 6.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0E)++0x01
|
|
line.word 0x00 "PIEIER7,Interrupt Group 7 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 7.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 7.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 7.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 7.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 7.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 7.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 7.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 7.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 7.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 7.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 7.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 7.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 7.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 7.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 7.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 7.1" "0,1"
|
|
group.word (d:0x00000CE0+0x0F)++0x01
|
|
line.word 0x00 "PIEIFR7,Interrupt Group 7 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 7.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 7.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 7.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 7.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 7.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 7.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 7.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 7.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 7.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 7.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 7.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 7.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 7.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 7.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 7.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 7.1" "0,1"
|
|
group.word (d:0x00000CE0+0x10)++0x01
|
|
line.word 0x00 "PIEIER8,Interrupt Group 8 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 8.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 8.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 8.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 8.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 8.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 8.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 8.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 8.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 8.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 8.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 8.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 8.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 8.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 8.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 8.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 8.1" "0,1"
|
|
group.word (d:0x00000CE0+0x11)++0x01
|
|
line.word 0x00 "PIEIFR8,Interrupt Group 8 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 8.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 8.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 8.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 8.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 8.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 8.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 8.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 8.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 8.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 8.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 8.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 8.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 8.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 8.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 8.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 8.1" "0,1"
|
|
group.word (d:0x00000CE0+0x12)++0x01
|
|
line.word 0x00 "PIEIER9,Interrupt Group 9 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 9.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 9.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 9.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 9.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 9.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 9.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 9.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 9.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 9.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 9.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 9.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 9.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 9.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 9.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 9.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 9.1" "0,1"
|
|
group.word (d:0x00000CE0+0x13)++0x01
|
|
line.word 0x00 "PIEIFR9,Interrupt Group 9 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 9.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 9.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 9.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 9.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 9.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 9.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 9.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 9.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 9.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 9.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 9.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 9.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 9.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 9.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 9.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 9.1" "0,1"
|
|
group.word (d:0x00000CE0+0x14)++0x01
|
|
line.word 0x00 "PIEIER10,Interrupt Group 10 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 10.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 10.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 10.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 10.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 10.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 10.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 10.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 10.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 10.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 10.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 10.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 10.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 10.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 10.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 10.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 10.1" "0,1"
|
|
group.word (d:0x00000CE0+0x15)++0x01
|
|
line.word 0x00 "PIEIFR10,Interrupt Group 10 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 10.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 10.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 10.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 10.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 10.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 10.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 10.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 10.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 10.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 10.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 10.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 10.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 10.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 10.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 10.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 10.1" "0,1"
|
|
group.word (d:0x00000CE0+0x16)++0x01
|
|
line.word 0x00 "PIEIER11,Interrupt Group 11 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 11.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 11.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 11.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 11.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 11.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 11.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 11.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 11.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 11.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 11.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 11.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 11.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 11.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 11.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 11.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 11.1" "0,1"
|
|
group.word (d:0x00000CE0+0x17)++0x01
|
|
line.word 0x00 "PIEIFR11,Interrupt Group 11 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 11.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 11.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 11.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 11.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 11.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 11.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 11.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 11.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 11.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 11.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 11.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 11.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 11.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 11.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 11.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 11.1" "0,1"
|
|
group.word (d:0x00000CE0+0x18)++0x01
|
|
line.word 0x00 "PIEIER12,Interrupt Group 12 Enable Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Enable for Interrupt 12.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Enable for Interrupt 12.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Enable for Interrupt 12.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Enable for Interrupt 12.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Enable for Interrupt 12.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Enable for Interrupt 12.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Enable for Interrupt 12.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Enable for Interrupt 12.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Enable for Interrupt 12.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Enable for Interrupt 12.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Enable for Interrupt 12.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Enable for Interrupt 12.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Enable for Interrupt 12.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Enable for Interrupt 12.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Enable for Interrupt 12.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Enable for Interrupt 12.1" "0,1"
|
|
group.word (d:0x00000CE0+0x19)++0x01
|
|
line.word 0x00 "PIEIFR12,Interrupt Group 12 Flag Register"
|
|
bitfld.word 0x00 15. " INTx16 ,Flag for Interrupt 12.16" "0,1"
|
|
bitfld.word 0x00 14. " INTx15 ,Flag for Interrupt 12.15" "0,1"
|
|
bitfld.word 0x00 13. " INTx14 ,Flag for Interrupt 12.14" "0,1"
|
|
bitfld.word 0x00 12. " INTx13 ,Flag for Interrupt 12.13" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " INTx12 ,Flag for Interrupt 12.12" "0,1"
|
|
bitfld.word 0x00 10. " INTx11 ,Flag for Interrupt 12.11" "0,1"
|
|
bitfld.word 0x00 9. " INTx10 ,Flag for Interrupt 12.10" "0,1"
|
|
bitfld.word 0x00 8. " INTx9 ,Flag for Interrupt 12.9" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " INTx8 ,Flag for Interrupt 12.8" "0,1"
|
|
bitfld.word 0x00 6. " INTx7 ,Flag for Interrupt 12.7" "0,1"
|
|
bitfld.word 0x00 5. " INTx6 ,Flag for Interrupt 12.6" "0,1"
|
|
bitfld.word 0x00 4. " INTx5 ,Flag for Interrupt 12.5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INTx4 ,Flag for Interrupt 12.4" "0,1"
|
|
bitfld.word 0x00 2. " INTx3 ,Flag for Interrupt 12.3" "0,1"
|
|
bitfld.word 0x00 1. " INTx2 ,Flag for Interrupt 12.2" "0,1"
|
|
bitfld.word 0x00 0. " INTx1 ,Flag for Interrupt 12.1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RomPrefetchRegs"
|
|
width 13.
|
|
group.long (d:0x0005F588+0x00)++0x03
|
|
line.long 0x00 "ROMPREFETCH,ROM Prefetch Configuration Register"
|
|
bitfld.long 0x00 0. " PFENABLE ,ROM Prefetch Enable/Disable Control" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RomWaitStateRegs"
|
|
width 14.
|
|
group.long (d:0x0005F580+0x00)++0x03
|
|
line.long 0x00 "ROMWAITSTATE,ROM Wait State Configuration Register"
|
|
bitfld.long 0x00 0. " WSDISABLE ,ROM Wait State Enable/Disable Control" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SyncSocRegs"
|
|
width 17.
|
|
group.long (d:0x00007940+0x00)++0x03
|
|
line.long 0x00 "SYNCSELECT,Sync Input and Output Select Register"
|
|
bitfld.long 0x00 24.--28. " SYNCOUT ,Select Syncout Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00007940+0x02)++0x03
|
|
line.long 0x00 "ADCSOCOUTSELECT,External ADC (Off Chip) SOC Select Register"
|
|
bitfld.long 0x00 31. " PWM16SOCBEN ,PWM16SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 30. " PWM15SOCBEN ,PWM15SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 29. " PWM14SOCBEN ,PWM14SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 28. " PWM13SOCBEN ,PWM13SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " PWM12SOCBEN ,PWM12SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 26. " PWM11SOCBEN ,PWM11SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 25. " PWM10SOCBEN ,PWM10SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 24. " PWM9SOCBEN ,PWM9SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " PWM8SOCBEN ,PWM8SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 22. " PWM7SOCBEN ,PWM7SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 21. " PWM6SOCBEN ,PWM6SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 20. " PWM5SOCBEN ,PWM5SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " PWM4SOCBEN ,PWM4SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 18. " PWM3SOCBEN ,PWM3SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 17. " PWM2SOCBEN ,PWM2SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
bitfld.long 0x00 16. " PWM1SOCBEN ,PWM1SOCBEN Enable for ADCSOCBOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " PWM16SOCAEN ,PWM16SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 14. " PWM15SOCAEN ,PWM15SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 13. " PWM14SOCAEN ,PWM14SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 12. " PWM13SOCAEN ,PWM13SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " PWM12SOCAEN ,PWM12SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 10. " PWM11SOCAEN ,PWM11SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 9. " PWM10SOCAEN ,PWM10SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 8. " PWM9SOCAEN ,PWM9SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " PWM8SOCAEN ,PWM8SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 6. " PWM7SOCAEN ,PWM7SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 5. " PWM6SOCAEN ,PWM6SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 4. " PWM5SOCAEN ,PWM5SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " PWM4SOCAEN ,PWM4SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 2. " PWM3SOCAEN ,PWM3SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 1. " PWM2SOCAEN ,PWM2SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
bitfld.long 0x00 0. " PWM1SOCAEN ,PWM1SOCAEN Enable for ADCSOCAOn" "0,1"
|
|
group.long (d:0x00007940+0x04)++0x03
|
|
line.long 0x00 "SYNCSOCLOCK,SYNCSEL and EXTADCSOC Select Lock register"
|
|
bitfld.long 0x00 1. " ADCSOCOUTSELECT ,ADCSOCOUTSELECT Register Lock bit" "0,1"
|
|
bitfld.long 0x00 0. " SYNCSELECT ,SYNCSEL Register Lock bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SysStatusRegs"
|
|
width 19.
|
|
rgroup.long (d:0x0005D400+0x00)++0x03
|
|
line.long 0x00 "CM_STATUS_INT_FLG,Status of interrupts due to multiple sources of Cortex-M4 reset."
|
|
bitfld.long 0x00 3. " CMVECTRESET ,CMVECTRESET caused a reset of CM" "0,1"
|
|
bitfld.long 0x00 2. " CMSYSRESETREQ ,CMSYSRESETREQ caused a reset of CM" "0,1"
|
|
bitfld.long 0x00 1. " CMNMIWDRST ,CMNMIWDRST caused a reset of CM" "0,1"
|
|
bitfld.long 0x00 0. " GINT ,Global Interrupt flag" "0,1"
|
|
group.long (d:0x0005D400+0x02)++0x03
|
|
line.long 0x00 "CM_STATUS_INT_CLR,CM_STATUS_INT_FLG clear register"
|
|
bitfld.long 0x00 3. " CMVECTRESET ,CMVECTRESET interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 2. " CMSYSRESETREQ ,CMSYSRESETREQ interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 1. " CMNMIWDRST ,CMNMIWDRST interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 0. " GINT ,Global Interrupt flag Clear bit" "0,1"
|
|
group.long (d:0x0005D400+0x04)++0x03
|
|
line.long 0x00 "CM_STATUS_INT_SET,CM_STATUS_INT_FLG set register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 3. " CMVECTRESET ,CMVECTRESET interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 2. " CMSYSRESETREQ ,CMSYSRESETREQ interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 1. " CMNMIWDRST ,CMNMIWDRST interrupt flag set bit" "0,1"
|
|
group.long (d:0x0005D400+0x06)++0x03
|
|
line.long 0x00 "CM_STATUS_MASK,CM_STATUS_MASK register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 3. " CMVECTRESET ,CMVECTRESET interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 2. " CMSYSRESETREQ ,CMSYSRESETREQ interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 1. " CMNMIWDRST ,CMNMIWDRST flag mask bit" "0,1"
|
|
rgroup.long (d:0x0005D400+0x10)++0x03
|
|
line.long 0x00 "SYS_ERR_INT_FLG,Status of interrupts due to multiple different errors in the system."
|
|
bitfld.long 0x00 9. " DCC2 ,DCC2 Interrupt flag." "0,1"
|
|
bitfld.long 0x00 8. " DCC1 ,DCC1 Interrupt flag." "0,1"
|
|
bitfld.long 0x00 7. " DCC0 ,DCC0 Interrupt flag." "0,1"
|
|
bitfld.long 0x00 6. " AUX_PLL_SLIP ,Auxillary PLL Slip event flag." "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " SYS_PLL_SLIP ,System PLL Slip event flag." "0,1"
|
|
bitfld.long 0x00 4. " RAM_ACC_VIOL ,A RAM access vioation flag." "0,1"
|
|
bitfld.long 0x00 3. " FLASH_CORRECTABLE_ERR ,FLASH correctable error flag" "0,1"
|
|
bitfld.long 0x00 2. " RAM_CORRECTABLE_ERR ,RAM correctable error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EMIF_ERR ,EMIF error event flag" "0,1"
|
|
bitfld.long 0x00 0. " GINT ,Global Interrupt flag" "0,1"
|
|
group.long (d:0x0005D400+0x12)++0x03
|
|
line.long 0x00 "SYS_ERR_INT_CLR,SYS_ERR_INT_FLG clear register"
|
|
bitfld.long 0x00 9. " DCC2 ,DCC2 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 8. " DCC1 ,DCC1 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 7. " DCC0 ,DCC0 interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 6. " AUX_PLL_SLIP ,AUX_PLL_SLIP interrupt flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " SYS_PLL_SLIP ,SYS_PLL_SLIP interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 4. " RAM_ACC_VIOL ,RAM_ACC_VIOL interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 3. " FLASH_CORRECTABLE_ERR ,FLASH_CORRECTABLE_ERR interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 2. " RAM_CORRECTABLE_ERR ,RAM_CORRECTABLE_ERR interrupt flag clear bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EMIF_ERR ,EMIF_ERR interrupt flag clear bit" "0,1"
|
|
bitfld.long 0x00 0. " GINT ,Global Interrupt flag Clear bit" "0,1"
|
|
group.long (d:0x0005D400+0x14)++0x03
|
|
line.long 0x00 "SYS_ERR_INT_SET,SYS_ERR_INT_FLG set register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 9. " DCC2 ,DCC2 interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 8. " DCC1 ,DCC1 interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 7. " DCC0 ,DCC0 interrupt flag set bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " AUX_PLL_SLIP ,AUX_PLL_SLIP interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 5. " SYS_PLL_SLIP ,SYS_PLL_SLIP interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 4. " RAM_ACC_VIOL ,RAM_ACC_VIOL interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 3. " FLASH_CORRECTABLE_ERR ,FLASH_CORRECTABLE_ERR interrupt flag set bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " RAM_CORRECTABLE_ERR ,RAM_CORRECTABLE_ERR interrupt flag set bit" "0,1"
|
|
bitfld.long 0x00 1. " EMIF_ERR ,Reserved" "0,1"
|
|
group.long (d:0x0005D400+0x16)++0x03
|
|
line.long 0x00 "SYS_ERR_MASK,SYS_ERR_MASK register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
bitfld.long 0x00 9. " DCC2 ,DCC2 flag mask bit" "0,1"
|
|
bitfld.long 0x00 8. " DCC1 ,DCC1 flag mask bit" "0,1"
|
|
bitfld.long 0x00 7. " DCC0 ,DCC0 flag mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " AUX_PLL_SLIP ,AUX_PLL_SLIP flag mask bit" "0,1"
|
|
bitfld.long 0x00 5. " SYS_PLL_SLIP ,SYS_PLL_SLIP flag mask bit" "0,1"
|
|
bitfld.long 0x00 4. " RAM_ACC_VIOL ,RAM_ACC_VIOL flag mask bit" "0,1"
|
|
bitfld.long 0x00 3. " FLASH_CORRECTABLE_ERR ,FLASH_CORRECTABLE_ERR flag mask bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " RAM_CORRECTABLE_ERR ,RAM_CORRECTABLE_ERR flag mask bit" "0,1"
|
|
bitfld.long 0x00 1. " EMIF_ERR ,Reserved" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TestErrorRegs"
|
|
width 28.
|
|
rgroup.long (d:0x0005F590+0x00)++0x03
|
|
line.long 0x00 "CPU_RAM_TEST_ERROR_STS,Ram Test: Error Status Register"
|
|
bitfld.long 0x00 1. " UNC_ERROR ,UNC_ERROR flag" "0,1"
|
|
bitfld.long 0x00 0. " COR_ERROR ,COR_ERROR flag" "0,1"
|
|
group.long (d:0x0005F590+0x02)++0x03
|
|
line.long 0x00 "CPU_RAM_TEST_ERROR_STS_CLR,Ram Test: Error Status Clear Register"
|
|
bitfld.long 0x00 1. " UNC_ERROR ,UNC_ERROR flag clear bit" "0,1"
|
|
bitfld.long 0x00 0. " COR_ERROR ,COR_ERROR flag clear bit" "0,1"
|
|
rgroup.long (d:0x0005F590+0x04)++0x03
|
|
line.long 0x00 "CPU_RAM_TEST_ERROR_ADDR,Ram Test: Error address register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WdRegs"
|
|
width 8.
|
|
group.word (d:0x00007000+0x22)++0x01
|
|
line.word 0x00 "SCSR,System Control and Status Register"
|
|
rbitfld.word 0x00 2. " WDINTS ,WD Interrupt Status" "0,1"
|
|
bitfld.word 0x00 1. " WDENINT ,WD Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0. " WDOVERRIDE ,WD Override for WDDIS bit" "0,1"
|
|
rgroup.word (d:0x00007000+0x23)++0x01
|
|
line.word 0x00 "WDCNTR,Watchdog Counter Register"
|
|
hexmask.word 0x00 0.--7. 1. "WDCNTR,WD Counter"
|
|
group.word (d:0x00007000+0x25)++0x01
|
|
line.word 0x00 "WDKEY,Watchdog Reset Key Register"
|
|
hexmask.word 0x00 0.--7. 1. "WDKEY,WD KEY"
|
|
group.word (d:0x00007000+0x29)++0x01
|
|
line.word 0x00 "WDCR,Watchdog Control Register"
|
|
bitfld.word 0x00 8.--11. " WDPRECLKDIV ,WD Pre Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " WDFLG ,WD Reset Status Flag" "0,1"
|
|
bitfld.word 0x00 6. " WDDIS ,WD Disable" "0,1"
|
|
bitfld.word 0x00 3.--5. " WDCHK ,WD Check Bits" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " WDPS ,WD Clock Prescalar" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007000+0x2A)++0x01
|
|
line.word 0x00 "WDWCR,Watchdog Windowed Control Register"
|
|
rbitfld.word 0x00 8. " FIRSTKEY ,First Key Detect Flag" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "MIN,WD Min Threshold setting for Windowed Watchdog functionality"
|
|
width 0x0B
|
|
tree.end
|
|
tree "XintRegs"
|
|
width 10.
|
|
group.word (d:0x00007070+0x00)++0x01
|
|
line.word 0x00 "XINT1CR,XINT1 configuration register"
|
|
bitfld.word 0x00 2.--3. " POLARITY ,XINT1 Polarity" "0,1,2,3"
|
|
bitfld.word 0x00 0. " ENABLE ,XINT1 Enable" "0,1"
|
|
group.word (d:0x00007070+0x01)++0x01
|
|
line.word 0x00 "XINT2CR,XINT2 configuration register"
|
|
bitfld.word 0x00 2.--3. " POLARITY ,XINT2 Polarity" "0,1,2,3"
|
|
bitfld.word 0x00 0. " ENABLE ,XINT2 Enable" "0,1"
|
|
group.word (d:0x00007070+0x02)++0x01
|
|
line.word 0x00 "XINT3CR,XINT3 configuration register"
|
|
bitfld.word 0x00 2.--3. " POLARITY ,XINT3 Polarity" "0,1,2,3"
|
|
bitfld.word 0x00 0. " ENABLE ,XINT3 Enable" "0,1"
|
|
group.word (d:0x00007070+0x03)++0x01
|
|
line.word 0x00 "XINT4CR,XINT4 configuration register"
|
|
bitfld.word 0x00 2.--3. " POLARITY ,XINT4 Polarity" "0,1,2,3"
|
|
bitfld.word 0x00 0. " ENABLE ,XINT4 Enable" "0,1"
|
|
group.word (d:0x00007070+0x04)++0x01
|
|
line.word 0x00 "XINT5CR,XINT5 configuration register"
|
|
bitfld.word 0x00 2.--3. " POLARITY ,XINT5 Polarity" "0,1,2,3"
|
|
bitfld.word 0x00 0. " ENABLE ,XINT5 Enable" "0,1"
|
|
rgroup.word (d:0x00007070+0x08)++0x01
|
|
line.word 0x00 "XINT1CTR,XINT1 counter register"
|
|
rgroup.word (d:0x00007070+0x09)++0x01
|
|
line.word 0x00 "XINT2CTR,XINT2 counter register"
|
|
rgroup.word (d:0x00007070+0x0A)++0x01
|
|
line.word 0x00 "XINT3CTR,XINT3 counter register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Analog to Digital Converter (ADC)"
|
|
tree "ADC1 Result"
|
|
width 15.
|
|
rgroup.word (d:0x00000B00+0x0)++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result 0 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x01)++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result 1 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x02)++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result 2 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x03)++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result 3 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x04)++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result 4 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x05)++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result 5 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x06)++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result 6 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x07)++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result 7 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x08)++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result 8 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x09)++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result 9 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0A)++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result 10 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0B)++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result 11 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0C)++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result 12 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0D)++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result 13 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0E)++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result 14 Register"
|
|
rgroup.word (d:0x00000B00+0x0+0x0F)++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result 15 Register"
|
|
rgroup.long (d:0x00000B00+0x0+0x10)++0x03
|
|
line.long 0x00 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x0+0x12)++0x03
|
|
line.long 0x00 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x0+0x14)++0x03
|
|
line.long 0x00 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x0+0x16)++0x03
|
|
line.long 0x00 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC2 Result"
|
|
width 15.
|
|
rgroup.word (d:0x00000B00+0x20)++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result 0 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x01)++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result 1 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x02)++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result 2 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x03)++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result 3 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x04)++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result 4 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x05)++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result 5 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x06)++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result 6 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x07)++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result 7 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x08)++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result 8 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x09)++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result 9 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0A)++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result 10 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0B)++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result 11 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0C)++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result 12 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0D)++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result 13 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0E)++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result 14 Register"
|
|
rgroup.word (d:0x00000B00+0x20+0x0F)++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result 15 Register"
|
|
rgroup.long (d:0x00000B00+0x20+0x10)++0x03
|
|
line.long 0x00 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x20+0x12)++0x03
|
|
line.long 0x00 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x20+0x14)++0x03
|
|
line.long 0x00 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x20+0x16)++0x03
|
|
line.long 0x00 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC3 Result"
|
|
width 15.
|
|
rgroup.word (d:0x00000B00+0x40)++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result 0 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x01)++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result 1 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x02)++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result 2 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x03)++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result 3 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x04)++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result 4 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x05)++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result 5 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x06)++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result 6 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x07)++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result 7 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x08)++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result 8 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x09)++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result 9 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0A)++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result 10 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0B)++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result 11 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0C)++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result 12 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0D)++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result 13 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0E)++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result 14 Register"
|
|
rgroup.word (d:0x00000B00+0x40+0x0F)++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result 15 Register"
|
|
rgroup.long (d:0x00000B00+0x40+0x10)++0x03
|
|
line.long 0x00 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x40+0x12)++0x03
|
|
line.long 0x00 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x40+0x14)++0x03
|
|
line.long 0x00 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x40+0x16)++0x03
|
|
line.long 0x00 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC4 Result"
|
|
width 15.
|
|
rgroup.word (d:0x00000B00+0x60)++0x01
|
|
line.word 0x00 "ADCRESULT0,ADC Result 0 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x01)++0x01
|
|
line.word 0x00 "ADCRESULT1,ADC Result 1 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x02)++0x01
|
|
line.word 0x00 "ADCRESULT2,ADC Result 2 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x03)++0x01
|
|
line.word 0x00 "ADCRESULT3,ADC Result 3 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x04)++0x01
|
|
line.word 0x00 "ADCRESULT4,ADC Result 4 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x05)++0x01
|
|
line.word 0x00 "ADCRESULT5,ADC Result 5 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x06)++0x01
|
|
line.word 0x00 "ADCRESULT6,ADC Result 6 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x07)++0x01
|
|
line.word 0x00 "ADCRESULT7,ADC Result 7 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x08)++0x01
|
|
line.word 0x00 "ADCRESULT8,ADC Result 8 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x09)++0x01
|
|
line.word 0x00 "ADCRESULT9,ADC Result 9 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0A)++0x01
|
|
line.word 0x00 "ADCRESULT10,ADC Result 10 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0B)++0x01
|
|
line.word 0x00 "ADCRESULT11,ADC Result 11 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0C)++0x01
|
|
line.word 0x00 "ADCRESULT12,ADC Result 12 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0D)++0x01
|
|
line.word 0x00 "ADCRESULT13,ADC Result 13 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0E)++0x01
|
|
line.word 0x00 "ADCRESULT14,ADC Result 14 Register"
|
|
rgroup.word (d:0x00000B00+0x60+0x0F)++0x01
|
|
line.word 0x00 "ADCRESULT15,ADC Result 15 Register"
|
|
rgroup.long (d:0x00000B00+0x60+0x10)++0x03
|
|
line.long 0x00 "ADCPPB1RESULT,ADC Post Processing Block 1 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x60+0x12)++0x03
|
|
line.long 0x00 "ADCPPB2RESULT,ADC Post Processing Block 2 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x60+0x14)++0x03
|
|
line.long 0x00 "ADCPPB3RESULT,ADC Post Processing Block 3 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
rgroup.long (d:0x00000B00+0x60+0x16)++0x03
|
|
line.long 0x00 "ADCPPB4RESULT,ADC Post Processing Block 4 Result Register"
|
|
hexmask.long 0x00 16.--31. 1. "SIGN,Sign Extended Bits"
|
|
hexmask.long 0x00 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC1"
|
|
width 15.
|
|
group.word (d:0x00007400+0x0)++0x01
|
|
line.word 0x00 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x00 13. " ADCBSY ,ADC Busy" "0,1"
|
|
rbitfld.word 0x00 8.--11. " ADCBSYCHN ,ADC Busy Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " ADCPWDNZ ,ADC Power Down" "0,1"
|
|
bitfld.word 0x00 2. " INTPULSEPOS ,ADC Interrupt Pulse Position" "0,1"
|
|
group.word (d:0x00007400+0x0+0x01)++0x01
|
|
line.word 0x00 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x00 7. " SIGNALMODE ,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x00 6. " RESOLUTION ,SOC Conversion Resolution" "0,1"
|
|
bitfld.word 0x00 0.--3. " PRESCALE ,ADC Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x0+0x02)++0x01
|
|
line.word 0x00 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x00 15. " BURSTEN ,SOC Burst Mode Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BURSTSIZE ,SOC Burst Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--5. " BURSTTRIGSEL ,SOC Burst Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word (d:0x00007400+0x0+0x03)++0x01
|
|
line.word 0x00 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag" "0,1"
|
|
group.word (d:0x00007400+0x0+0x04)++0x01
|
|
line.word 0x00 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word (d:0x00007400+0x0+0x05)++0x01
|
|
line.word 0x00 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word (d:0x00007400+0x0+0x06)++0x01
|
|
line.word 0x00 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
group.word (d:0x00007400+0x0+0x07)++0x01
|
|
line.word 0x00 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x00 14. " INT2CONT ,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT2E ,ADCINT2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT2SEL ,ADCINT2 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT1CONT ,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT1E ,ADCINT1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT1SEL ,ADCINT1 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x0+0x08)++0x01
|
|
line.word 0x00 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x00 14. " INT4CONT ,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT4E ,ADCINT4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT4SEL ,ADCINT4 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT3CONT ,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT3E ,ADCINT3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT3SEL ,ADCINT3 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x0+0x09)++0x01
|
|
line.word 0x00 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
rbitfld.word 0x00 5.--9. " RRPOINTER ,Round Robin Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SOCPRIORITY ,SOC Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007400+0x0+0x0A)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x00 14.--15. " SOC7 ,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC6 ,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC5 ,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC4 ,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC3 ,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC2 ,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC1 ,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC0 ,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
group.word (d:0x00007400+0x0+0x0B)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x00 14.--15. " SOC15 ,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC14 ,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC13 ,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC12 ,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC11 ,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC10 ,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC9 ,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC8 ,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word (d:0x00007400+0x0+0x0C)++0x01
|
|
line.word 0x00 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word (d:0x00007400+0x0+0x0D)++0x01
|
|
line.word 0x00 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word (d:0x00007400+0x0+0x0E)++0x01
|
|
line.word 0x00 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word (d:0x00007400+0x0+0x0F)++0x01
|
|
line.word 0x00 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long (d:0x00007400+0x0+0x10)++0x03
|
|
line.long 0x00 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC0 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC0 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x12)++0x03
|
|
line.long 0x00 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC1 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC1 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x14)++0x03
|
|
line.long 0x00 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC2 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC2 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x16)++0x03
|
|
line.long 0x00 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC3 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC3 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x18)++0x03
|
|
line.long 0x00 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC4 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC4 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x1A)++0x03
|
|
line.long 0x00 "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC5 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC5 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x1C)++0x03
|
|
line.long 0x00 "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC6 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC6 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x1E)++0x03
|
|
line.long 0x00 "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC7 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC7 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x20)++0x03
|
|
line.long 0x00 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC8 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC8 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x22)++0x03
|
|
line.long 0x00 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC9 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC9 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x24)++0x03
|
|
line.long 0x00 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC10 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC10 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x26)++0x03
|
|
line.long 0x00 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC11 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC11 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x28)++0x03
|
|
line.long 0x00 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC12 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC12 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x2A)++0x03
|
|
line.long 0x00 "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC13 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC13 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x2C)++0x03
|
|
line.long 0x00 "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC14 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC14 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x0+0x2E)++0x03
|
|
line.long 0x00 "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC15 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC15 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word (d:0x00007400+0x0+0x30)++0x01
|
|
line.word 0x00 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word (d:0x00007400+0x0+0x32)++0x01
|
|
line.word 0x00 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Clear" "0,1"
|
|
group.word (d:0x00007400+0x0+0x34)++0x01
|
|
line.word 0x00 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
group.word (d:0x00007400+0x0+0x36)++0x01
|
|
line.word 0x00 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00007400+0x0+0x39)++0x01
|
|
line.word 0x00 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x00 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
rgroup.word (d:0x00007400+0x0+0x3A)++0x01
|
|
line.word 0x00 "ADCREV,ADC Revision Register"
|
|
hexmask.word 0x00 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word 0x00 0.--7. 1. "TYPE,ADC Type"
|
|
group.word (d:0x00007400+0x0+0x3B)++0x01
|
|
line.word 0x00 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word (d:0x00007400+0x0+0x40)++0x01
|
|
line.word 0x00 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 1 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x0+0x41)++0x01
|
|
line.word 0x00 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x0+0x42)++0x01
|
|
line.word 0x00 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x0+0x43)++0x01
|
|
line.word 0x00 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
group.long (d:0x00007400+0x0+0x44)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
group.long (d:0x00007400+0x0+0x46)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word (d:0x00007400+0x0+0x48)++0x01
|
|
line.word 0x00 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 2 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x0+0x49)++0x01
|
|
line.word 0x00 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x0+0x4A)++0x01
|
|
line.word 0x00 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x0+0x4B)++0x01
|
|
line.word 0x00 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
group.long (d:0x00007400+0x0+0x4C)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
group.long (d:0x00007400+0x0+0x4E)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word (d:0x00007400+0x0+0x50)++0x01
|
|
line.word 0x00 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 3 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x0+0x51)++0x01
|
|
line.word 0x00 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x0+0x52)++0x01
|
|
line.word 0x00 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x0+0x53)++0x01
|
|
line.word 0x00 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
group.long (d:0x00007400+0x0+0x54)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
group.long (d:0x00007400+0x0+0x56)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word (d:0x00007400+0x0+0x58)++0x01
|
|
line.word 0x00 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 4 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x0+0x59)++0x01
|
|
line.word 0x00 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x0+0x5A)++0x01
|
|
line.word 0x00 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x0+0x5B)++0x01
|
|
line.word 0x00 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
group.long (d:0x00007400+0x0+0x5C)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
group.long (d:0x00007400+0x0+0x5E)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word (d:0x00007400+0x0+0x6F)++0x01
|
|
line.word 0x00 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
group.long (d:0x00007400+0x0+0x70)++0x03
|
|
line.long 0x00 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
group.long (d:0x00007400+0x0+0x72)++0x03
|
|
line.long 0x00 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
group.long (d:0x00007400+0x0+0x74)++0x03
|
|
line.long 0x00 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
group.long (d:0x00007400+0x0+0x76)++0x03
|
|
line.long 0x00 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
group.long (d:0x00007400+0x0+0x78)++0x03
|
|
line.long 0x00 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
group.long (d:0x00007400+0x0+0x7A)++0x03
|
|
line.long 0x00 "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC2"
|
|
width 15.
|
|
group.word (d:0x00007400+0x80)++0x01
|
|
line.word 0x00 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x00 13. " ADCBSY ,ADC Busy" "0,1"
|
|
rbitfld.word 0x00 8.--11. " ADCBSYCHN ,ADC Busy Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " ADCPWDNZ ,ADC Power Down" "0,1"
|
|
bitfld.word 0x00 2. " INTPULSEPOS ,ADC Interrupt Pulse Position" "0,1"
|
|
group.word (d:0x00007400+0x80+0x01)++0x01
|
|
line.word 0x00 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x00 7. " SIGNALMODE ,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x00 6. " RESOLUTION ,SOC Conversion Resolution" "0,1"
|
|
bitfld.word 0x00 0.--3. " PRESCALE ,ADC Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x80+0x02)++0x01
|
|
line.word 0x00 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x00 15. " BURSTEN ,SOC Burst Mode Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BURSTSIZE ,SOC Burst Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--5. " BURSTTRIGSEL ,SOC Burst Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word (d:0x00007400+0x80+0x03)++0x01
|
|
line.word 0x00 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag" "0,1"
|
|
group.word (d:0x00007400+0x80+0x04)++0x01
|
|
line.word 0x00 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word (d:0x00007400+0x80+0x05)++0x01
|
|
line.word 0x00 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word (d:0x00007400+0x80+0x06)++0x01
|
|
line.word 0x00 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
group.word (d:0x00007400+0x80+0x07)++0x01
|
|
line.word 0x00 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x00 14. " INT2CONT ,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT2E ,ADCINT2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT2SEL ,ADCINT2 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 6. " INT1CONT ,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT1E ,ADCINT1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT1SEL ,ADCINT1 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x80+0x08)++0x01
|
|
line.word 0x00 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x00 14. " INT4CONT ,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT4E ,ADCINT4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT4SEL ,ADCINT4 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 6. " INT3CONT ,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT3E ,ADCINT3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT3SEL ,ADCINT3 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00007400+0x80+0x09)++0x01
|
|
line.word 0x00 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
rbitfld.word 0x00 5.--9. " RRPOINTER ,Round Robin Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.word 0x00 0.--4. " SOCPRIORITY ,SOC Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.word (d:0x00007400+0x80+0x0A)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
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|
bitfld.word 0x00 14.--15. " SOC7 ,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC6 ,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC5 ,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC4 ,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC3 ,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC2 ,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC1 ,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC0 ,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
group.word (d:0x00007400+0x80+0x0B)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x00 14.--15. " SOC15 ,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC14 ,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC13 ,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC12 ,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC11 ,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC10 ,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC9 ,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC8 ,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word (d:0x00007400+0x80+0x0C)++0x01
|
|
line.word 0x00 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word (d:0x00007400+0x80+0x0D)++0x01
|
|
line.word 0x00 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word (d:0x00007400+0x80+0x0E)++0x01
|
|
line.word 0x00 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word (d:0x00007400+0x80+0x0F)++0x01
|
|
line.word 0x00 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long (d:0x00007400+0x80+0x10)++0x03
|
|
line.long 0x00 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC0 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC0 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x12)++0x03
|
|
line.long 0x00 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC1 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC1 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x14)++0x03
|
|
line.long 0x00 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC2 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC2 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x16)++0x03
|
|
line.long 0x00 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC3 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC3 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x18)++0x03
|
|
line.long 0x00 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC4 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC4 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x1A)++0x03
|
|
line.long 0x00 "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC5 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC5 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x1C)++0x03
|
|
line.long 0x00 "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC6 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC6 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x1E)++0x03
|
|
line.long 0x00 "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC7 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC7 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x20)++0x03
|
|
line.long 0x00 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC8 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC8 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x22)++0x03
|
|
line.long 0x00 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC9 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC9 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x24)++0x03
|
|
line.long 0x00 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC10 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC10 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x26)++0x03
|
|
line.long 0x00 "ADCSOC11CTL,ADC SOC11 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC11 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC11 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x28)++0x03
|
|
line.long 0x00 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC12 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC12 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x2A)++0x03
|
|
line.long 0x00 "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC13 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC13 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x2C)++0x03
|
|
line.long 0x00 "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC14 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC14 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x80+0x2E)++0x03
|
|
line.long 0x00 "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC15 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC15 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word (d:0x00007400+0x80+0x30)++0x01
|
|
line.word 0x00 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word (d:0x00007400+0x80+0x32)++0x01
|
|
line.word 0x00 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Clear" "0,1"
|
|
group.word (d:0x00007400+0x80+0x34)++0x01
|
|
line.word 0x00 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Event Enable" "0,1"
|
|
group.word (d:0x00007400+0x80+0x36)++0x01
|
|
line.word 0x00 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00007400+0x80+0x39)++0x01
|
|
line.word 0x00 "ADCCOUNTER,ADC Counter Register"
|
|
hexmask.word 0x00 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
|
|
rgroup.word (d:0x00007400+0x80+0x3A)++0x01
|
|
line.word 0x00 "ADCREV,ADC Revision Register"
|
|
hexmask.word 0x00 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word 0x00 0.--7. 1. "TYPE,ADC Type"
|
|
group.word (d:0x00007400+0x80+0x3B)++0x01
|
|
line.word 0x00 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFTRIM,ADC Offset Trim"
|
|
group.word (d:0x00007400+0x80+0x40)++0x01
|
|
line.word 0x00 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 1 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x80+0x41)++0x01
|
|
line.word 0x00 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x80+0x42)++0x01
|
|
line.word 0x00 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x80+0x43)++0x01
|
|
line.word 0x00 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
group.long (d:0x00007400+0x80+0x44)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
|
|
group.long (d:0x00007400+0x80+0x46)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
|
|
group.word (d:0x00007400+0x80+0x48)++0x01
|
|
line.word 0x00 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 2 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x80+0x49)++0x01
|
|
line.word 0x00 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x80+0x4A)++0x01
|
|
line.word 0x00 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x80+0x4B)++0x01
|
|
line.word 0x00 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
group.long (d:0x00007400+0x80+0x4C)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
group.long (d:0x00007400+0x80+0x4E)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word (d:0x00007400+0x80+0x50)++0x01
|
|
line.word 0x00 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 3 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x80+0x51)++0x01
|
|
line.word 0x00 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x80+0x52)++0x01
|
|
line.word 0x00 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x80+0x53)++0x01
|
|
line.word 0x00 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
group.long (d:0x00007400+0x80+0x54)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
group.long (d:0x00007400+0x80+0x56)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word (d:0x00007400+0x80+0x58)++0x01
|
|
line.word 0x00 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 4 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x80+0x59)++0x01
|
|
line.word 0x00 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x80+0x5A)++0x01
|
|
line.word 0x00 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x80+0x5B)++0x01
|
|
line.word 0x00 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
group.long (d:0x00007400+0x80+0x5C)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
group.long (d:0x00007400+0x80+0x5E)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word (d:0x00007400+0x80+0x6F)++0x01
|
|
line.word 0x00 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
group.long (d:0x00007400+0x80+0x70)++0x03
|
|
line.long 0x00 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
group.long (d:0x00007400+0x80+0x72)++0x03
|
|
line.long 0x00 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
group.long (d:0x00007400+0x80+0x74)++0x03
|
|
line.long 0x00 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
group.long (d:0x00007400+0x80+0x76)++0x03
|
|
line.long 0x00 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
group.long (d:0x00007400+0x80+0x78)++0x03
|
|
line.long 0x00 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
group.long (d:0x00007400+0x80+0x7A)++0x03
|
|
line.long 0x00 "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC3"
|
|
width 15.
|
|
group.word (d:0x00007400+0x100)++0x01
|
|
line.word 0x00 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x00 13. " ADCBSY ,ADC Busy" "0,1"
|
|
rbitfld.word 0x00 8.--11. " ADCBSYCHN ,ADC Busy Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " ADCPWDNZ ,ADC Power Down" "0,1"
|
|
bitfld.word 0x00 2. " INTPULSEPOS ,ADC Interrupt Pulse Position" "0,1"
|
|
group.word (d:0x00007400+0x100+0x01)++0x01
|
|
line.word 0x00 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x00 7. " SIGNALMODE ,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x00 6. " RESOLUTION ,SOC Conversion Resolution" "0,1"
|
|
bitfld.word 0x00 0.--3. " PRESCALE ,ADC Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x100+0x02)++0x01
|
|
line.word 0x00 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x00 15. " BURSTEN ,SOC Burst Mode Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BURSTSIZE ,SOC Burst Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--5. " BURSTTRIGSEL ,SOC Burst Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word (d:0x00007400+0x100+0x03)++0x01
|
|
line.word 0x00 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag" "0,1"
|
|
group.word (d:0x00007400+0x100+0x04)++0x01
|
|
line.word 0x00 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word (d:0x00007400+0x100+0x05)++0x01
|
|
line.word 0x00 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word (d:0x00007400+0x100+0x06)++0x01
|
|
line.word 0x00 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
group.word (d:0x00007400+0x100+0x07)++0x01
|
|
line.word 0x00 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x00 14. " INT2CONT ,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT2E ,ADCINT2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT2SEL ,ADCINT2 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT1CONT ,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT1E ,ADCINT1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT1SEL ,ADCINT1 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x100+0x08)++0x01
|
|
line.word 0x00 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x00 14. " INT4CONT ,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT4E ,ADCINT4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT4SEL ,ADCINT4 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT3CONT ,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT3E ,ADCINT3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT3SEL ,ADCINT3 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x100+0x09)++0x01
|
|
line.word 0x00 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
rbitfld.word 0x00 5.--9. " RRPOINTER ,Round Robin Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SOCPRIORITY ,SOC Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007400+0x100+0x0A)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x00 14.--15. " SOC7 ,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC6 ,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC5 ,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC4 ,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC3 ,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC2 ,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC1 ,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC0 ,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
group.word (d:0x00007400+0x100+0x0B)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x00 14.--15. " SOC15 ,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC14 ,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC13 ,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC12 ,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC11 ,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC10 ,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC9 ,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC8 ,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word (d:0x00007400+0x100+0x0C)++0x01
|
|
line.word 0x00 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word (d:0x00007400+0x100+0x0D)++0x01
|
|
line.word 0x00 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word (d:0x00007400+0x100+0x0E)++0x01
|
|
line.word 0x00 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word (d:0x00007400+0x100+0x0F)++0x01
|
|
line.word 0x00 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long (d:0x00007400+0x100+0x10)++0x03
|
|
line.long 0x00 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC0 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC0 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x12)++0x03
|
|
line.long 0x00 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC1 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC1 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x14)++0x03
|
|
line.long 0x00 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC2 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC2 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x16)++0x03
|
|
line.long 0x00 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC3 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC3 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x18)++0x03
|
|
line.long 0x00 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC4 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC4 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x1A)++0x03
|
|
line.long 0x00 "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC5 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC5 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x1C)++0x03
|
|
line.long 0x00 "ADCSOC6CTL,ADC SOC6 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC6 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC6 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x1E)++0x03
|
|
line.long 0x00 "ADCSOC7CTL,ADC SOC7 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC7 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC7 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x20)++0x03
|
|
line.long 0x00 "ADCSOC8CTL,ADC SOC8 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC8 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC8 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x22)++0x03
|
|
line.long 0x00 "ADCSOC9CTL,ADC SOC9 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC9 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC9 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x24)++0x03
|
|
line.long 0x00 "ADCSOC10CTL,ADC SOC10 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC10 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC10 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x26)++0x03
|
|
line.long 0x00 "ADCSOC11CTL,ADC SOC11 Control Register"
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|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC11 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC11 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x28)++0x03
|
|
line.long 0x00 "ADCSOC12CTL,ADC SOC12 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC12 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC12 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x2A)++0x03
|
|
line.long 0x00 "ADCSOC13CTL,ADC SOC13 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC13 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC13 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x2C)++0x03
|
|
line.long 0x00 "ADCSOC14CTL,ADC SOC14 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC14 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC14 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x100+0x2E)++0x03
|
|
line.long 0x00 "ADCSOC15CTL,ADC SOC15 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC15 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC15 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
|
|
rgroup.word (d:0x00007400+0x100+0x30)++0x01
|
|
line.word 0x00 "ADCEVTSTAT,ADC Event Status Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Flag" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Flag" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Flag" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Flag" "0,1"
|
|
group.word (d:0x00007400+0x100+0x32)++0x01
|
|
line.word 0x00 "ADCEVTCLR,ADC Event Clear Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Clear" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Clear" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Clear" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Clear" "0,1"
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|
group.word (d:0x00007400+0x100+0x34)++0x01
|
|
line.word 0x00 "ADCEVTSEL,ADC Event Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Event Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Event Enable" "0,1"
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|
group.word (d:0x00007400+0x100+0x36)++0x01
|
|
line.word 0x00 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
|
|
bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
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|
bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
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|
rgroup.word (d:0x00007400+0x100+0x39)++0x01
|
|
line.word 0x00 "ADCCOUNTER,ADC Counter Register"
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|
hexmask.word 0x00 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
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|
rgroup.word (d:0x00007400+0x100+0x3A)++0x01
|
|
line.word 0x00 "ADCREV,ADC Revision Register"
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|
hexmask.word 0x00 8.--15. 1. "REV,ADC Revision"
|
|
hexmask.word 0x00 0.--7. 1. "TYPE,ADC Type"
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|
group.word (d:0x00007400+0x100+0x3B)++0x01
|
|
line.word 0x00 "ADCOFFTRIM,ADC Offset Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFTRIM,ADC Offset Trim"
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|
group.word (d:0x00007400+0x100+0x40)++0x01
|
|
line.word 0x00 "ADCPPB1CONFIG,ADC PPB1 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 1 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.word (d:0x00007400+0x100+0x41)++0x01
|
|
line.word 0x00 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
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|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x100+0x42)++0x01
|
|
line.word 0x00 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
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|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
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|
group.word (d:0x00007400+0x100+0x43)++0x01
|
|
line.word 0x00 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
|
|
group.long (d:0x00007400+0x100+0x44)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
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|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
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|
group.long (d:0x00007400+0x100+0x46)++0x03
|
|
line.long 0x00 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
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|
group.word (d:0x00007400+0x100+0x48)++0x01
|
|
line.word 0x00 "ADCPPB2CONFIG,ADC PPB2 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
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|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 2 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.word (d:0x00007400+0x100+0x49)++0x01
|
|
line.word 0x00 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x100+0x4A)++0x01
|
|
line.word 0x00 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x100+0x4B)++0x01
|
|
line.word 0x00 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
|
|
group.long (d:0x00007400+0x100+0x4C)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
|
|
group.long (d:0x00007400+0x100+0x4E)++0x03
|
|
line.long 0x00 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
|
|
group.word (d:0x00007400+0x100+0x50)++0x01
|
|
line.word 0x00 "ADCPPB3CONFIG,ADC PPB3 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 3 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x100+0x51)++0x01
|
|
line.word 0x00 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x100+0x52)++0x01
|
|
line.word 0x00 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x100+0x53)++0x01
|
|
line.word 0x00 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
|
|
group.long (d:0x00007400+0x100+0x54)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
|
|
group.long (d:0x00007400+0x100+0x56)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word (d:0x00007400+0x100+0x58)++0x01
|
|
line.word 0x00 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 4 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x100+0x59)++0x01
|
|
line.word 0x00 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x100+0x5A)++0x01
|
|
line.word 0x00 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x100+0x5B)++0x01
|
|
line.word 0x00 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
group.long (d:0x00007400+0x100+0x5C)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
group.long (d:0x00007400+0x100+0x5E)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word (d:0x00007400+0x100+0x6F)++0x01
|
|
line.word 0x00 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
group.long (d:0x00007400+0x100+0x70)++0x03
|
|
line.long 0x00 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
group.long (d:0x00007400+0x100+0x72)++0x03
|
|
line.long 0x00 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
group.long (d:0x00007400+0x100+0x74)++0x03
|
|
line.long 0x00 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
group.long (d:0x00007400+0x100+0x76)++0x03
|
|
line.long 0x00 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
group.long (d:0x00007400+0x100+0x78)++0x03
|
|
line.long 0x00 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
group.long (d:0x00007400+0x100+0x7A)++0x03
|
|
line.long 0x00 "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC4"
|
|
width 15.
|
|
group.word (d:0x00007400+0x180)++0x01
|
|
line.word 0x00 "ADCCTL1,ADC Control 1 Register"
|
|
rbitfld.word 0x00 13. " ADCBSY ,ADC Busy" "0,1"
|
|
rbitfld.word 0x00 8.--11. " ADCBSYCHN ,ADC Busy Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " ADCPWDNZ ,ADC Power Down" "0,1"
|
|
bitfld.word 0x00 2. " INTPULSEPOS ,ADC Interrupt Pulse Position" "0,1"
|
|
group.word (d:0x00007400+0x180+0x01)++0x01
|
|
line.word 0x00 "ADCCTL2,ADC Control 2 Register"
|
|
bitfld.word 0x00 7. " SIGNALMODE ,SOC Signaling Mode" "0,1"
|
|
bitfld.word 0x00 6. " RESOLUTION ,SOC Conversion Resolution" "0,1"
|
|
bitfld.word 0x00 0.--3. " PRESCALE ,ADC Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x180+0x02)++0x01
|
|
line.word 0x00 "ADCBURSTCTL,ADC Burst Control Register"
|
|
bitfld.word 0x00 15. " BURSTEN ,SOC Burst Mode Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BURSTSIZE ,SOC Burst Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--5. " BURSTTRIGSEL ,SOC Burst Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word (d:0x00007400+0x180+0x03)++0x01
|
|
line.word 0x00 "ADCINTFLG,ADC Interrupt Flag Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag" "0,1"
|
|
group.word (d:0x00007400+0x180+0x04)++0x01
|
|
line.word 0x00 "ADCINTFLGCLR,ADC Interrupt Flag Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Flag Clear" "0,1"
|
|
rgroup.word (d:0x00007400+0x180+0x05)++0x01
|
|
line.word 0x00 "ADCINTOVF,ADC Interrupt Overflow Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Flags" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Flags" "0,1"
|
|
group.word (d:0x00007400+0x180+0x06)++0x01
|
|
line.word 0x00 "ADCINTOVFCLR,ADC Interrupt Overflow Clear Register"
|
|
bitfld.word 0x00 3. " ADCINT4 ,ADC Interrupt 4 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 2. " ADCINT3 ,ADC Interrupt 3 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 1. " ADCINT2 ,ADC Interrupt 2 Overflow Clear Bits" "0,1"
|
|
bitfld.word 0x00 0. " ADCINT1 ,ADC Interrupt 1 Overflow Clear Bits" "0,1"
|
|
group.word (d:0x00007400+0x180+0x07)++0x01
|
|
line.word 0x00 "ADCINTSEL1N2,ADC Interrupt 1 and 2 Selection Register"
|
|
bitfld.word 0x00 14. " INT2CONT ,ADCINT2 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT2E ,ADCINT2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT2SEL ,ADCINT2 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT1CONT ,ADCINT1 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT1E ,ADCINT1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT1SEL ,ADCINT1 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x180+0x08)++0x01
|
|
line.word 0x00 "ADCINTSEL3N4,ADC Interrupt 3 and 4 Selection Register"
|
|
bitfld.word 0x00 14. " INT4CONT ,ADCINT4 Continue to Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 13. " INT4E ,ADCINT4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " INT4SEL ,ADCINT4 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 6. " INT3CONT ,ADCINT3 Continue to Interrupt Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " INT3E ,ADCINT3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " INT3SEL ,ADCINT3 EOC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00007400+0x180+0x09)++0x01
|
|
line.word 0x00 "ADCSOCPRICTL,ADC SOC Priority Control Register"
|
|
rbitfld.word 0x00 5.--9. " RRPOINTER ,Round Robin Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SOCPRIORITY ,SOC Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007400+0x180+0x0A)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL1,ADC Interrupt SOC Selection 1 Register"
|
|
bitfld.word 0x00 14.--15. " SOC7 ,SOC7 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC6 ,SOC6 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC5 ,SOC5 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC4 ,SOC4 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC3 ,SOC3 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC2 ,SOC2 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC1 ,SOC1 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC0 ,SOC0 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
group.word (d:0x00007400+0x180+0x0B)++0x01
|
|
line.word 0x00 "ADCINTSOCSEL2,ADC Interrupt SOC Selection 2 Register"
|
|
bitfld.word 0x00 14.--15. " SOC15 ,SOC15 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOC14 ,SOC14 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SOC13 ,SOC13 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOC12 ,SOC12 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SOC11 ,SOC11 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " SOC10 ,SOC10 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " SOC9 ,SOC9 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " SOC8 ,SOC8 ADC Interrupt Trigger Select" "0,1,2,3"
|
|
rgroup.word (d:0x00007400+0x180+0x0C)++0x01
|
|
line.word 0x00 "ADCSOCFLG1,ADC SOC Flag 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Flag" "0,1"
|
|
group.word (d:0x00007400+0x180+0x0D)++0x01
|
|
line.word 0x00 "ADCSOCFRC1,ADC SOC Force 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Force Start of Conversion Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Force Start of Conversion Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Force Start of Conversion Bit" "0,1"
|
|
rgroup.word (d:0x00007400+0x180+0x0E)++0x01
|
|
line.word 0x00 "ADCSOCOVF1,ADC SOC Overflow 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Start of Conversion Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Start of Conversion Overflow Flag" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Start of Conversion Overflow Flag" "0,1"
|
|
group.word (d:0x00007400+0x180+0x0F)++0x01
|
|
line.word 0x00 "ADCSOCOVFCLR1,ADC SOC Overflow Clear 1 Register"
|
|
bitfld.word 0x00 15. " SOC15 ,SOC15 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 14. " SOC14 ,SOC14 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 13. " SOC13 ,SOC13 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 12. " SOC12 ,SOC12 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOC11 ,SOC11 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 10. " SOC10 ,SOC10 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 9. " SOC9 ,SOC9 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 8. " SOC8 ,SOC8 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SOC7 ,SOC7 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 6. " SOC6 ,SOC6 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 5. " SOC5 ,SOC5 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 4. " SOC4 ,SOC4 Clear Start of Conversion Overflow Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " SOC3 ,SOC3 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 2. " SOC2 ,SOC2 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 1. " SOC1 ,SOC1 Clear Start of Conversion Overflow Bit" "0,1"
|
|
bitfld.word 0x00 0. " SOC0 ,SOC0 Clear Start of Conversion Overflow Bit" "0,1"
|
|
group.long (d:0x00007400+0x180+0x10)++0x03
|
|
line.long 0x00 "ADCSOC0CTL,ADC SOC0 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC0 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC0 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x180+0x12)++0x03
|
|
line.long 0x00 "ADCSOC1CTL,ADC SOC1 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC1 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC1 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x180+0x14)++0x03
|
|
line.long 0x00 "ADCSOC2CTL,ADC SOC2 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC2 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC2 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x180+0x16)++0x03
|
|
line.long 0x00 "ADCSOC3CTL,ADC SOC3 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC3 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC3 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x180+0x18)++0x03
|
|
line.long 0x00 "ADCSOC4CTL,ADC SOC4 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC4 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15.--18. " CHSEL ,SOC4 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale"
|
|
group.long (d:0x00007400+0x180+0x1A)++0x03
|
|
line.long 0x00 "ADCSOC5CTL,ADC SOC5 Control Register"
|
|
bitfld.long 0x00 20.--25. " TRIGSEL ,SOC5 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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bitfld.long 0x00 15.--18. " CHSEL ,SOC5 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x1C)++0x03
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line.long 0x00 "ADCSOC6CTL,ADC SOC6 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC6 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC6 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x1E)++0x03
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line.long 0x00 "ADCSOC7CTL,ADC SOC7 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC7 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC7 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x20)++0x03
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line.long 0x00 "ADCSOC8CTL,ADC SOC8 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC8 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC8 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x22)++0x03
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line.long 0x00 "ADCSOC9CTL,ADC SOC9 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC9 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC9 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x24)++0x03
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line.long 0x00 "ADCSOC10CTL,ADC SOC10 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC10 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC10 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x26)++0x03
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line.long 0x00 "ADCSOC11CTL,ADC SOC11 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC11 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC11 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x28)++0x03
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line.long 0x00 "ADCSOC12CTL,ADC SOC12 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC12 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC12 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x2A)++0x03
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line.long 0x00 "ADCSOC13CTL,ADC SOC13 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC13 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC13 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x2C)++0x03
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line.long 0x00 "ADCSOC14CTL,ADC SOC14 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC14 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC14 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale"
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group.long (d:0x00007400+0x180+0x2E)++0x03
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line.long 0x00 "ADCSOC15CTL,ADC SOC15 Control Register"
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bitfld.long 0x00 20.--25. " TRIGSEL ,SOC15 Trigger Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15.--18. " CHSEL ,SOC15 Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long 0x00 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale"
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rgroup.word (d:0x00007400+0x180+0x30)++0x01
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line.word 0x00 "ADCEVTSTAT,ADC Event Status Register"
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bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Flag" "0,1"
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bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Flag" "0,1"
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bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Flag" "0,1"
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bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Flag" "0,1"
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newline
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bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Flag" "0,1"
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bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Flag" "0,1"
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bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Flag" "0,1"
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bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Flag" "0,1"
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newline
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bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Flag" "0,1"
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bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Flag" "0,1"
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bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Flag" "0,1"
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bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Flag" "0,1"
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group.word (d:0x00007400+0x180+0x32)++0x01
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line.word 0x00 "ADCEVTCLR,ADC Event Clear Register"
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bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Clear" "0,1"
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bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Clear" "0,1"
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bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Clear" "0,1"
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bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Clear" "0,1"
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newline
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bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Clear" "0,1"
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bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Clear" "0,1"
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bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Clear" "0,1"
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bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Clear" "0,1"
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newline
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bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Clear" "0,1"
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bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Clear" "0,1"
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bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Clear" "0,1"
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bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Clear" "0,1"
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group.word (d:0x00007400+0x180+0x34)++0x01
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line.word 0x00 "ADCEVTSEL,ADC Event Selection Register"
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bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Event Enable" "0,1"
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bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Event Enable" "0,1"
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bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Event Enable" "0,1"
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bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Event Enable" "0,1"
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newline
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bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Event Enable" "0,1"
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bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Event Enable" "0,1"
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bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Event Enable" "0,1"
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bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Event Enable" "0,1"
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newline
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bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Event Enable" "0,1"
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bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Event Enable" "0,1"
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bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Event Enable" "0,1"
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bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Event Enable" "0,1"
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group.word (d:0x00007400+0x180+0x36)++0x01
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line.word 0x00 "ADCEVTINTSEL,ADC Event Interrupt Selection Register"
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bitfld.word 0x00 14. " PPB4ZERO ,Post Processing Block 4 Zero Crossing Interrupt Enable" "0,1"
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bitfld.word 0x00 13. " PPB4TRIPLO ,Post Processing Block 4 Trip Low Interrupt Enable" "0,1"
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bitfld.word 0x00 12. " PPB4TRIPHI ,Post Processing Block 4 Trip High Interrupt Enable" "0,1"
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bitfld.word 0x00 10. " PPB3ZERO ,Post Processing Block 3 Zero Crossing Interrupt Enable" "0,1"
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newline
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bitfld.word 0x00 9. " PPB3TRIPLO ,Post Processing Block 3 Trip Low Interrupt Enable" "0,1"
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bitfld.word 0x00 8. " PPB3TRIPHI ,Post Processing Block 3 Trip High Interrupt Enable" "0,1"
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bitfld.word 0x00 6. " PPB2ZERO ,Post Processing Block 2 Zero Crossing Interrupt Enable" "0,1"
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bitfld.word 0x00 5. " PPB2TRIPLO ,Post Processing Block 2 Trip Low Interrupt Enable" "0,1"
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newline
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bitfld.word 0x00 4. " PPB2TRIPHI ,Post Processing Block 2 Trip High Interrupt Enable" "0,1"
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bitfld.word 0x00 2. " PPB1ZERO ,Post Processing Block 1 Zero Crossing Interrupt Enable" "0,1"
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bitfld.word 0x00 1. " PPB1TRIPLO ,Post Processing Block 1 Trip Low Interrupt Enable" "0,1"
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bitfld.word 0x00 0. " PPB1TRIPHI ,Post Processing Block 1 Trip High Interrupt Enable" "0,1"
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rgroup.word (d:0x00007400+0x180+0x39)++0x01
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line.word 0x00 "ADCCOUNTER,ADC Counter Register"
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hexmask.word 0x00 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value"
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rgroup.word (d:0x00007400+0x180+0x3A)++0x01
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line.word 0x00 "ADCREV,ADC Revision Register"
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hexmask.word 0x00 8.--15. 1. "REV,ADC Revision"
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hexmask.word 0x00 0.--7. 1. "TYPE,ADC Type"
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group.word (d:0x00007400+0x180+0x3B)++0x01
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line.word 0x00 "ADCOFFTRIM,ADC Offset Trim Register"
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hexmask.word 0x00 0.--7. 1. "OFFTRIM,ADC Offset Trim"
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group.word (d:0x00007400+0x180+0x40)++0x01
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line.word 0x00 "ADCPPB1CONFIG,ADC PPB1 Config Register"
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bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
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bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 1 Two's Complement Enable" "0,1"
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bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 1 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word (d:0x00007400+0x180+0x41)++0x01
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line.word 0x00 "ADCPPB1STAMP,ADC PPB1 Sample Delay Time Stamp Register"
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hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp"
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group.word (d:0x00007400+0x180+0x42)++0x01
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line.word 0x00 "ADCPPB1OFFCAL,ADC PPB1 Offset Calibration Register"
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hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
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group.word (d:0x00007400+0x180+0x43)++0x01
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line.word 0x00 "ADCPPB1OFFREF,ADC PPB1 Offset Reference Register"
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group.long (d:0x00007400+0x180+0x44)++0x03
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line.long 0x00 "ADCPPB1TRIPHI,ADC PPB1 Trip High Register"
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bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
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hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit"
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group.long (d:0x00007400+0x180+0x46)++0x03
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line.long 0x00 "ADCPPB1TRIPLO,ADC PPB1 Trip Low/Trigger Time Stamp Register"
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hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp"
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bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
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hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit"
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group.word (d:0x00007400+0x180+0x48)++0x01
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line.word 0x00 "ADCPPB2CONFIG,ADC PPB2 Config Register"
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bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
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bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 2 Two's Complement Enable" "0,1"
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bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 2 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.word (d:0x00007400+0x180+0x49)++0x01
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|
line.word 0x00 "ADCPPB2STAMP,ADC PPB2 Sample Delay Time Stamp Register"
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hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp"
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group.word (d:0x00007400+0x180+0x4A)++0x01
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line.word 0x00 "ADCPPB2OFFCAL,ADC PPB2 Offset Calibration Register"
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hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
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group.word (d:0x00007400+0x180+0x4B)++0x01
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line.word 0x00 "ADCPPB2OFFREF,ADC PPB2 Offset Reference Register"
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group.long (d:0x00007400+0x180+0x4C)++0x03
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line.long 0x00 "ADCPPB2TRIPHI,ADC PPB2 Trip High Register"
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bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
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hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit"
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group.long (d:0x00007400+0x180+0x4E)++0x03
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line.long 0x00 "ADCPPB2TRIPLO,ADC PPB2 Trip Low/Trigger Time Stamp Register"
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|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp"
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|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit"
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group.word (d:0x00007400+0x180+0x50)++0x01
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|
line.word 0x00 "ADCPPB3CONFIG,ADC PPB3 Config Register"
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|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
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|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 3 Two's Complement Enable" "0,1"
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|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 3 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.word (d:0x00007400+0x180+0x51)++0x01
|
|
line.word 0x00 "ADCPPB3STAMP,ADC PPB3 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x180+0x52)++0x01
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|
line.word 0x00 "ADCPPB3OFFCAL,ADC PPB3 Offset Calibration Register"
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|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
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|
group.word (d:0x00007400+0x180+0x53)++0x01
|
|
line.word 0x00 "ADCPPB3OFFREF,ADC PPB3 Offset Reference Register"
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|
group.long (d:0x00007400+0x180+0x54)++0x03
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|
line.long 0x00 "ADCPPB3TRIPHI,ADC PPB3 Trip High Register"
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|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit"
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|
group.long (d:0x00007400+0x180+0x56)++0x03
|
|
line.long 0x00 "ADCPPB3TRIPLO,ADC PPB3 Trip Low/Trigger Time Stamp Register"
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|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp"
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|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
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|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit"
|
|
group.word (d:0x00007400+0x180+0x58)++0x01
|
|
line.word 0x00 "ADCPPB4CONFIG,ADC PPB4 Config Register"
|
|
bitfld.word 0x00 5. " CBCEN ,Cycle By Cycle Enable" "0,1"
|
|
bitfld.word 0x00 4. " TWOSCOMPEN ,ADC Post Processing Block 4 Two's Complement Enable" "0,1"
|
|
bitfld.word 0x00 0.--3. " CONFIG ,ADC Post Processing Block 4 Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00007400+0x180+0x59)++0x01
|
|
line.word 0x00 "ADCPPB4STAMP,ADC PPB4 Sample Delay Time Stamp Register"
|
|
hexmask.word 0x00 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp"
|
|
group.word (d:0x00007400+0x180+0x5A)++0x01
|
|
line.word 0x00 "ADCPPB4OFFCAL,ADC PPB4 Offset Calibration Register"
|
|
hexmask.word 0x00 0.--9. 1. "OFFCAL,ADC Post Processing Block Offset Correction"
|
|
group.word (d:0x00007400+0x180+0x5B)++0x01
|
|
line.word 0x00 "ADCPPB4OFFREF,ADC PPB4 Offset Reference Register"
|
|
group.long (d:0x00007400+0x180+0x5C)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPHI,ADC PPB4 Trip High Register"
|
|
bitfld.long 0x00 16. " HSIGN ,High Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit"
|
|
group.long (d:0x00007400+0x180+0x5E)++0x03
|
|
line.long 0x00 "ADCPPB4TRIPLO,ADC PPB4 Trip Low/Trigger Time Stamp Register"
|
|
hexmask.long 0x00 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp"
|
|
bitfld.long 0x00 16. " LSIGN ,Low Limit Sign Bit" "0,1"
|
|
hexmask.long 0x00 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit"
|
|
group.word (d:0x00007400+0x180+0x6F)++0x01
|
|
line.word 0x00 "ADCINTCYCLE,ADC Early Interrupt Generation Cycle"
|
|
group.long (d:0x00007400+0x180+0x70)++0x03
|
|
line.long 0x00 "ADCINLTRIM1,ADC Linearity Trim 1 Register"
|
|
group.long (d:0x00007400+0x180+0x72)++0x03
|
|
line.long 0x00 "ADCINLTRIM2,ADC Linearity Trim 2 Register"
|
|
group.long (d:0x00007400+0x180+0x74)++0x03
|
|
line.long 0x00 "ADCINLTRIM3,ADC Linearity Trim 3 Register"
|
|
group.long (d:0x00007400+0x180+0x76)++0x03
|
|
line.long 0x00 "ADCINLTRIM4,ADC Linearity Trim 4 Register"
|
|
group.long (d:0x00007400+0x180+0x78)++0x03
|
|
line.long 0x00 "ADCINLTRIM5,ADC Linearity Trim 5 Register"
|
|
group.long (d:0x00007400+0x180+0x7A)++0x03
|
|
line.long 0x00 "ADCINLTRIM6,ADC Linearity Trim 6 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Analog Subsystem"
|
|
width 13.
|
|
group.long (d:0x0005D700+0x20)++0x03
|
|
line.long 0x00 "INTOSC1TRIM,Internal Oscillator 1 Trim Register"
|
|
hexmask.long 0x00 0.--11. 1. "VALFINETRIM,Oscillator Value Fine Trim Bits"
|
|
group.long (d:0x0005D700+0x22)++0x03
|
|
line.long 0x00 "INTOSC2TRIM,Internal Oscillator 2 Trim Register"
|
|
hexmask.long 0x00 0.--11. 1. "VALFINETRIM,Oscillator Value Fine Trim Bits"
|
|
group.word (d:0x0005D700+0x26)++0x01
|
|
line.word 0x00 "TSNSCTL,Temperature Sensor Control Register"
|
|
bitfld.word 0x00 0. " ENABLE ,Temperature Sensor Enable" "0,1"
|
|
group.long (d:0x0005D700+0x2E)++0x03
|
|
line.long 0x00 "LOCK,Lock Register"
|
|
bitfld.long 0x00 3. " TSNSCTL ,Temperature Sensor Control Register Lock" "0,1"
|
|
group.long (d:0x0005D700+0x36)++0x03
|
|
line.long 0x00 "ANAREFTRIMA,Analog Reference Trim A Register"
|
|
bitfld.long 0x00 11.--15. " IREFTRIM ,Reference Current Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " BGSLOPETRIM ,Bandgap Slope Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " BGVALTRIM ,Bandgap Value Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005D700+0x38)++0x03
|
|
line.long 0x00 "ANAREFTRIMB,Analog Reference Trim B Register"
|
|
bitfld.long 0x00 11.--15. " IREFTRIM ,Reference Current Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " BGSLOPETRIM ,Bandgap Slope Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " BGVALTRIM ,Bandgap Value Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005D700+0x3A)++0x03
|
|
line.long 0x00 "ANAREFTRIMC,Analog Reference Trim C Register"
|
|
bitfld.long 0x00 11.--15. " IREFTRIM ,Reference Current Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " BGSLOPETRIM ,Bandgap Slope Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " BGVALTRIM ,Bandgap Value Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005D700+0x3C)++0x03
|
|
line.long 0x00 "ANAREFTRIMD,Analog Reference Trim D Register"
|
|
bitfld.long 0x00 11.--15. " IREFTRIM ,Reference Current Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. " BGSLOPETRIM ,Bandgap Slope Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " BGVALTRIM ,Bandgap Value Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Background CRC-32 (BGCRC)"
|
|
width 18.
|
|
group.long (d:0x00006340+0x00)++0x03
|
|
line.long 0x00 "BGCRC_EN,BGCRC Enable"
|
|
rbitfld.long 0x00 31. " RUN_STS ,CRC module activity monitor" "0,1"
|
|
bitfld.long 0x00 0.--3. " START ,Start Bit used to Kick-off CRC calculations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006340+0x02)++0x03
|
|
line.long 0x00 "BGCRC_CTRL1,BGCRC Control register 1"
|
|
bitfld.long 0x00 16.--19. " NMIDIS ,NMI disable configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " FREE_SOFT ,emulation control bit" "0,1"
|
|
group.long (d:0x00006340+0x04)++0x03
|
|
line.long 0x00 "BGCRC_CTRL2,BGCRC Control register 2"
|
|
bitfld.long 0x00 16.--19. " SCRUB_MODE ,Scrub mode configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TEST_HALT ,TEST_HALT configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 0.--9. 1. "BLOCK_SIZE,block size for memory check"
|
|
group.long (d:0x00006340+0x06)++0x03
|
|
line.long 0x00 "BGCRC_START_ADDR,Start address for the BGCRC check"
|
|
group.long (d:0x00006340+0x08)++0x03
|
|
line.long 0x00 "BGCRC_SEED,Seed for CRC calculation"
|
|
group.long (d:0x00006340+0x0E)++0x03
|
|
line.long 0x00 "BGCRC_GOLDEN,Golden CRC to be compared against"
|
|
rgroup.long (d:0x00006340+0x10)++0x03
|
|
line.long 0x00 "BGCRC_RESULT,CRC calculated"
|
|
rgroup.long (d:0x00006340+0x12)++0x03
|
|
line.long 0x00 "BGCRC_CURR_ADDR,Current address regsiter"
|
|
group.long (d:0x00006340+0x1C)++0x03
|
|
line.long 0x00 "BGCRC_WD_CFG,BGCRC windowed watchdog configuration"
|
|
bitfld.long 0x00 0.--3. " WDDIS ,CRC Watchdog disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006340+0x1E)++0x03
|
|
line.long 0x00 "BGCRC_WD_MIN,BGCRC windowed watchdog min value"
|
|
group.long (d:0x00006340+0x20)++0x03
|
|
line.long 0x00 "BGCRC_WD_MAX,BGCRC windowed watchdog max value"
|
|
rgroup.long (d:0x00006340+0x22)++0x03
|
|
line.long 0x00 "BGCRC_WD_CNT,BGCRC windowed watchdog count"
|
|
rgroup.long (d:0x00006340+0x2A)++0x03
|
|
line.long 0x00 "BGCRC_NMIFLG,BGCRC NMI flag register"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,CRC/scrubbing did not complete within BGCRC_WD_MAX" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,CRC/scrubbing completed before BGCRC_WD_MIN" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,Correctable ECC error obtained during memory data read." "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,Uncorrectable error obtained during memory data read." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC computation failed" "0,1"
|
|
group.long (d:0x00006340+0x2C)++0x03
|
|
line.long 0x00 "BGCRC_NMICLR,BGCRC NMI flag clear register"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,WD_OVERFLOW NMI flag clear" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,WD_UNDERFLOW NMI flag clear" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,CORRECTABLE_ERR NMI flag clear" "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,UNCORRECTABLE_ERR NMI flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC_FAIL NMI flag clear" "0,1"
|
|
group.long (d:0x00006340+0x2E)++0x03
|
|
line.long 0x00 "BGCRC_NMIFRC,BGCRC NMI flag force register"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,WD_OVERFLOW NMI force" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,WD_UNDERFLOW NMI force" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,CORRECTABLE_ERR NMI force" "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,UNCORRECTABLE_ERR NMI force" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC_FAIL NMI force" "0,1"
|
|
group.long (d:0x00006340+0x34)++0x03
|
|
line.long 0x00 "BGCRC_INTEN,Interrupt enable"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,WD_OVERFLOW interrupt enable register" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,WD_UNDERFLOW interrupt enable register" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,CORRECTABLE_ERR interrupt enable register" "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,UNCORRECTABLE_ERR interrupt enable register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC_FAIL interrupt enable register" "0,1"
|
|
bitfld.long 0x00 1. " TEST_DONE ,TEST_DONE interrupt enable register" "0,1"
|
|
rgroup.long (d:0x00006340+0x36)++0x03
|
|
line.long 0x00 "BGCRC_INTFLG,Interrupt flag"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,CRC/scrubbing did not complete within BGCRC_WD_MAX" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,CRC/scrubbing completed before BGCRC_WD_MIN" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,Correctable ECC error obtained during memory data read." "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,Uncorrectable error obtained during memory data read." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC computation failed" "0,1"
|
|
bitfld.long 0x00 1. " TEST_DONE ,TEST_DONE Interrupt status flag" "0,1"
|
|
bitfld.long 0x00 0. " INT ,Global Interrupt status flag" "0,1"
|
|
group.long (d:0x00006340+0x38)++0x03
|
|
line.long 0x00 "BGCRC_INTCLR,Interrupt flag clear"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,WD_OVERFLOW interrupt clear" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,WD_UNDERFLOW interrupt clear" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,CORRECTABLE_ERR interrupt clear" "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,UNCORRECTABLE_ERR interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC_FAIL interrupt clear" "0,1"
|
|
bitfld.long 0x00 1. " TEST_DONE ,TEST_DONE Interrupt clear" "0,1"
|
|
bitfld.long 0x00 0. " INT ,Global Interrupt clear" "0,1"
|
|
group.long (d:0x00006340+0x3A)++0x03
|
|
line.long 0x00 "BGCRC_INTFRC,Interrupt flag force"
|
|
bitfld.long 0x00 6. " WD_OVERFLOW ,WD_OVERFLOW interrupt force" "0,1"
|
|
bitfld.long 0x00 5. " WD_UNDERFLOW ,WD_UNDERFLOW interrupt force" "0,1"
|
|
bitfld.long 0x00 4. " CORRECTABLE_ERR ,CORRECTABLE_ERR interrupt force" "0,1"
|
|
bitfld.long 0x00 3. " UNCORRECTABLE_ERR ,UNCORRECTABLE_ERR interrupt force" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CRC_FAIL ,CRC_FAIL interrupt force" "0,1"
|
|
bitfld.long 0x00 1. " TEST_DONE ,TEST_DONE Interrupt force" "0,1"
|
|
group.long (d:0x00006340+0x3C)++0x03
|
|
line.long 0x00 "BGCRC_LOCK,BGCRC register map lockconfiguration"
|
|
bitfld.long 0x00 29. " BGCRC_INTFRC ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 26. " BGCRC_INTEN ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 23. " BGCRC_NMIFRC ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 16. " BGCRC_WD_MAX ,Register lock configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " BGCRC_WD_MIN ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 14. " BGCRC_WD_CFG ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 7. " BGCRC_GOLDEN ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 4. " BGCRC_SEED ,Register lock configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " BGCRC_START_ADDR ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 2. " BGCRC_CTRL2 ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 1. " BGCRC_CTRL1 ,Register lock configuration" "0,1"
|
|
bitfld.long 0x00 0. " BGCRC_EN ,Register lock configuration" "0,1"
|
|
group.long (d:0x00006340+0x3E)++0x03
|
|
line.long 0x00 "BGCRC_COMMIT,BGCRC register map commit configuration"
|
|
bitfld.long 0x00 29. " BGCRC_INTFRC ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 26. " BGCRC_INTEN ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 23. " BGCRC_NMIFRC ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 16. " BGCRC_WD_MAX ,Register lock committed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " BGCRC_WD_MIN ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 14. " BGCRC_WD_CFG ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 7. " BGCRC_GOLDEN ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 4. " BGCRC_SEED ,Register lock committed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " BGCRC_START_ADDR ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 2. " BGCRC_CTRL2 ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 1. " BGCRC_CTRL1 ,Register lock committed" "0,1"
|
|
bitfld.long 0x00 0. " BGCRC_EN ,Register lock committed" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Controller Area Network (CAN)"
|
|
tree "CAN A"
|
|
width 17.
|
|
group.long (d:0x00048000+0x00)++0x03
|
|
line.long 0x00 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x00 20. " DE3 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 19. " DE2 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 18. " DE1 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 17. " IE1 ,Interrupt line 1 Enable Disabled" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. " INITDBG ,Debug Mode Status" "0,1"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "0,1"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. " ABO ,Auto-Bus-On Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x00 7. " Test ,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. " SIE ,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. " IE0 ,Interrupt line 0 Enable" "0,1"
|
|
bitfld.long 0x00 0. " Init ,Initialization" "0,1"
|
|
rgroup.long (d:0x00048000+0x04)++0x03
|
|
line.long 0x00 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x00 8. " PER ,Parity Error Detected" "0,1"
|
|
bitfld.long 0x00 7. " BOff ,Bus-Off State" "0,1"
|
|
bitfld.long 0x00 6. " EWarn ,Warning State" "0,1"
|
|
bitfld.long 0x00 5. " EPass ,Error Passive State" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " RxOk ,Reception status" "0,1"
|
|
bitfld.long 0x00 3. " TxOk ,Transmission status" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x00048000+0x08)++0x03
|
|
line.long 0x00 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "0,1"
|
|
bitfld.long 0x00 8.--14. " REC ,Receive Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long (d:0x00048000+0x0C)++0x03
|
|
line.long 0x00 "CAN_BTR,Bit Timing Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long (d:0x00048000+0x10)++0x03
|
|
line.long 0x00 "CAN_INT,Interrupt Register"
|
|
hexmask.long 0x00 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long 0x00 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long (d:0x00048000+0x14)++0x03
|
|
line.long 0x00 "CAN_TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x00 8. " EXL ,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x00 7. " RX ,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x00 5.--6. " TX ,CANTX Pin Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. " LBACK ,Loopback Mode" "0,1"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "0,1"
|
|
rgroup.long (d:0x00048000+0x1C)++0x03
|
|
line.long 0x00 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUM ,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x00048000+0x40)++0x03
|
|
line.long 0x00 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x00 5. " RAM_INIT_DONE ,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x00 4. " CAN_RAM_INIT ,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x00 3. " KEY3 ,KEY3" "0,1"
|
|
bitfld.long 0x00 2. " KEY2 ,KEY2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY1 ,KEY1" "0,1"
|
|
bitfld.long 0x00 0. " KEY0 ,KEY0" "0,1"
|
|
group.long (d:0x00048000+0x50)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " GLBINT1_EN ,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " GLBINT0_EN ,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long (d:0x00048000+0x54)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x00 1. " INT1_FLG ,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " INT0_FLG ,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long (d:0x00048000+0x58)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " INT1_FLG_CLR ,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " INT0_FLG_CLR ,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long (d:0x00048000+0x80)++0x03
|
|
line.long 0x00 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
rgroup.long (d:0x00048000+0x84)++0x03
|
|
line.long 0x00 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x00 2.--3. " TxRqstReg2 ,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TxRqstReg1 ,Transmit Request Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x00048000+0x88)++0x03
|
|
line.long 0x00 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
rgroup.long (d:0x00048000+0x98)++0x03
|
|
line.long 0x00 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x00 2.--3. " NewDatReg2 ,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " NewDatReg1 ,New Data Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x00048000+0x9C)++0x03
|
|
line.long 0x00 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
rgroup.long (d:0x00048000+0xAC)++0x03
|
|
line.long 0x00 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x00 2.--3. " IntPndReg2 ,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " IntPndReg1 ,Interrupt Pending Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x00048000+0xB0)++0x03
|
|
line.long 0x00 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
rgroup.long (d:0x00048000+0xC0)++0x03
|
|
line.long 0x00 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x00 2.--3. " MsgValReg2 ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MsgValReg1 ,Message Valid Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x00048000+0xC4)++0x03
|
|
line.long 0x00 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
group.long (d:0x00048000+0xD8)++0x03
|
|
line.long 0x00 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
group.long (d:0x00048000+0x100)++0x03
|
|
line.long 0x00 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " DIR ,Write/Read Direction" "0,1"
|
|
bitfld.long 0x00 22. " Mask ,Access Mask Bits" "0,1"
|
|
bitfld.long 0x00 21. " Arb ,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x00 20. " Control ,Access Control Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ClrIntPnd ,Clear Interrupt Pending Bit" "0,1"
|
|
bitfld.long 0x00 18. " TXRQST ,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. " Busy ,Busy Flag" "0,1"
|
|
bitfld.long 0x00 14. " DMAactive ,DMA Status" "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x00048000+0x104)++0x03
|
|
line.long 0x00 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Identifier Mask"
|
|
group.long (d:0x00048000+0x108)++0x03
|
|
line.long 0x00 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,`"
|
|
group.long (d:0x00048000+0x10C)++0x03
|
|
line.long 0x00 "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00048000+0x110)++0x03
|
|
line.long 0x00 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
group.long (d:0x00048000+0x114)++0x03
|
|
line.long 0x00 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x00048000+0x120)++0x03
|
|
line.long 0x00 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " DIR ,Write/Read Direction" "0,1"
|
|
bitfld.long 0x00 22. " Mask ,Access Mask Bits" "0,1"
|
|
bitfld.long 0x00 21. " Arb ,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x00 20. " Control ,Access Control Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ClrIntPnd ,Clear Interrupt Pending Bit" "0,1"
|
|
bitfld.long 0x00 18. " TxRqst ,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. " Busy ,Busy Flag" "0,1"
|
|
bitfld.long 0x00 14. " DMAactive ,DMA Status" "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x00048000+0x124)++0x03
|
|
line.long 0x00 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Identifier Mask"
|
|
group.long (d:0x00048000+0x128)++0x03
|
|
line.long 0x00 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Message Identifier"
|
|
group.long (d:0x00048000+0x12C)++0x03
|
|
line.long 0x00 "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00048000+0x130)++0x03
|
|
line.long 0x00 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
group.long (d:0x00048000+0x134)++0x03
|
|
line.long 0x00 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x00048000+0x140)++0x03
|
|
line.long 0x00 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x00 15. " IF3Upd ,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control bits read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "0,1"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x00 4. " Data_B ,Data B read observation" "0,1"
|
|
bitfld.long 0x00 3. " Data_A ,Data A read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " Ctrl ,Ctrl read observation" "0,1"
|
|
bitfld.long 0x00 1. " Arb ,Arbitration data read observation" "0,1"
|
|
bitfld.long 0x00 0. " Mask ,Mask data read observation" "0,1"
|
|
rgroup.long (d:0x00048000+0x144)++0x03
|
|
line.long 0x00 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Mask"
|
|
rgroup.long (d:0x00048000+0x148)++0x03
|
|
line.long 0x00 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Message Identifier"
|
|
rgroup.long (d:0x00048000+0x14C)++0x03
|
|
line.long 0x00 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x00048000+0x150)++0x03
|
|
line.long 0x00 "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
rgroup.long (d:0x00048000+0x154)++0x03
|
|
line.long 0x00 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x00048000+0x160)++0x03
|
|
line.long 0x00 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN B"
|
|
width 17.
|
|
group.long (d:0x0004A000+0x00)++0x03
|
|
line.long 0x00 "CAN_CTL,CAN Control Register"
|
|
bitfld.long 0x00 20. " DE3 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 19. " DE2 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 18. " DE1 ,Enable DMA request line" "0,1"
|
|
bitfld.long 0x00 17. " IE1 ,Interrupt line 1 Enable Disabled" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. " INITDBG ,Debug Mode Status" "0,1"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "0,1"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. " ABO ,Auto-Bus-On Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "0,1"
|
|
bitfld.long 0x00 7. " Test ,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. " SIE ,Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. " IE0 ,Interrupt line 0 Enable" "0,1"
|
|
bitfld.long 0x00 0. " Init ,Initialization" "0,1"
|
|
rgroup.long (d:0x0004A000+0x04)++0x03
|
|
line.long 0x00 "CAN_ES,Error and Status Register"
|
|
bitfld.long 0x00 8. " PER ,Parity Error Detected" "0,1"
|
|
bitfld.long 0x00 7. " BOff ,Bus-Off State" "0,1"
|
|
bitfld.long 0x00 6. " EWarn ,Warning State" "0,1"
|
|
bitfld.long 0x00 5. " EPass ,Error Passive State" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " RxOk ,Reception status" "0,1"
|
|
bitfld.long 0x00 3. " TxOk ,Transmission status" "0,1"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x0004A000+0x08)++0x03
|
|
line.long 0x00 "CAN_ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "0,1"
|
|
bitfld.long 0x00 8.--14. " REC ,Receive Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long (d:0x0004A000+0x0C)++0x03
|
|
line.long 0x00 "CAN_BTR,Bit Timing Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long (d:0x0004A000+0x10)++0x03
|
|
line.long 0x00 "CAN_INT,Interrupt Register"
|
|
hexmask.long 0x00 16.--23. 1. "INT1ID,Interrupt 1 Identifier"
|
|
hexmask.long 0x00 0.--15. 1. "INT0ID,Interrupt Identifier"
|
|
group.long (d:0x0004A000+0x14)++0x03
|
|
line.long 0x00 "CAN_TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable:" "0,1"
|
|
bitfld.long 0x00 8. " EXL ,External Loopback Mode" "0,1"
|
|
rbitfld.long 0x00 7. " RX ,CANRX Pin Status" "0,1"
|
|
bitfld.long 0x00 5.--6. " TX ,CANTX Pin Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. " LBACK ,Loopback Mode" "0,1"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "0,1"
|
|
rgroup.long (d:0x0004A000+0x1C)++0x03
|
|
line.long 0x00 "CAN_PERR,CAN Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUM ,Word Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x0004A000+0x40)++0x03
|
|
line.long 0x00 "CAN_RAM_INIT,CAN RAM Initialization Register"
|
|
rbitfld.long 0x00 5. " RAM_INIT_DONE ,CAN RAM initialization complete" "0,1"
|
|
bitfld.long 0x00 4. " CAN_RAM_INIT ,Initialize CAN Mailbox RAM" "0,1"
|
|
bitfld.long 0x00 3. " KEY3 ,KEY3" "0,1"
|
|
bitfld.long 0x00 2. " KEY2 ,KEY2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY1 ,KEY1" "0,1"
|
|
bitfld.long 0x00 0. " KEY0 ,KEY0" "0,1"
|
|
group.long (d:0x0004A000+0x50)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_EN,CAN Global Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " GLBINT1_EN ,Global Interrupt Enable for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " GLBINT0_EN ,Global Interrupt Enable for CANINT0" "0,1"
|
|
rgroup.long (d:0x0004A000+0x54)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_FLG,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x00 1. " INT1_FLG ,Global Interrupt Flag for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " INT0_FLG ,Global Interrupt Flag for CANINT0" "0,1"
|
|
group.long (d:0x0004A000+0x58)++0x03
|
|
line.long 0x00 "CAN_GLB_INT_CLR,CAN Global Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " INT1_FLG_CLR ,Global Interrupt flag clear for CANINT1" "0,1"
|
|
bitfld.long 0x00 0. " INT0_FLG_CLR ,Global Interrupt flag clear for CANINT0" "0,1"
|
|
group.long (d:0x0004A000+0x80)++0x03
|
|
line.long 0x00 "CAN_ABOTR,Auto-Bus-On Time Register"
|
|
rgroup.long (d:0x0004A000+0x84)++0x03
|
|
line.long 0x00 "CAN_TXRQ_X,CAN Transmission Request Register"
|
|
bitfld.long 0x00 2.--3. " TxRqstReg2 ,Transmit Request Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TxRqstReg1 ,Transmit Request Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x0004A000+0x88)++0x03
|
|
line.long 0x00 "CAN_TXRQ_21,CAN Transmission Request 2_1 Register"
|
|
rgroup.long (d:0x0004A000+0x98)++0x03
|
|
line.long 0x00 "CAN_NDAT_X,CAN New Data Register"
|
|
bitfld.long 0x00 2.--3. " NewDatReg2 ,New Data Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " NewDatReg1 ,New Data Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x0004A000+0x9C)++0x03
|
|
line.long 0x00 "CAN_NDAT_21,CAN New Data 2_1 Register"
|
|
rgroup.long (d:0x0004A000+0xAC)++0x03
|
|
line.long 0x00 "CAN_IPEN_X,CAN Interrupt Pending Register"
|
|
bitfld.long 0x00 2.--3. " IntPndReg2 ,Interrupt Pending Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " IntPndReg1 ,Interrupt Pending Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x0004A000+0xB0)++0x03
|
|
line.long 0x00 "CAN_IPEN_21,CAN Interrupt Pending 2_1 Register"
|
|
rgroup.long (d:0x0004A000+0xC0)++0x03
|
|
line.long 0x00 "CAN_MVAL_X,CAN Message Valid Register"
|
|
bitfld.long 0x00 2.--3. " MsgValReg2 ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MsgValReg1 ,Message Valid Register 1" "0,1,2,3"
|
|
rgroup.long (d:0x0004A000+0xC4)++0x03
|
|
line.long 0x00 "CAN_MVAL_21,CAN Message Valid 2_1 Register"
|
|
group.long (d:0x0004A000+0xD8)++0x03
|
|
line.long 0x00 "CAN_IP_MUX21,CAN Interrupt Multiplexer 2_1 Register"
|
|
group.long (d:0x0004A000+0x100)++0x03
|
|
line.long 0x00 "CAN_IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " DIR ,Write/Read Direction" "0,1"
|
|
bitfld.long 0x00 22. " Mask ,Access Mask Bits" "0,1"
|
|
bitfld.long 0x00 21. " Arb ,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x00 20. " Control ,Access Control Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ClrIntPnd ,Clear Interrupt Pending Bit" "0,1"
|
|
bitfld.long 0x00 18. " TXRQST ,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. " Busy ,Busy Flag" "0,1"
|
|
bitfld.long 0x00 14. " DMAactive ,DMA Status" "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x0004A000+0x104)++0x03
|
|
line.long 0x00 "CAN_IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Identifier Mask"
|
|
group.long (d:0x0004A000+0x108)++0x03
|
|
line.long 0x00 "CAN_IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,`"
|
|
group.long (d:0x0004A000+0x10C)++0x03
|
|
line.long 0x00 "CAN_IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0004A000+0x110)++0x03
|
|
line.long 0x00 "CAN_IF1DATA,IF1 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
group.long (d:0x0004A000+0x114)++0x03
|
|
line.long 0x00 "CAN_IF1DATB,IF1 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x0004A000+0x120)++0x03
|
|
line.long 0x00 "CAN_IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " DIR ,Write/Read Direction" "0,1"
|
|
bitfld.long 0x00 22. " Mask ,Access Mask Bits" "0,1"
|
|
bitfld.long 0x00 21. " Arb ,Access Arbitration Bits" "0,1"
|
|
bitfld.long 0x00 20. " Control ,Access Control Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ClrIntPnd ,Clear Interrupt Pending Bit" "0,1"
|
|
bitfld.long 0x00 18. " TxRqst ,Access Transmission Request Bit" "0,1"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "0,1"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 15. " Busy ,Busy Flag" "0,1"
|
|
bitfld.long 0x00 14. " DMAactive ,DMA Status" "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MSG_NUM,Message Number"
|
|
group.long (d:0x0004A000+0x124)++0x03
|
|
line.long 0x00 "CAN_IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Identifier Mask"
|
|
group.long (d:0x0004A000+0x128)++0x03
|
|
line.long 0x00 "CAN_IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Message Identifier"
|
|
group.long (d:0x0004A000+0x12C)++0x03
|
|
line.long 0x00 "CAN_IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0004A000+0x130)++0x03
|
|
line.long 0x00 "CAN_IF2DATA,IF2 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
group.long (d:0x0004A000+0x134)++0x03
|
|
line.long 0x00 "CAN_IF2DATB,IF2 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x0004A000+0x140)++0x03
|
|
line.long 0x00 "CAN_IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x00 15. " IF3Upd ,IF3 Update Data" "0,1"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "0,1"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "0,1"
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control bits read access" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "0,1"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "0,1"
|
|
bitfld.long 0x00 4. " Data_B ,Data B read observation" "0,1"
|
|
bitfld.long 0x00 3. " Data_A ,Data A read observation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " Ctrl ,Ctrl read observation" "0,1"
|
|
bitfld.long 0x00 1. " Arb ,Arbitration data read observation" "0,1"
|
|
bitfld.long 0x00 0. " Mask ,Mask data read observation" "0,1"
|
|
rgroup.long (d:0x0004A000+0x144)++0x03
|
|
line.long 0x00 "CAN_IF3MSK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "0,1"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "Msk,Mask"
|
|
rgroup.long (d:0x0004A000+0x148)++0x03
|
|
line.long 0x00 "CAN_IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x00 31. " MsgVal ,Message Valid" "0,1"
|
|
bitfld.long 0x00 30. " Xtd ,Extended Identifier" "0,1"
|
|
bitfld.long 0x00 29. " Dir ,Message Direction" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Message Identifier"
|
|
rgroup.long (d:0x0004A000+0x14C)++0x03
|
|
line.long 0x00 "CAN_IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NewDat ,New Data" "0,1"
|
|
bitfld.long 0x00 14. " MsgLst ,Message Lost" "0,1"
|
|
bitfld.long 0x00 13. " IntPnd ,Interrupt Pending" "0,1"
|
|
bitfld.long 0x00 12. " UMask ,Use Acceptance Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TxIE ,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 10. " RxIE ,Receive Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 9. " RmtEn ,Remote Enable" "0,1"
|
|
bitfld.long 0x00 8. " TxRqst ,Transmit Request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EoB ,End of Block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x0004A000+0x150)++0x03
|
|
line.long 0x00 "CAN_IF3DATA,IF3 Data A Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_3,Data Byte 3"
|
|
hexmask.long 0x00 16.--23. 1. "Data_2,Data Byte 2"
|
|
hexmask.long 0x00 8.--15. 1. "Data_1,Data Byte 1"
|
|
hexmask.long 0x00 0.--7. 1. "Data_0,Data Byte 0"
|
|
rgroup.long (d:0x0004A000+0x154)++0x03
|
|
line.long 0x00 "CAN_IF3DATB,IF3 Data B Register"
|
|
hexmask.long 0x00 24.--31. 1. "Data_7,Data Byte 7"
|
|
hexmask.long 0x00 16.--23. 1. "Data_6,Data Byte 6"
|
|
hexmask.long 0x00 8.--15. 1. "Data_5,Data Byte 5"
|
|
hexmask.long 0x00 0.--7. 1. "Data_4,Data Byte 4"
|
|
group.long (d:0x0004A000+0x160)++0x03
|
|
line.long 0x00 "CAN_IF3UPD,IF3 Update Enable Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Control Law Accelerator (CLA)"
|
|
tree "CPU1Cla1Regs"
|
|
width 19.
|
|
group.word (d:0x00001400+0x00)++0x01
|
|
line.word 0x00 "MVECT1,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x01)++0x01
|
|
line.word 0x00 "MVECT2,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x02)++0x01
|
|
line.word 0x00 "MVECT3,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x03)++0x01
|
|
line.word 0x00 "MVECT4,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x04)++0x01
|
|
line.word 0x00 "MVECT5,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x05)++0x01
|
|
line.word 0x00 "MVECT6,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x06)++0x01
|
|
line.word 0x00 "MVECT7,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x07)++0x01
|
|
line.word 0x00 "MVECT8,Task Interrupt Vector"
|
|
group.word (d:0x00001400+0x10)++0x01
|
|
line.word 0x00 "MCTL,Control Register"
|
|
bitfld.word 0x00 2. " IACKE ,IACK enable" "0,1"
|
|
bitfld.word 0x00 1. " SOFTRESET ,Soft Reset" "0,1"
|
|
bitfld.word 0x00 0. " HARDRESET ,Hard Reset" "0,1"
|
|
rgroup.word (d:0x00001400+0x1B)++0x01
|
|
line.word 0x00 "_MVECTBGRNDACTIVE,Active register for MVECTBGRND."
|
|
group.word (d:0x00001400+0x1C)++0x01
|
|
line.word 0x00 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " TASK8 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 6. " TASK7 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 5. " TASK6 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 4. " TASK5 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " TASK4 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 2. " TASK3 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 1. " TASK2 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 0. " TASK1 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
group.word (d:0x00001400+0x1D)++0x01
|
|
line.word 0x00 "_MSTSBGRND,Status register for the back ground task."
|
|
bitfld.word 0x00 2. " BGOVF ,background task harware trigger overflow." "0,1"
|
|
rbitfld.word 0x00 1. " _BGINTM ,Indicates whether background task can be interrupted." "0,1"
|
|
rbitfld.word 0x00 0. " RUN ,Background task run status bit." "0,1"
|
|
group.word (d:0x00001400+0x1E)++0x01
|
|
line.word 0x00 "_MCTLBGRND,Control register for the back ground task."
|
|
bitfld.word 0x00 15. " BGEN ,Enable background task" "0,1"
|
|
bitfld.word 0x00 1. " TRIGEN ,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x00 0. " BGSTART ,Background task start bit" "0,1"
|
|
group.word (d:0x00001400+0x1F)++0x01
|
|
line.word 0x00 "_MVECTBGRND,Vector for the back ground task."
|
|
rgroup.word (d:0x00001400+0x20)++0x01
|
|
line.word 0x00 "MIFR,Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Flag" "0,1"
|
|
rgroup.word (d:0x00001400+0x21)++0x01
|
|
line.word 0x00 "MIOVF,Interrupt Overflow Flag Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Overflow Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Overflow Flag" "0,1"
|
|
group.word (d:0x00001400+0x22)++0x01
|
|
line.word 0x00 "MIFRC,Interrupt Force Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Force" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Force" "0,1"
|
|
group.word (d:0x00001400+0x23)++0x01
|
|
line.word 0x00 "MICLR,Interrupt Flag Clear Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Flag Clear" "0,1"
|
|
group.word (d:0x00001400+0x24)++0x01
|
|
line.word 0x00 "MICLROVF,Interrupt Overflow Flag Clear Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Overflow Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Overflow Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Overflow Flag Clear" "0,1"
|
|
group.word (d:0x00001400+0x25)++0x01
|
|
line.word 0x00 "MIER,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00001400+0x26)++0x01
|
|
line.word 0x00 "MIRUN,Interrupt Run Status Register"
|
|
bitfld.word 0x00 7. " INT8 ,Task 8 Run Status" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Task 7 Run Status" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Task 6 Run Status" "0,1"
|
|
bitfld.word 0x00 4. " INT5 ,Task 5 Run Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT4 ,Task 4 Run Status" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Task 3 Run Status" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Task 2 Run Status" "0,1"
|
|
bitfld.word 0x00 0. " INT1 ,Task 1 Run Status" "0,1"
|
|
rgroup.word (d:0x00001400+0x28)++0x01
|
|
line.word 0x00 "_MPC,CLA Program Counter"
|
|
rgroup.word (d:0x00001400+0x2A)++0x01
|
|
line.word 0x00 "_MAR0,CLA Auxiliary Register 0"
|
|
rgroup.word (d:0x00001400+0x2B)++0x01
|
|
line.word 0x00 "_MAR1,CLA Auxiliary Register 1"
|
|
rgroup.long (d:0x00001400+0x2E)++0x03
|
|
line.long 0x00 "_MSTF,CLA Floating-Point Status Register"
|
|
hexmask.long 0x00 12.--27. 1. "_RPC,Return PC"
|
|
bitfld.long 0x00 11. " MEALLOW ,MEALLOW Status" "0,1"
|
|
bitfld.long 0x00 9. " RNDF32 ,Round 32-bit Floating-Point Mode" "0,1"
|
|
bitfld.long 0x00 6. " TF ,Test Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ZF ,Zero Float Flag" "0,1"
|
|
bitfld.long 0x00 2. " NF ,Negative Float Flag" "0,1"
|
|
bitfld.long 0x00 1. " LUF ,Latched Underflow Flag" "0,1"
|
|
bitfld.long 0x00 0. " LVF ,Latched Overflow Flag" "0,1"
|
|
rgroup.long (d:0x00001400+0x30)++0x03
|
|
line.long 0x00 "_MR0,CLA Floating-Point Result Register 0"
|
|
rgroup.long (d:0x00001400+0x34)++0x03
|
|
line.long 0x00 "_MR1,CLA Floating-Point Result Register 1"
|
|
rgroup.long (d:0x00001400+0x38)++0x03
|
|
line.long 0x00 "_MR2,CLA Floating-Point Result Register 2"
|
|
rgroup.long (d:0x00001400+0x3C)++0x03
|
|
line.long 0x00 "_MR3,CLA Floating-Point Result Register 3"
|
|
group.word (d:0x00001400+0x42)++0x01
|
|
line.word 0x00 "_MPSACTL,CLA PSA Control Register"
|
|
bitfld.word 0x00 6.--7. " MPSA2CFG ,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x00 5. " MPSA2CLEAR ,PSA2 Clear" "0,1"
|
|
bitfld.word 0x00 4. " MPSA1CLEAR ,PSA1 clear" "0,1"
|
|
bitfld.word 0x00 3. " MDWDBCYC ,DWDB logging into PSA2 is on every cycle." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " MDWDBSTART ,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x00 1. " MPABCYC ,PAB logging into PSA1 is on every cycle or when PAB changes." "0,1"
|
|
bitfld.word 0x00 0. " MPABSTART ,Start logging PAB onto PSA1" "0,1"
|
|
group.long (d:0x00001400+0x44)++0x03
|
|
line.long 0x00 "_MPSA1,CLA PSA1 Register"
|
|
group.long (d:0x00001400+0x46)++0x03
|
|
line.long 0x00 "_MPSA2,CLA PSA2 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CPU1_CLA1"
|
|
width 18.
|
|
group.word (d:0x00001400+0x00)++0x01
|
|
line.word 0x00 "MVECT1,Task 1 vector"
|
|
group.word (d:0x00001400+0x01)++0x01
|
|
line.word 0x00 "MVECT2,Task 2 vector"
|
|
group.word (d:0x00001400+0x02)++0x01
|
|
line.word 0x00 "MVECT3,Task 3 vector"
|
|
group.word (d:0x00001400+0x03)++0x01
|
|
line.word 0x00 "MVECT4,Task 4 vector"
|
|
group.word (d:0x00001400+0x04)++0x01
|
|
line.word 0x00 "MVECT5,Task 5 vector"
|
|
group.word (d:0x00001400+0x05)++0x01
|
|
line.word 0x00 "MVECT6,Task 6 vector"
|
|
group.word (d:0x00001400+0x06)++0x01
|
|
line.word 0x00 "MVECT7,Task 7 vector"
|
|
group.word (d:0x00001400+0x07)++0x01
|
|
line.word 0x00 "MVECT8,Task 8 vector"
|
|
group.word (d:0x00001400+0x10)++0x01
|
|
line.word 0x00 "MCTL,CLA control"
|
|
bitfld.word 0x00 0. " HARDRESET ,Hard reset" "0,1"
|
|
bitfld.word 0x00 1. " SOFTRESET ,Soft reset" "0,1"
|
|
bitfld.word 0x00 2. " IACKE ,IACK enable" "0,1"
|
|
group.word (d:0x00001400+0x11)++0x01
|
|
line.word 0x00 "MMEMCFG,CLA memory configuration"
|
|
bitfld.word 0x00 0. " PROGE ,Program memory enable" "0,1"
|
|
bitfld.word 0x00 4.--6. " RAMnE ,Data RAM Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " RAMnCPUE ,Data RAM CPU Access Enable" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00001400+0x14)++0x03
|
|
line.long 0x00 "MPISRCSEL1,CLA interrupt source select 1"
|
|
bitfld.long 0x00 0.--3. " PERINT1SEL ,Task 1 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PERINT2SEL ,Task 2 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PERINT3SEL ,Task 3 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " PERINT4SEL ,Task 4 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PERINT5SEL ,Task 5 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " PERINT6SEL ,Task 6 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PERINT7SEL ,Task 7 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 28.--31. " PERINT8SEL ,Task 8 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00001400+0x16)++0x03
|
|
line.long 0x00 "MPISRCSEL2,CLA interrupt source select 2"
|
|
bitfld.long 0x00 0.--3. " PERINT9SEL ,Task 9 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PERINT10SEL ,Task 10 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PERINT11SEL ,Task 11 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " PERINT12SEL ,Task 12 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PERINT13SEL ,Task 13 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " PERINT14SEL ,Task 14 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PERINT15SEL ,Task 15 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 28.--31. " PERINT16SEL ,Task 16 Peripheral Interrupt Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00001400+0x1B)++0x01
|
|
line.word 0x00 "MVECTBGRNDACTIVE,Active register for MVECTBGRND"
|
|
group.word (d:0x00001400+0x1C)++0x01
|
|
line.word 0x00 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x00 0. " TASK1 ,Configure Software Interrupt or End of Task 1 interrupt" "0,1"
|
|
bitfld.word 0x00 1. " TASK2 ,Configure Software Interrupt or End of Task 2 interrupt" "0,1"
|
|
bitfld.word 0x00 2. " TASK3 ,Configure Software Interrupt or End of Task 3 interrupt" "0,1"
|
|
bitfld.word 0x00 3. " TASK4 ,Configure Software Interrupt or End of Task 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TASK5 ,Configure Software Interrupt or End of Task 5 interrupt" "0,1"
|
|
bitfld.word 0x00 5. " TASK6 ,Configure Software Interrupt or End of Task 6 interrupt" "0,1"
|
|
bitfld.word 0x00 6. " TASK7 ,Configure Software Interrupt or End of Task 7 interrupt" "0,1"
|
|
bitfld.word 0x00 7. " TASK8 ,Configure Software Interrupt or End of Task 8 interrupt" "0,1"
|
|
rgroup.word (d:0x00001400+0x1D)++0x01
|
|
line.word 0x00 "MSTSBGRND,Status register for the background task"
|
|
bitfld.word 0x00 0. " RUN ,Background task run status bit" "0,1"
|
|
bitfld.word 0x00 1. " BGINTM ,Indicates whether background task can be interrupted" "0,1"
|
|
bitfld.word 0x00 2. " BGOVF ,Background task hardware trigger overflow" "0,1"
|
|
group.word (d:0x00001400+0x1E)++0x01
|
|
line.word 0x00 "MCTLBGRND,Control register for the background task"
|
|
bitfld.word 0x00 0. " BGSTART ,Background task start bit" "0,1"
|
|
bitfld.word 0x00 1. " TRIGEN ,Background task hardware trigger enable" "0,1"
|
|
bitfld.word 0x00 15. " BGEN ,Enable Background task" "0,1"
|
|
group.word (d:0x00001400+0x1F)++0x01
|
|
line.word 0x00 "MVECTBGRND,Vector for the background task"
|
|
rgroup.word (d:0x00001400+0x20)++0x01
|
|
line.word 0x00 "MIFR,CLA interrupt flag"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 flag bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 flag bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 flag bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 flag bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 flag bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 flag bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 flag bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 flag bit" "0,1"
|
|
rgroup.word (d:0x00001400+0x21)++0x01
|
|
line.word 0x00 "MIOVF,CLA interrupt overflow flag"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 overflow bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 overflow bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 overflow bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 overflow bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 overflow bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 overflow bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 overflow bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 overflow bit" "0,1"
|
|
group.word (d:0x00001400+0x22)++0x01
|
|
line.word 0x00 "MIFRC,CLA interrupt force"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 force bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 force bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 force bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 force bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 force bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 force bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 force bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 force bit" "0,1"
|
|
group.word (d:0x00001400+0x23)++0x01
|
|
line.word 0x00 "MICLR,CLA interrupt flag clear"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 clear bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 clear bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 clear bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 clear bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 clear bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 clear bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 clear bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 clear bit" "0,1"
|
|
group.word (d:0x00001400+0x24)++0x01
|
|
line.word 0x00 "MICLROVF,CLA interrupt overflow flag clear"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 overflow clear bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 overflow clear bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 overflow clear bit" "0,1"
|
|
group.word (d:0x00001400+0x25)++0x01
|
|
line.word 0x00 "MIER,CLA interrupt enable"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 enable bit" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 enable bit" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 enable bit" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 enable bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 enable bit" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 enable bit" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 enable bit" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 enable bit" "0,1"
|
|
group.word (d:0x00001400+0x26)++0x01
|
|
line.word 0x00 "MIRUN,CLA interrupt run status"
|
|
bitfld.word 0x00 0. " INT1 ,Interrupt 1 run status" "0,1"
|
|
bitfld.word 0x00 1. " INT2 ,Interrupt 2 run status" "0,1"
|
|
bitfld.word 0x00 2. " INT3 ,Interrupt 3 run status" "0,1"
|
|
bitfld.word 0x00 3. " INT4 ,Interrupt 4 run status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " INT5 ,Interrupt 5 run status" "0,1"
|
|
bitfld.word 0x00 5. " INT6 ,Interrupt 6 run status" "0,1"
|
|
bitfld.word 0x00 6. " INT7 ,Interrupt 7 run status" "0,1"
|
|
bitfld.word 0x00 7. " INT8 ,Interrupt 8 run status" "0,1"
|
|
group.word (d:0x00001400+0x28)++0x01
|
|
line.word 0x00 "MPC,CLA program counter"
|
|
group.word (d:0x00001400+0x2A)++0x01
|
|
line.word 0x00 "MAR0,CLA auxiliary register 0"
|
|
group.word (d:0x00001400+0x2B)++0x01
|
|
line.word 0x00 "MAR1,CLA auxiliary register 1"
|
|
rgroup.long (d:0x00001400+0x2E)++0x03
|
|
line.long 0x00 "MSTF,CLA floating-point status register"
|
|
bitfld.long 0x00 0. " LVF ,Overflow flag" "0,1"
|
|
bitfld.long 0x00 1. " LUF ,Underflow flag" "0,1"
|
|
bitfld.long 0x00 2. " NF ,Negative flag" "0,1"
|
|
bitfld.long 0x00 3. " ZF ,Zero flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " TF ,Test flag" "0,1"
|
|
bitfld.long 0x00 9. " RND32 ,Rounding mode" "0,1"
|
|
bitfld.long 0x00 11. " MEALLOW ,Protected write" "0,1"
|
|
hexmask.long 0x00 12.--27. 1. "RPC,Return PC"
|
|
group.long (d:0x00001400+0x30)++0x03
|
|
line.long 0x00 "MR0,CLA result register 0"
|
|
group.long (d:0x00001400+0x34)++0x03
|
|
line.long 0x00 "MR1,CLA result register 1"
|
|
group.long (d:0x00001400+0x38)++0x03
|
|
line.long 0x00 "MR2,CLA result register 2"
|
|
group.long (d:0x00001400+0x3C)++0x03
|
|
line.long 0x00 "MR3,CLA result register 3"
|
|
group.word (d:0x00001400+0x40)++0x01
|
|
line.word 0x00 "MDEBUGCTL,CLA Debug Control Register"
|
|
bitfld.word 0x00 0. " ONESHOT ,One Shot Mode bit" "0,1"
|
|
bitfld.word 0x00 1. " SSE ,Single Step Enable bit" "0,1"
|
|
rbitfld.word 0x00 2. " DEBUGSTOP ,Debug stop bit" "0,1"
|
|
group.word (d:0x00001400+0x41)++0x01
|
|
line.word 0x00 "MDEBUGSS,CLA Debug Step Register"
|
|
bitfld.word 0x00 0. " SS ,Single Step Command bit" "0,1"
|
|
bitfld.word 0x00 1. " RUN ,Run bit" "0,1"
|
|
group.word (d:0x00001400+0x42)++0x01
|
|
line.word 0x00 "MPSACTL,PSA Control Register"
|
|
bitfld.word 0x00 0. " MPABSTART ,Start logging PAB onto PSA1" "0,1"
|
|
bitfld.word 0x00 1. " MPABCYC ,PAB logging into PSA1 is on every cycle or when PAB changes" "0,1"
|
|
bitfld.word 0x00 2. " MDWDBSTART ,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x00 3. " MDWDBCYC ,DWDB logging into PSA2 is on every cycle" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " MPSA1CLEAR ,PSA1 Clear" "0,1"
|
|
bitfld.word 0x00 5. " MPSA2CLEAR ,PSA2 Clear" "0,1"
|
|
bitfld.word 0x00 6.--7. " MPSA2CFG ,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
group.long (d:0x00001400+0x44)++0x03
|
|
line.long 0x00 "MPSA1,CLA PSA1 Register"
|
|
group.long (d:0x00001400+0x46)++0x03
|
|
line.long 0x00 "MPSA1,CLA PSA2 Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ClaOnlyRegs"
|
|
width 19.
|
|
rgroup.word (d:0x00000C00+0x80)++0x01
|
|
line.word 0x00 "_MVECTBGRNDACTIVE,Active register for MVECTBGRND."
|
|
group.word (d:0x00000C00+0xC0)++0x01
|
|
line.word 0x00 "_MPSACTL,CLA PSA Control Register"
|
|
bitfld.word 0x00 6.--7. " MPSA2CFG ,PSA2 Polynomial Configuration" "0,1,2,3"
|
|
bitfld.word 0x00 5. " MPSA2CLEAR ,PSA2 Clear" "0,1"
|
|
bitfld.word 0x00 4. " MPSA1CLEAR ,PSA1 clear" "0,1"
|
|
bitfld.word 0x00 3. " MDWDBCYC ,DWDB logging into PSA2 is on every cycle." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " MDWDBSTART ,Start logging DWDB onto PSA2" "0,1"
|
|
bitfld.word 0x00 1. " MPABCYC ,PAB logging into PSA1 is on every cycle or when PAB changes." "0,1"
|
|
bitfld.word 0x00 0. " MPABSTART ,Start logging PAB onto PSA1" "0,1"
|
|
group.long (d:0x00000C00+0xC2)++0x03
|
|
line.long 0x00 "_MPSA1,CLA PSA1 Register"
|
|
group.long (d:0x00000C00+0xC4)++0x03
|
|
line.long 0x00 "_MPSA2,CLA PSA2 Register"
|
|
group.word (d:0x00000C00+0xE0)++0x01
|
|
line.word 0x00 "SOFTINTEN,CLA Software Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " TASK8 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 6. " TASK7 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 5. " TASK6 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 4. " TASK5 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " TASK4 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 2. " TASK3 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 1. " TASK2 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
bitfld.word 0x00 0. " TASK1 ,Configure Software Interrupt or End of Task interrupt." "0,1"
|
|
group.word (d:0x00000C00+0xE2)++0x01
|
|
line.word 0x00 "SOFTINTFRC,CLA Software Interrupt Force Register"
|
|
bitfld.word 0x00 7. " TASK8 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 6. " TASK7 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 5. " TASK6 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 4. " TASK5 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " TASK4 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 2. " TASK3 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 1. " TASK2 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
bitfld.word 0x00 0. " TASK1 ,Force CLA software interrupt for the corresponding task." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif !cpuis("F28384D*")&&!cpuis("F28384S*")
|
|
tree "Configurable Logic Block (CLB)"
|
|
tree "Clb1LogicCfgRegs"
|
|
width 25.
|
|
group.long (d:0x00003000+0x02)++0x03
|
|
line.long 0x00 "CLB_COUNT_RESET,Counter Block RESET"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Count Reset Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Count Reset Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Count Reset Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x04)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 1 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 1 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 1 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x06)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 0 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 0 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 0 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x08)++0x03
|
|
line.long 0x00 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter event select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter event select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter event select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0A)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0C)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN0 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN0 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN0 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0E)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN1 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN1 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN1 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x10)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x12)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x14)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x16)++0x03
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line.long 0x00 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x18)++0x03
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line.long 0x00 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x1C)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
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hexmask.long 0x00 16.--31. 1. "FN1,FSM LUT output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,FSM LUT output function for unit 0"
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group.long (d:0x00003000+0x1E)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,FSM LUT output function for unit 2"
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group.long (d:0x00003000+0x20)++0x03
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line.long 0x00 "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
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hexmask.long 0x00 16.--31. 1. "FN1,LUT4 output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,LUT4 output function for unit 0"
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group.long (d:0x00003000+0x22)++0x03
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line.long 0x00 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,LUT4 output function for unit 2"
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group.long (d:0x00003000+0x24)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x26)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x28)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x2A)++0x03
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line.long 0x00 "CLB_MISC_CONTROL,Static controls for Ctr,FSM"
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bitfld.long 0x00 26. " COUNT2_LFSR_EN ,Enable LFSR mode for Counter 2" "0,1"
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bitfld.long 0x00 25. " COUNT1_LFSR_EN ,Enable LFSR mode for Counter 1" "0,1"
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bitfld.long 0x00 24. " COUNT0_LFSR_EN ,Enable LFSR mode for Counter 0" "0,1"
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bitfld.long 0x00 23. " COUNT2_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 2" "0,1"
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newline
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bitfld.long 0x00 22. " COUNT1_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 21. " COUNT0_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 20. " COUNT2_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 19. " COUNT1_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 18. " COUNT0_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 17. " FSM_EXTRA_SEL1_2 ,FSM extra_sel1 for 2" "0,1"
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bitfld.long 0x00 16. " FSM_EXTRA_SEL0_2 ,FSM extra_sel0 for 2" "0,1"
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bitfld.long 0x00 15. " FSM_EXTRA_SEL1_1 ,FSM extra_sel1 for 1" "0,1"
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bitfld.long 0x00 14. " FSM_EXTRA_SEL0_1 ,FSM extra_sel0 for 1" "0,1"
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bitfld.long 0x00 13. " FSM_EXTRA_SEL1_0 ,FSM extra_sel1 for 0" "0,1"
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bitfld.long 0x00 12. " FSM_EXTRA_SEL0_0 ,FSM extra_sel0 for 0" "0,1"
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bitfld.long 0x00 11. " COUNT_SERIALIZER_2 ,Serializer enable 2" "0,1"
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bitfld.long 0x00 10. " COUNT_SERIALIZER_1 ,Serializer enable 1" "0,1"
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bitfld.long 0x00 9. " COUNT_SERIALIZER_0 ,Serializer enable 0" "0,1"
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bitfld.long 0x00 8. " COUNT_EVENT_CTRL_2 ,Event control for counter 2" "0,1"
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bitfld.long 0x00 7. " COUNT_DIR_2 ,Direction for counter 2" "0,1"
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bitfld.long 0x00 6. " COUNT_ADD_SHIFT_2 ,Add/Shift for counter 2" "0,1"
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bitfld.long 0x00 5. " COUNT_EVENT_CTRL_1 ,Event control for counter 1" "0,1"
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bitfld.long 0x00 4. " COUNT_DIR_1 ,Direction for counter 1" "0,1"
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bitfld.long 0x00 3. " COUNT_ADD_SHIFT_1 ,Add/Shift for counter 1" "0,1"
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bitfld.long 0x00 2. " COUNT_EVENT_CTRL_0 ,Event control for counter 0" "0,1"
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bitfld.long 0x00 1. " COUNT_DIR_0 ,Direction for counter 0" "0,1"
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bitfld.long 0x00 0. " COUNT_ADD_SHIFT_0 ,Add/Shift for counter 0" "0,1"
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group.long (d:0x00003000+0x2C)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_0,Inp Sel, LUT fns for Out0"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x2E)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_1,Inp Sel, LUT fns for Out1"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x30)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_2,Inp Sel, LUT fns for Out2"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x32)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_3,Inp Sel, LUT fns for Out3"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x34)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_4,Inp Sel, LUT fns for Out4"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x36)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_5,Inp Sel, LUT fns for Out5"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x38)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_6,Inp Sel, LUT fns for Out6"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3A)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_7,Inp Sel, LUT fns for Out7"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3C)++0x03
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line.long 0x00 "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
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bitfld.long 0x00 23. " ALT_EVENT3_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 22. " ALT_EVENT2_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 21. " ALT_EVENT1_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 20. " ALT_EVENT0_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 15.--19. " EVENT3_SEL ,Event Select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " EVENT2_SEL ,Event Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " EVENT1_SEL ,Event Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " EVENT0_SEL ,Event Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3E)++0x03
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line.long 0x00 "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
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bitfld.long 0x00 26.--30. " COUNT2_MATCH2 ,Match2 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 21.--25. " COUNT1_MATCH2 ,Match2 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " COUNT0_MATCH2 ,Match2 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " COUNT2_MATCH1 ,Match1 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " COUNT1_MATCH1 ,Match1 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " COUNT0_MATCH1 ,Match1 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x40)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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newline
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
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group.long (d:0x00003000+0x42)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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newline
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x44)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x46)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x48)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4A)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4C)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4E)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.word (d:0x00003000+0x50)++0x01
|
|
line.word 0x00 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x00 1. " BLKEN ,Block Register write" "0,1"
|
|
bitfld.word 0x00 0. " SPIEN ,Enable CLB SPI Buffer feature" "0,1"
|
|
group.word (d:0x00003000+0x51)++0x01
|
|
line.word 0x00 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
bitfld.word 0x00 8.--12. " SHIFT ,Shift value select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " STRB ,Select value for strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb1LogicCtrlRegs"
|
|
width 24.
|
|
group.word (d:0x00003100+0x00)++0x01
|
|
line.word 0x00 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x00 4. " PIPELINE_EN ,Enable input pipelining" "0,1"
|
|
bitfld.word 0x00 3. " NMI_EN ,NMI output enable" "0,1"
|
|
bitfld.word 0x00 2. " STOP ,Debug stop control" "0,1"
|
|
bitfld.word 0x00 1. " GLOBAL_EN ,Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " LOAD_EN ,Load Enable" "0,1"
|
|
group.long (d:0x00003100+0x02)++0x03
|
|
line.long 0x00 "CLB_LOAD_ADDR,Indirect address"
|
|
bitfld.long 0x00 0.--5. " ADDR ,Indirect Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x04)++0x03
|
|
line.long 0x00 "CLB_LOAD_DATA,Data for indirect loads"
|
|
group.long (d:0x00003100+0x06)++0x03
|
|
line.long 0x00 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x00 31. " PIPE7 ,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x00 30. " PIPE6 ,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x00 29. " PIPE5 ,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x00 28. " PIPE4 ,Enable pipeline 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " PIPE3 ,Enable pipeline 3" "0,1"
|
|
bitfld.long 0x00 26. " PIPE2 ,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x00 25. " PIPE1 ,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x00 24. " PIPE0 ,Enable pipeline 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SYNC7 ,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x00 22. " SYNC6 ,Synchronizer control 6" "0,1"
|
|
bitfld.long 0x00 21. " SYNC5 ,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x00 20. " SYNC4 ,Synchronizer control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SYNC3 ,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x00 18. " SYNC2 ,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x00 17. " SYNC1 ,Synchronizer control 1" "0,1"
|
|
bitfld.long 0x00 16. " SYNC0 ,Synchronizer control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " FIN7 ,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FIN6 ,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " FIN5 ,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " FIN4 ,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " FIN3 ,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " FIN2 ,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " FIN1 ,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FIN0 ,Input filter control 0" "0,1,2,3"
|
|
group.long (d:0x00003100+0x08)++0x03
|
|
line.long 0x00 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x00 31. " SW_GATING_CTRL_7 ,Software gating control 7" "0,1"
|
|
bitfld.long 0x00 30. " SW_GATING_CTRL_6 ,Software gating control 6" "0,1"
|
|
bitfld.long 0x00 29. " SW_GATING_CTRL_5 ,Software gating control 5" "0,1"
|
|
bitfld.long 0x00 28. " SW_GATING_CTRL_4 ,Software gating control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SW_GATING_CTRL_3 ,Software gating control 3" "0,1"
|
|
bitfld.long 0x00 26. " SW_GATING_CTRL_2 ,Software gating control 2" "0,1"
|
|
bitfld.long 0x00 25. " SW_GATING_CTRL_1 ,Software gating control 1" "0,1"
|
|
bitfld.long 0x00 24. " SW_GATING_CTRL_0 ,Software gating control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SW_RLS_CTRL_7 ,Software release control 7" "0,1"
|
|
bitfld.long 0x00 22. " SW_RLS_CTRL_6 ,Software release control 6" "0,1"
|
|
bitfld.long 0x00 21. " SW_RLS_CTRL_5 ,Software release control 5" "0,1"
|
|
bitfld.long 0x00 20. " SW_RLS_CTRL_4 ,Software release control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SW_RLS_CTRL_3 ,Software release control 3" "0,1"
|
|
bitfld.long 0x00 18. " SW_RLS_CTRL_2 ,Software release control 2" "0,1"
|
|
bitfld.long 0x00 17. " SW_RLS_CTRL_1 ,Software release control 1" "0,1"
|
|
bitfld.long 0x00 16. " SW_RLS_CTRL_0 ,Software release control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL_GP_IN_7 ,Select GP register 7" "0,1"
|
|
bitfld.long 0x00 6. " SEL_GP_IN_6 ,Select GP register 6" "0,1"
|
|
bitfld.long 0x00 5. " SEL_GP_IN_5 ,Select GP register 5" "0,1"
|
|
bitfld.long 0x00 4. " SEL_GP_IN_4 ,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SEL_GP_IN_3 ,Select GP register 3" "0,1"
|
|
bitfld.long 0x00 2. " SEL_GP_IN_2 ,Select GP register 2" "0,1"
|
|
bitfld.long 0x00 1. " SEL_GP_IN_1 ,Select GP register 1" "0,1"
|
|
bitfld.long 0x00 0. " SEL_GP_IN_0 ,Select GP register 0" "0,1"
|
|
group.long (d:0x00003100+0x0A)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_3 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_2 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_1 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_0 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_3 ,Local Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_2 ,Local Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_1 ,Local Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_0 ,Local Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0C)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_7 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_6 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_5 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_4 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_7 ,Local Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_6 ,Local Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_5 ,Local Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_4 ,Local Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0E)++0x03
|
|
line.long 0x00 "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long 0x00 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long 0x00 0.--7. 1. "PULL,Data pointer for pull"
|
|
group.long (d:0x00003100+0x10)++0x03
|
|
line.long 0x00 "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long 0x00 0.--7. 1. "REG,General Purpose bit register"
|
|
group.long (d:0x00003100+0x12)++0x03
|
|
line.long 0x00 "CLB_OUT_EN,CELL output enable register"
|
|
group.long (d:0x00003100+0x14)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_3 ,Global Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_2 ,Global Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_1 ,Global Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_0 ,Global Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x16)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_7 ,Global Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_6 ,Global Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_5 ,Global Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_4 ,Global Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x18)++0x03
|
|
line.long 0x00 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long 0x00 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
bitfld.long 0x00 2.--5. " TAP ,TAP Select value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " STRB ,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x00 0. " CLKEN ,Enable the prescale clock generator" "0,1"
|
|
group.word (d:0x00003100+0x20)++0x01
|
|
line.word 0x00 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
bitfld.word 0x00 0.--5. " TAG ,Interrupt tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x22)++0x03
|
|
line.long 0x00 "CLB_LOCK,Lock control register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x00 0. " LOCK ,LOCK enable" "0,1"
|
|
group.word (d:0x00003100+0x24)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
bitfld.word 0x00 0.--4. " READ_PTR ,HLC instruction read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00003100+0x26)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x00 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long (d:0x00003100+0x2E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long 0x00 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long 0x00 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long (d:0x00003100+0x30)++0x03
|
|
line.long 0x00 "CLB_DBG_R0,R0 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x32)++0x03
|
|
line.long 0x00 "CLB_DBG_R1,R1 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x34)++0x03
|
|
line.long 0x00 "CLB_DBG_R2,R2 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x36)++0x03
|
|
line.long 0x00 "CLB_DBG_R3,R3 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x38)++0x03
|
|
line.long 0x00 "CLB_DBG_C0,Count of Unit 0"
|
|
rgroup.long (d:0x00003100+0x3A)++0x03
|
|
line.long 0x00 "CLB_DBG_C1,Count of Unit 1"
|
|
rgroup.long (d:0x00003100+0x3C)++0x03
|
|
line.long 0x00 "CLB_DBG_C2,Count of Unit 2"
|
|
rgroup.long (d:0x00003100+0x3E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0x00 31. " OUT7 ,CELL Output 7" "0,1"
|
|
bitfld.long 0x00 30. " OUT6 ,CELL Output 6" "0,1"
|
|
bitfld.long 0x00 29. " OUT5 ,CELL Output 5" "0,1"
|
|
bitfld.long 0x00 28. " OUT4 ,CELL Output 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " OUT3 ,CELL Output 3" "0,1"
|
|
bitfld.long 0x00 26. " OUT2 ,CELL Output 2" "0,1"
|
|
bitfld.long 0x00 25. " OUT1 ,CELL Output 1" "0,1"
|
|
bitfld.long 0x00 24. " OUT0 ,CELL Output 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " LUT42_OUT ,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 22. " FSM2_LUTOUT ,FSM_LUT_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 21. " FSM2_S1 ,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 20. " FSM2_S0 ,FSM_S0 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " COUNT2_MATCH1 ,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 18. " COUNT2_ZERO ,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0x00 17. " COUNT2_MATCH2 ,COUNT_MATCH2 UNIT 2" "0,1"
|
|
bitfld.long 0x00 15. " LUT41_OUT ,LUT4_OUT UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " FSM1_LUTOUT ,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0x00 13. " FSM1_S1 ,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0x00 12. " FSM1_S0 ,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0x00 11. " COUNT1_MATCH1 ,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " COUNT1_ZERO ,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0x00 9. " COUNT1_MATCH2 ,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0x00 7. " LUT40_OUT ,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0x00 6. " FSM0_LUTOUT ,FSM_LUT_OUT UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " FSM0_S1 ,FSM_S1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 4. " FSM0_S0 ,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0x00 3. " COUNT0_MATCH1 ,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 2. " COUNT0_ZERO ,COUNT_ZERO UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " COUNT0_MATCH2 ,COUNT_MATCH2 UNIT 0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb1DataExchRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00003180+0x00)++0x03
|
|
line.long 0x00 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
group.long (d:0x00003180+0x40)++0x03
|
|
line.long 0x00 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb2LogicCfgRegs"
|
|
width 25.
|
|
group.long (d:0x00003000+0x02)++0x03
|
|
line.long 0x00 "CLB_COUNT_RESET,Counter Block RESET"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Count Reset Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Count Reset Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Count Reset Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x04)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 1 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 1 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 1 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x06)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 0 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 0 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 0 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x08)++0x03
|
|
line.long 0x00 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter event select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter event select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter event select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0A)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0C)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN0 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN0 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN0 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0E)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN1 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN1 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN1 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x10)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x12)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x14)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x16)++0x03
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line.long 0x00 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x18)++0x03
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line.long 0x00 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x1C)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
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hexmask.long 0x00 16.--31. 1. "FN1,FSM LUT output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,FSM LUT output function for unit 0"
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group.long (d:0x00003000+0x1E)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,FSM LUT output function for unit 2"
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group.long (d:0x00003000+0x20)++0x03
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line.long 0x00 "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
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hexmask.long 0x00 16.--31. 1. "FN1,LUT4 output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,LUT4 output function for unit 0"
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group.long (d:0x00003000+0x22)++0x03
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line.long 0x00 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,LUT4 output function for unit 2"
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group.long (d:0x00003000+0x24)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x26)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x28)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x2A)++0x03
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line.long 0x00 "CLB_MISC_CONTROL,Static controls for Ctr,FSM"
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bitfld.long 0x00 26. " COUNT2_LFSR_EN ,Enable LFSR mode for Counter 2" "0,1"
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bitfld.long 0x00 25. " COUNT1_LFSR_EN ,Enable LFSR mode for Counter 1" "0,1"
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bitfld.long 0x00 24. " COUNT0_LFSR_EN ,Enable LFSR mode for Counter 0" "0,1"
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bitfld.long 0x00 23. " COUNT2_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 22. " COUNT1_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 21. " COUNT0_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 20. " COUNT2_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 19. " COUNT1_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 18. " COUNT0_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 17. " FSM_EXTRA_SEL1_2 ,FSM extra_sel1 for 2" "0,1"
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bitfld.long 0x00 16. " FSM_EXTRA_SEL0_2 ,FSM extra_sel0 for 2" "0,1"
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bitfld.long 0x00 15. " FSM_EXTRA_SEL1_1 ,FSM extra_sel1 for 1" "0,1"
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bitfld.long 0x00 14. " FSM_EXTRA_SEL0_1 ,FSM extra_sel0 for 1" "0,1"
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bitfld.long 0x00 13. " FSM_EXTRA_SEL1_0 ,FSM extra_sel1 for 0" "0,1"
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bitfld.long 0x00 12. " FSM_EXTRA_SEL0_0 ,FSM extra_sel0 for 0" "0,1"
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bitfld.long 0x00 11. " COUNT_SERIALIZER_2 ,Serializer enable 2" "0,1"
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bitfld.long 0x00 10. " COUNT_SERIALIZER_1 ,Serializer enable 1" "0,1"
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bitfld.long 0x00 9. " COUNT_SERIALIZER_0 ,Serializer enable 0" "0,1"
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bitfld.long 0x00 8. " COUNT_EVENT_CTRL_2 ,Event control for counter 2" "0,1"
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bitfld.long 0x00 7. " COUNT_DIR_2 ,Direction for counter 2" "0,1"
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bitfld.long 0x00 6. " COUNT_ADD_SHIFT_2 ,Add/Shift for counter 2" "0,1"
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bitfld.long 0x00 5. " COUNT_EVENT_CTRL_1 ,Event control for counter 1" "0,1"
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bitfld.long 0x00 4. " COUNT_DIR_1 ,Direction for counter 1" "0,1"
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bitfld.long 0x00 3. " COUNT_ADD_SHIFT_1 ,Add/Shift for counter 1" "0,1"
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bitfld.long 0x00 2. " COUNT_EVENT_CTRL_0 ,Event control for counter 0" "0,1"
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bitfld.long 0x00 1. " COUNT_DIR_0 ,Direction for counter 0" "0,1"
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bitfld.long 0x00 0. " COUNT_ADD_SHIFT_0 ,Add/Shift for counter 0" "0,1"
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group.long (d:0x00003000+0x2C)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_0,Inp Sel, LUT fns for Out0"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x2E)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_1,Inp Sel, LUT fns for Out1"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x30)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_2,Inp Sel, LUT fns for Out2"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x32)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_3,Inp Sel, LUT fns for Out3"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x34)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_4,Inp Sel, LUT fns for Out4"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x36)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_5,Inp Sel, LUT fns for Out5"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x38)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_6,Inp Sel, LUT fns for Out6"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3A)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_7,Inp Sel, LUT fns for Out7"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3C)++0x03
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line.long 0x00 "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
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bitfld.long 0x00 23. " ALT_EVENT3_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 22. " ALT_EVENT2_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 21. " ALT_EVENT1_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 20. " ALT_EVENT0_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 15.--19. " EVENT3_SEL ,Event Select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " EVENT2_SEL ,Event Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " EVENT1_SEL ,Event Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " EVENT0_SEL ,Event Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3E)++0x03
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line.long 0x00 "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
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bitfld.long 0x00 26.--30. " COUNT2_MATCH2 ,Match2 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 21.--25. " COUNT1_MATCH2 ,Match2 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " COUNT0_MATCH2 ,Match2 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " COUNT2_MATCH1 ,Match1 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " COUNT1_MATCH1 ,Match1 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " COUNT0_MATCH1 ,Match1 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x40)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
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group.long (d:0x00003000+0x42)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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|
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x44)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x46)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x48)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4A)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4C)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4E)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.word (d:0x00003000+0x50)++0x01
|
|
line.word 0x00 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x00 1. " BLKEN ,Block Register write" "0,1"
|
|
bitfld.word 0x00 0. " SPIEN ,Enable CLB SPI Buffer feature" "0,1"
|
|
group.word (d:0x00003000+0x51)++0x01
|
|
line.word 0x00 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
bitfld.word 0x00 8.--12. " SHIFT ,Shift value select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " STRB ,Select value for strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb2LogicCtrlRegs"
|
|
width 24.
|
|
group.word (d:0x00003100+0x00)++0x01
|
|
line.word 0x00 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x00 4. " PIPELINE_EN ,Enable input pipelining" "0,1"
|
|
bitfld.word 0x00 3. " NMI_EN ,NMI output enable" "0,1"
|
|
bitfld.word 0x00 2. " STOP ,Debug stop control" "0,1"
|
|
bitfld.word 0x00 1. " GLOBAL_EN ,Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " LOAD_EN ,Load Enable" "0,1"
|
|
group.long (d:0x00003100+0x02)++0x03
|
|
line.long 0x00 "CLB_LOAD_ADDR,Indirect address"
|
|
bitfld.long 0x00 0.--5. " ADDR ,Indirect Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x04)++0x03
|
|
line.long 0x00 "CLB_LOAD_DATA,Data for indirect loads"
|
|
group.long (d:0x00003100+0x06)++0x03
|
|
line.long 0x00 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x00 31. " PIPE7 ,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x00 30. " PIPE6 ,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x00 29. " PIPE5 ,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x00 28. " PIPE4 ,Enable pipeline 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " PIPE3 ,Enable pipeline 3" "0,1"
|
|
bitfld.long 0x00 26. " PIPE2 ,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x00 25. " PIPE1 ,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x00 24. " PIPE0 ,Enable pipeline 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SYNC7 ,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x00 22. " SYNC6 ,Synchronizer control 6" "0,1"
|
|
bitfld.long 0x00 21. " SYNC5 ,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x00 20. " SYNC4 ,Synchronizer control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SYNC3 ,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x00 18. " SYNC2 ,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x00 17. " SYNC1 ,Synchronizer control 1" "0,1"
|
|
bitfld.long 0x00 16. " SYNC0 ,Synchronizer control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " FIN7 ,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FIN6 ,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " FIN5 ,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " FIN4 ,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " FIN3 ,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " FIN2 ,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " FIN1 ,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FIN0 ,Input filter control 0" "0,1,2,3"
|
|
group.long (d:0x00003100+0x08)++0x03
|
|
line.long 0x00 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x00 31. " SW_GATING_CTRL_7 ,Software gating control 7" "0,1"
|
|
bitfld.long 0x00 30. " SW_GATING_CTRL_6 ,Software gating control 6" "0,1"
|
|
bitfld.long 0x00 29. " SW_GATING_CTRL_5 ,Software gating control 5" "0,1"
|
|
bitfld.long 0x00 28. " SW_GATING_CTRL_4 ,Software gating control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SW_GATING_CTRL_3 ,Software gating control 3" "0,1"
|
|
bitfld.long 0x00 26. " SW_GATING_CTRL_2 ,Software gating control 2" "0,1"
|
|
bitfld.long 0x00 25. " SW_GATING_CTRL_1 ,Software gating control 1" "0,1"
|
|
bitfld.long 0x00 24. " SW_GATING_CTRL_0 ,Software gating control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SW_RLS_CTRL_7 ,Software release control 7" "0,1"
|
|
bitfld.long 0x00 22. " SW_RLS_CTRL_6 ,Software release control 6" "0,1"
|
|
bitfld.long 0x00 21. " SW_RLS_CTRL_5 ,Software release control 5" "0,1"
|
|
bitfld.long 0x00 20. " SW_RLS_CTRL_4 ,Software release control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SW_RLS_CTRL_3 ,Software release control 3" "0,1"
|
|
bitfld.long 0x00 18. " SW_RLS_CTRL_2 ,Software release control 2" "0,1"
|
|
bitfld.long 0x00 17. " SW_RLS_CTRL_1 ,Software release control 1" "0,1"
|
|
bitfld.long 0x00 16. " SW_RLS_CTRL_0 ,Software release control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL_GP_IN_7 ,Select GP register 7" "0,1"
|
|
bitfld.long 0x00 6. " SEL_GP_IN_6 ,Select GP register 6" "0,1"
|
|
bitfld.long 0x00 5. " SEL_GP_IN_5 ,Select GP register 5" "0,1"
|
|
bitfld.long 0x00 4. " SEL_GP_IN_4 ,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SEL_GP_IN_3 ,Select GP register 3" "0,1"
|
|
bitfld.long 0x00 2. " SEL_GP_IN_2 ,Select GP register 2" "0,1"
|
|
bitfld.long 0x00 1. " SEL_GP_IN_1 ,Select GP register 1" "0,1"
|
|
bitfld.long 0x00 0. " SEL_GP_IN_0 ,Select GP register 0" "0,1"
|
|
group.long (d:0x00003100+0x0A)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_3 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_2 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_1 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_0 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_3 ,Local Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_2 ,Local Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_1 ,Local Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_0 ,Local Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0C)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_7 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_6 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_5 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_4 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_7 ,Local Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_6 ,Local Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_5 ,Local Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_4 ,Local Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0E)++0x03
|
|
line.long 0x00 "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long 0x00 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long 0x00 0.--7. 1. "PULL,Data pointer for pull"
|
|
group.long (d:0x00003100+0x10)++0x03
|
|
line.long 0x00 "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long 0x00 0.--7. 1. "REG,General Purpose bit register"
|
|
group.long (d:0x00003100+0x12)++0x03
|
|
line.long 0x00 "CLB_OUT_EN,CELL output enable register"
|
|
group.long (d:0x00003100+0x14)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_3 ,Global Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_2 ,Global Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_1 ,Global Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_0 ,Global Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x16)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_7 ,Global Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_6 ,Global Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_5 ,Global Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_4 ,Global Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x18)++0x03
|
|
line.long 0x00 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long 0x00 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
bitfld.long 0x00 2.--5. " TAP ,TAP Select value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " STRB ,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x00 0. " CLKEN ,Enable the prescale clock generator" "0,1"
|
|
group.word (d:0x00003100+0x20)++0x01
|
|
line.word 0x00 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
bitfld.word 0x00 0.--5. " TAG ,Interrupt tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x22)++0x03
|
|
line.long 0x00 "CLB_LOCK,Lock control register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x00 0. " LOCK ,LOCK enable" "0,1"
|
|
group.word (d:0x00003100+0x24)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
bitfld.word 0x00 0.--4. " READ_PTR ,HLC instruction read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00003100+0x26)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x00 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long (d:0x00003100+0x2E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long 0x00 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long 0x00 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long (d:0x00003100+0x30)++0x03
|
|
line.long 0x00 "CLB_DBG_R0,R0 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x32)++0x03
|
|
line.long 0x00 "CLB_DBG_R1,R1 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x34)++0x03
|
|
line.long 0x00 "CLB_DBG_R2,R2 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x36)++0x03
|
|
line.long 0x00 "CLB_DBG_R3,R3 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x38)++0x03
|
|
line.long 0x00 "CLB_DBG_C0,Count of Unit 0"
|
|
rgroup.long (d:0x00003100+0x3A)++0x03
|
|
line.long 0x00 "CLB_DBG_C1,Count of Unit 1"
|
|
rgroup.long (d:0x00003100+0x3C)++0x03
|
|
line.long 0x00 "CLB_DBG_C2,Count of Unit 2"
|
|
rgroup.long (d:0x00003100+0x3E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0x00 31. " OUT7 ,CELL Output 7" "0,1"
|
|
bitfld.long 0x00 30. " OUT6 ,CELL Output 6" "0,1"
|
|
bitfld.long 0x00 29. " OUT5 ,CELL Output 5" "0,1"
|
|
bitfld.long 0x00 28. " OUT4 ,CELL Output 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " OUT3 ,CELL Output 3" "0,1"
|
|
bitfld.long 0x00 26. " OUT2 ,CELL Output 2" "0,1"
|
|
bitfld.long 0x00 25. " OUT1 ,CELL Output 1" "0,1"
|
|
bitfld.long 0x00 24. " OUT0 ,CELL Output 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " LUT42_OUT ,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 22. " FSM2_LUTOUT ,FSM_LUT_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 21. " FSM2_S1 ,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 20. " FSM2_S0 ,FSM_S0 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " COUNT2_MATCH1 ,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 18. " COUNT2_ZERO ,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0x00 17. " COUNT2_MATCH2 ,COUNT_MATCH2 UNIT 2" "0,1"
|
|
bitfld.long 0x00 15. " LUT41_OUT ,LUT4_OUT UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " FSM1_LUTOUT ,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0x00 13. " FSM1_S1 ,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0x00 12. " FSM1_S0 ,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0x00 11. " COUNT1_MATCH1 ,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " COUNT1_ZERO ,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0x00 9. " COUNT1_MATCH2 ,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0x00 7. " LUT40_OUT ,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0x00 6. " FSM0_LUTOUT ,FSM_LUT_OUT UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " FSM0_S1 ,FSM_S1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 4. " FSM0_S0 ,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0x00 3. " COUNT0_MATCH1 ,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 2. " COUNT0_ZERO ,COUNT_ZERO UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " COUNT0_MATCH2 ,COUNT_MATCH2 UNIT 0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb2DataExchRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00003180+0x00)++0x03
|
|
line.long 0x00 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
group.long (d:0x00003180+0x40)++0x03
|
|
line.long 0x00 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb3LogicCfgRegs"
|
|
width 25.
|
|
group.long (d:0x00003000+0x02)++0x03
|
|
line.long 0x00 "CLB_COUNT_RESET,Counter Block RESET"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Count Reset Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Count Reset Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Count Reset Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x04)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 1 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 1 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 1 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x06)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 0 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 0 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 0 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x08)++0x03
|
|
line.long 0x00 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter event select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter event select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter event select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0A)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0C)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN0 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN0 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN0 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0E)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN1 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN1 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN1 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x10)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x12)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x14)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x16)++0x03
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line.long 0x00 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x18)++0x03
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line.long 0x00 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x1C)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
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hexmask.long 0x00 16.--31. 1. "FN1,FSM LUT output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,FSM LUT output function for unit 0"
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group.long (d:0x00003000+0x1E)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,FSM LUT output function for unit 2"
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group.long (d:0x00003000+0x20)++0x03
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line.long 0x00 "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
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hexmask.long 0x00 16.--31. 1. "FN1,LUT4 output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,LUT4 output function for unit 0"
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group.long (d:0x00003000+0x22)++0x03
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line.long 0x00 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,LUT4 output function for unit 2"
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group.long (d:0x00003000+0x24)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x26)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x28)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x2A)++0x03
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line.long 0x00 "CLB_MISC_CONTROL,Static controls for Ctr,FSM"
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bitfld.long 0x00 26. " COUNT2_LFSR_EN ,Enable LFSR mode for Counter 2" "0,1"
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bitfld.long 0x00 25. " COUNT1_LFSR_EN ,Enable LFSR mode for Counter 1" "0,1"
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bitfld.long 0x00 24. " COUNT0_LFSR_EN ,Enable LFSR mode for Counter 0" "0,1"
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bitfld.long 0x00 23. " COUNT2_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 22. " COUNT1_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 21. " COUNT0_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 20. " COUNT2_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 19. " COUNT1_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 18. " COUNT0_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 17. " FSM_EXTRA_SEL1_2 ,FSM extra_sel1 for 2" "0,1"
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bitfld.long 0x00 16. " FSM_EXTRA_SEL0_2 ,FSM extra_sel0 for 2" "0,1"
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bitfld.long 0x00 15. " FSM_EXTRA_SEL1_1 ,FSM extra_sel1 for 1" "0,1"
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bitfld.long 0x00 14. " FSM_EXTRA_SEL0_1 ,FSM extra_sel0 for 1" "0,1"
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bitfld.long 0x00 13. " FSM_EXTRA_SEL1_0 ,FSM extra_sel1 for 0" "0,1"
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bitfld.long 0x00 12. " FSM_EXTRA_SEL0_0 ,FSM extra_sel0 for 0" "0,1"
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bitfld.long 0x00 11. " COUNT_SERIALIZER_2 ,Serializer enable 2" "0,1"
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bitfld.long 0x00 10. " COUNT_SERIALIZER_1 ,Serializer enable 1" "0,1"
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bitfld.long 0x00 9. " COUNT_SERIALIZER_0 ,Serializer enable 0" "0,1"
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bitfld.long 0x00 8. " COUNT_EVENT_CTRL_2 ,Event control for counter 2" "0,1"
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bitfld.long 0x00 7. " COUNT_DIR_2 ,Direction for counter 2" "0,1"
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bitfld.long 0x00 6. " COUNT_ADD_SHIFT_2 ,Add/Shift for counter 2" "0,1"
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bitfld.long 0x00 5. " COUNT_EVENT_CTRL_1 ,Event control for counter 1" "0,1"
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bitfld.long 0x00 4. " COUNT_DIR_1 ,Direction for counter 1" "0,1"
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bitfld.long 0x00 3. " COUNT_ADD_SHIFT_1 ,Add/Shift for counter 1" "0,1"
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bitfld.long 0x00 2. " COUNT_EVENT_CTRL_0 ,Event control for counter 0" "0,1"
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bitfld.long 0x00 1. " COUNT_DIR_0 ,Direction for counter 0" "0,1"
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bitfld.long 0x00 0. " COUNT_ADD_SHIFT_0 ,Add/Shift for counter 0" "0,1"
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group.long (d:0x00003000+0x2C)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_0,Inp Sel, LUT fns for Out0"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x2E)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_1,Inp Sel, LUT fns for Out1"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x30)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_2,Inp Sel, LUT fns for Out2"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x32)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_3,Inp Sel, LUT fns for Out3"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x34)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_4,Inp Sel, LUT fns for Out4"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x36)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_5,Inp Sel, LUT fns for Out5"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x38)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_6,Inp Sel, LUT fns for Out6"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3A)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_7,Inp Sel, LUT fns for Out7"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3C)++0x03
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line.long 0x00 "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
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bitfld.long 0x00 23. " ALT_EVENT3_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 22. " ALT_EVENT2_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 21. " ALT_EVENT1_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 20. " ALT_EVENT0_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 15.--19. " EVENT3_SEL ,Event Select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " EVENT2_SEL ,Event Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " EVENT1_SEL ,Event Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " EVENT0_SEL ,Event Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3E)++0x03
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line.long 0x00 "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
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bitfld.long 0x00 26.--30. " COUNT2_MATCH2 ,Match2 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 21.--25. " COUNT1_MATCH2 ,Match2 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " COUNT0_MATCH2 ,Match2 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " COUNT2_MATCH1 ,Match1 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " COUNT1_MATCH1 ,Match1 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " COUNT0_MATCH1 ,Match1 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x40)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
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group.long (d:0x00003000+0x42)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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|
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x44)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x46)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x48)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4A)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4C)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4E)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.word (d:0x00003000+0x50)++0x01
|
|
line.word 0x00 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x00 1. " BLKEN ,Block Register write" "0,1"
|
|
bitfld.word 0x00 0. " SPIEN ,Enable CLB SPI Buffer feature" "0,1"
|
|
group.word (d:0x00003000+0x51)++0x01
|
|
line.word 0x00 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
bitfld.word 0x00 8.--12. " SHIFT ,Shift value select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " STRB ,Select value for strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb3LogicCtrlRegs"
|
|
width 24.
|
|
group.word (d:0x00003100+0x00)++0x01
|
|
line.word 0x00 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x00 4. " PIPELINE_EN ,Enable input pipelining" "0,1"
|
|
bitfld.word 0x00 3. " NMI_EN ,NMI output enable" "0,1"
|
|
bitfld.word 0x00 2. " STOP ,Debug stop control" "0,1"
|
|
bitfld.word 0x00 1. " GLOBAL_EN ,Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " LOAD_EN ,Load Enable" "0,1"
|
|
group.long (d:0x00003100+0x02)++0x03
|
|
line.long 0x00 "CLB_LOAD_ADDR,Indirect address"
|
|
bitfld.long 0x00 0.--5. " ADDR ,Indirect Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x04)++0x03
|
|
line.long 0x00 "CLB_LOAD_DATA,Data for indirect loads"
|
|
group.long (d:0x00003100+0x06)++0x03
|
|
line.long 0x00 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x00 31. " PIPE7 ,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x00 30. " PIPE6 ,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x00 29. " PIPE5 ,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x00 28. " PIPE4 ,Enable pipeline 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " PIPE3 ,Enable pipeline 3" "0,1"
|
|
bitfld.long 0x00 26. " PIPE2 ,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x00 25. " PIPE1 ,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x00 24. " PIPE0 ,Enable pipeline 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SYNC7 ,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x00 22. " SYNC6 ,Synchronizer control 6" "0,1"
|
|
bitfld.long 0x00 21. " SYNC5 ,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x00 20. " SYNC4 ,Synchronizer control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SYNC3 ,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x00 18. " SYNC2 ,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x00 17. " SYNC1 ,Synchronizer control 1" "0,1"
|
|
bitfld.long 0x00 16. " SYNC0 ,Synchronizer control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " FIN7 ,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FIN6 ,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " FIN5 ,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " FIN4 ,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " FIN3 ,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " FIN2 ,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " FIN1 ,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FIN0 ,Input filter control 0" "0,1,2,3"
|
|
group.long (d:0x00003100+0x08)++0x03
|
|
line.long 0x00 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x00 31. " SW_GATING_CTRL_7 ,Software gating control 7" "0,1"
|
|
bitfld.long 0x00 30. " SW_GATING_CTRL_6 ,Software gating control 6" "0,1"
|
|
bitfld.long 0x00 29. " SW_GATING_CTRL_5 ,Software gating control 5" "0,1"
|
|
bitfld.long 0x00 28. " SW_GATING_CTRL_4 ,Software gating control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SW_GATING_CTRL_3 ,Software gating control 3" "0,1"
|
|
bitfld.long 0x00 26. " SW_GATING_CTRL_2 ,Software gating control 2" "0,1"
|
|
bitfld.long 0x00 25. " SW_GATING_CTRL_1 ,Software gating control 1" "0,1"
|
|
bitfld.long 0x00 24. " SW_GATING_CTRL_0 ,Software gating control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SW_RLS_CTRL_7 ,Software release control 7" "0,1"
|
|
bitfld.long 0x00 22. " SW_RLS_CTRL_6 ,Software release control 6" "0,1"
|
|
bitfld.long 0x00 21. " SW_RLS_CTRL_5 ,Software release control 5" "0,1"
|
|
bitfld.long 0x00 20. " SW_RLS_CTRL_4 ,Software release control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SW_RLS_CTRL_3 ,Software release control 3" "0,1"
|
|
bitfld.long 0x00 18. " SW_RLS_CTRL_2 ,Software release control 2" "0,1"
|
|
bitfld.long 0x00 17. " SW_RLS_CTRL_1 ,Software release control 1" "0,1"
|
|
bitfld.long 0x00 16. " SW_RLS_CTRL_0 ,Software release control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL_GP_IN_7 ,Select GP register 7" "0,1"
|
|
bitfld.long 0x00 6. " SEL_GP_IN_6 ,Select GP register 6" "0,1"
|
|
bitfld.long 0x00 5. " SEL_GP_IN_5 ,Select GP register 5" "0,1"
|
|
bitfld.long 0x00 4. " SEL_GP_IN_4 ,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SEL_GP_IN_3 ,Select GP register 3" "0,1"
|
|
bitfld.long 0x00 2. " SEL_GP_IN_2 ,Select GP register 2" "0,1"
|
|
bitfld.long 0x00 1. " SEL_GP_IN_1 ,Select GP register 1" "0,1"
|
|
bitfld.long 0x00 0. " SEL_GP_IN_0 ,Select GP register 0" "0,1"
|
|
group.long (d:0x00003100+0x0A)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_3 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_2 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_1 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_0 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_3 ,Local Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_2 ,Local Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_1 ,Local Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_0 ,Local Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0C)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_7 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_6 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_5 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_4 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_7 ,Local Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_6 ,Local Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_5 ,Local Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_4 ,Local Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0E)++0x03
|
|
line.long 0x00 "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long 0x00 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long 0x00 0.--7. 1. "PULL,Data pointer for pull"
|
|
group.long (d:0x00003100+0x10)++0x03
|
|
line.long 0x00 "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long 0x00 0.--7. 1. "REG,General Purpose bit register"
|
|
group.long (d:0x00003100+0x12)++0x03
|
|
line.long 0x00 "CLB_OUT_EN,CELL output enable register"
|
|
group.long (d:0x00003100+0x14)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_3 ,Global Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_2 ,Global Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_1 ,Global Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_0 ,Global Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x16)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_7 ,Global Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_6 ,Global Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_5 ,Global Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_4 ,Global Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x18)++0x03
|
|
line.long 0x00 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long 0x00 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
bitfld.long 0x00 2.--5. " TAP ,TAP Select value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " STRB ,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x00 0. " CLKEN ,Enable the prescale clock generator" "0,1"
|
|
group.word (d:0x00003100+0x20)++0x01
|
|
line.word 0x00 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
bitfld.word 0x00 0.--5. " TAG ,Interrupt tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x22)++0x03
|
|
line.long 0x00 "CLB_LOCK,Lock control register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x00 0. " LOCK ,LOCK enable" "0,1"
|
|
group.word (d:0x00003100+0x24)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
bitfld.word 0x00 0.--4. " READ_PTR ,HLC instruction read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00003100+0x26)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x00 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long (d:0x00003100+0x2E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long 0x00 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long 0x00 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long (d:0x00003100+0x30)++0x03
|
|
line.long 0x00 "CLB_DBG_R0,R0 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x32)++0x03
|
|
line.long 0x00 "CLB_DBG_R1,R1 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x34)++0x03
|
|
line.long 0x00 "CLB_DBG_R2,R2 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x36)++0x03
|
|
line.long 0x00 "CLB_DBG_R3,R3 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x38)++0x03
|
|
line.long 0x00 "CLB_DBG_C0,Count of Unit 0"
|
|
rgroup.long (d:0x00003100+0x3A)++0x03
|
|
line.long 0x00 "CLB_DBG_C1,Count of Unit 1"
|
|
rgroup.long (d:0x00003100+0x3C)++0x03
|
|
line.long 0x00 "CLB_DBG_C2,Count of Unit 2"
|
|
rgroup.long (d:0x00003100+0x3E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0x00 31. " OUT7 ,CELL Output 7" "0,1"
|
|
bitfld.long 0x00 30. " OUT6 ,CELL Output 6" "0,1"
|
|
bitfld.long 0x00 29. " OUT5 ,CELL Output 5" "0,1"
|
|
bitfld.long 0x00 28. " OUT4 ,CELL Output 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " OUT3 ,CELL Output 3" "0,1"
|
|
bitfld.long 0x00 26. " OUT2 ,CELL Output 2" "0,1"
|
|
bitfld.long 0x00 25. " OUT1 ,CELL Output 1" "0,1"
|
|
bitfld.long 0x00 24. " OUT0 ,CELL Output 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " LUT42_OUT ,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 22. " FSM2_LUTOUT ,FSM_LUT_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 21. " FSM2_S1 ,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 20. " FSM2_S0 ,FSM_S0 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " COUNT2_MATCH1 ,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 18. " COUNT2_ZERO ,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0x00 17. " COUNT2_MATCH2 ,COUNT_MATCH2 UNIT 2" "0,1"
|
|
bitfld.long 0x00 15. " LUT41_OUT ,LUT4_OUT UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " FSM1_LUTOUT ,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0x00 13. " FSM1_S1 ,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0x00 12. " FSM1_S0 ,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0x00 11. " COUNT1_MATCH1 ,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " COUNT1_ZERO ,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0x00 9. " COUNT1_MATCH2 ,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0x00 7. " LUT40_OUT ,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0x00 6. " FSM0_LUTOUT ,FSM_LUT_OUT UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " FSM0_S1 ,FSM_S1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 4. " FSM0_S0 ,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0x00 3. " COUNT0_MATCH1 ,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 2. " COUNT0_ZERO ,COUNT_ZERO UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " COUNT0_MATCH2 ,COUNT_MATCH2 UNIT 0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb3DataExchRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00003180+0x00)++0x03
|
|
line.long 0x00 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
group.long (d:0x00003180+0x40)++0x03
|
|
line.long 0x00 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb4LogicCfgRegs"
|
|
width 25.
|
|
group.long (d:0x00003000+0x02)++0x03
|
|
line.long 0x00 "CLB_COUNT_RESET,Counter Block RESET"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Count Reset Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Count Reset Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Count Reset Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x04)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_1,Counter Block MODE_1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 1 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 1 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 1 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x06)++0x03
|
|
line.long 0x00 "CLB_COUNT_MODE_0,Counter Block MODE_0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter mode 0 select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter mode 0 select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter mode 0 select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x08)++0x03
|
|
line.long 0x00 "CLB_COUNT_EVENT,Counter Block EVENT"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Counter event select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Counter event select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Counter event select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0A)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN0,FSM Extra EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0C)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN0,FSM EXT_IN0"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN0 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN0 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN0 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x0E)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTERNAL_IN1,FSM_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM EXT_IN1 select input for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM EXT_IN1 select input for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM EXT_IN1 select input for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x10)++0x03
|
|
line.long 0x00 "CLB_FSM_EXTRA_IN1,FSM Extra_EXT_IN1"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,FSM extra ext input select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,FSM extra ext input select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,FSM extra ext input select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x12)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN0,LUT4_0/1/2 IN0 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003000+0x14)++0x03
|
|
line.long 0x00 "CLB_LUT4_IN1,LUT4_0/1/2 IN1 input source"
|
|
bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x16)++0x03
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line.long 0x00 "CLB_LUT4_IN2,LUT4_0/1/2 IN2 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x18)++0x03
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line.long 0x00 "CLB_LUT4_IN3,LUT4_0/1/2 IN3 input source"
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bitfld.long 0x00 10.--14. " SEL_2 ,Select inputs for unit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " SEL_1 ,Select inputs for unit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " SEL_0 ,Select inputs for unit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x1C)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN1_0,LUT function for FSM Unit 1 and Unit 0"
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hexmask.long 0x00 16.--31. 1. "FN1,FSM LUT output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,FSM LUT output function for unit 0"
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group.long (d:0x00003000+0x1E)++0x03
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line.long 0x00 "CLB_FSM_LUT_FN2,LUT function for FSM Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,FSM LUT output function for unit 2"
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group.long (d:0x00003000+0x20)++0x03
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line.long 0x00 "CLB_LUT4_FN1_0,LUT function for LUT4 block of Unit 1 and 0"
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hexmask.long 0x00 16.--31. 1. "FN1,LUT4 output function for unit 1"
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hexmask.long 0x00 0.--15. 1. "FN0,LUT4 output function for unit 0"
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group.long (d:0x00003000+0x22)++0x03
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line.long 0x00 "CLB_LUT4_FN2,LUT function for LUT4 block of Unit 2"
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hexmask.long 0x00 0.--15. 1. "FN1,LUT4 output function for unit 2"
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group.long (d:0x00003000+0x24)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_0,FSM Next state equations for Unit 0"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x26)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_1,FSM Next state equations for Unit 1"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x28)++0x03
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line.long 0x00 "CLB_FSM_NEXT_STATE_2,FSM Next state equations for Unit 2"
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hexmask.long 0x00 16.--31. 1. "S1,FSM next state function for S1"
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hexmask.long 0x00 0.--15. 1. "S0,FSM next state function for S0"
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group.long (d:0x00003000+0x2A)++0x03
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line.long 0x00 "CLB_MISC_CONTROL,Static controls for Ctr,FSM"
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bitfld.long 0x00 26. " COUNT2_LFSR_EN ,Enable LFSR mode for Counter 2" "0,1"
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bitfld.long 0x00 25. " COUNT1_LFSR_EN ,Enable LFSR mode for Counter 1" "0,1"
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bitfld.long 0x00 24. " COUNT0_LFSR_EN ,Enable LFSR mode for Counter 0" "0,1"
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bitfld.long 0x00 23. " COUNT2_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 22. " COUNT1_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 21. " COUNT0_MATCH2_TAP_EN ,Match2 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 20. " COUNT2_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 2" "0,1"
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bitfld.long 0x00 19. " COUNT1_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 1" "0,1"
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bitfld.long 0x00 18. " COUNT0_MATCH1_TAP_EN ,Match1 Tap Enable for Counter 0" "0,1"
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bitfld.long 0x00 17. " FSM_EXTRA_SEL1_2 ,FSM extra_sel1 for 2" "0,1"
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bitfld.long 0x00 16. " FSM_EXTRA_SEL0_2 ,FSM extra_sel0 for 2" "0,1"
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bitfld.long 0x00 15. " FSM_EXTRA_SEL1_1 ,FSM extra_sel1 for 1" "0,1"
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bitfld.long 0x00 14. " FSM_EXTRA_SEL0_1 ,FSM extra_sel0 for 1" "0,1"
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bitfld.long 0x00 13. " FSM_EXTRA_SEL1_0 ,FSM extra_sel1 for 0" "0,1"
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bitfld.long 0x00 12. " FSM_EXTRA_SEL0_0 ,FSM extra_sel0 for 0" "0,1"
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bitfld.long 0x00 11. " COUNT_SERIALIZER_2 ,Serializer enable 2" "0,1"
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bitfld.long 0x00 10. " COUNT_SERIALIZER_1 ,Serializer enable 1" "0,1"
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bitfld.long 0x00 9. " COUNT_SERIALIZER_0 ,Serializer enable 0" "0,1"
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bitfld.long 0x00 8. " COUNT_EVENT_CTRL_2 ,Event control for counter 2" "0,1"
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bitfld.long 0x00 7. " COUNT_DIR_2 ,Direction for counter 2" "0,1"
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bitfld.long 0x00 6. " COUNT_ADD_SHIFT_2 ,Add/Shift for counter 2" "0,1"
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bitfld.long 0x00 5. " COUNT_EVENT_CTRL_1 ,Event control for counter 1" "0,1"
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bitfld.long 0x00 4. " COUNT_DIR_1 ,Direction for counter 1" "0,1"
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bitfld.long 0x00 3. " COUNT_ADD_SHIFT_1 ,Add/Shift for counter 1" "0,1"
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bitfld.long 0x00 2. " COUNT_EVENT_CTRL_0 ,Event control for counter 0" "0,1"
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bitfld.long 0x00 1. " COUNT_DIR_0 ,Direction for counter 0" "0,1"
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bitfld.long 0x00 0. " COUNT_ADD_SHIFT_0 ,Add/Shift for counter 0" "0,1"
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group.long (d:0x00003000+0x2C)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_0,Inp Sel, LUT fns for Out0"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x2E)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_1,Inp Sel, LUT fns for Out1"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x30)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_2,Inp Sel, LUT fns for Out2"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x32)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_3,Inp Sel, LUT fns for Out3"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x34)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_4,Inp Sel, LUT fns for Out4"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x36)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_5,Inp Sel, LUT fns for Out5"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x38)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_6,Inp Sel, LUT fns for Out6"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3A)++0x03
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line.long 0x00 "CLB_OUTPUT_LUT_7,Inp Sel, LUT fns for Out7"
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hexmask.long 0x00 15.--22. 1. "FN,Output function for output LUT"
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bitfld.long 0x00 10.--14. " IN2 ,Select value for IN2 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " IN1 ,Select value for IN1 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " IN0 ,Select value for IN0 of output LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3C)++0x03
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line.long 0x00 "CLB_HLC_EVENT_SEL,Event Selector register for the High Level controller"
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bitfld.long 0x00 23. " ALT_EVENT3_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 22. " ALT_EVENT2_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 21. " ALT_EVENT1_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 20. " ALT_EVENT0_SEL ,Event Select 3" "0,1"
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bitfld.long 0x00 15.--19. " EVENT3_SEL ,Event Select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " EVENT2_SEL ,Event Select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " EVENT1_SEL ,Event Select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " EVENT0_SEL ,Event Select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x3E)++0x03
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line.long 0x00 "CLB_COUNT_MATCH_TAP_SEL,Counter tap values for match1 and match2 outputs"
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bitfld.long 0x00 26.--30. " COUNT2_MATCH2 ,Match2 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 21.--25. " COUNT1_MATCH2 ,Match2 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. " COUNT0_MATCH2 ,Match2 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--14. " COUNT2_MATCH1 ,Match1 tap select for Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5.--9. " COUNT1_MATCH1 ,Match1 tap select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " COUNT0_MATCH1 ,Match1 tap select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long (d:0x00003000+0x40)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_0,Output conditioning control for output 0"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
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group.long (d:0x00003000+0x42)++0x03
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line.long 0x00 "CLB_OUTPUT_COND_CTRL_1,Output conditioning control for output 1"
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bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
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bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
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bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
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bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
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bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
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bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
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|
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bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x44)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_2,Output conditioning control for output 2"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x46)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_3,Output conditioning control for output 3"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x48)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_4,Output conditioning control for output 4"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4A)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_5,Output conditioning control for output 5"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4C)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_6,Output conditioning control for output 6"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.long (d:0x00003000+0x4E)++0x03
|
|
line.long 0x00 "CLB_OUTPUT_COND_CTRL_7,Output conditioning control for output 7"
|
|
bitfld.long 0x00 14. " ASYNC_COND_EN ,Enable for conditioning" "0,1"
|
|
bitfld.long 0x00 13. " SEL_RAW_IN ,Select Input for" "0,1"
|
|
bitfld.long 0x00 12. " HW_RLS_CTRL_SEL ,Select HW for release control" "0,1"
|
|
bitfld.long 0x00 11. " HW_GATING_CTRL_SEL ,Select HW for gating control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SEL_RELEASE_CTRL ,Releast control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SEL_GATING_CTRL ,Gating control mux select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. " LEVEL_3_SEL ,Level 3 Mux Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. " LEVEL_2_SEL ,Level 2 Mux Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. " LEVEL_1_SEL ,Level 1 Mux Select" "0,1"
|
|
group.word (d:0x00003000+0x50)++0x01
|
|
line.word 0x00 "CLB_MISC_ACCESS_CTRL,Miscellaneous Access and enable control"
|
|
bitfld.word 0x00 1. " BLKEN ,Block Register write" "0,1"
|
|
bitfld.word 0x00 0. " SPIEN ,Enable CLB SPI Buffer feature" "0,1"
|
|
group.word (d:0x00003000+0x51)++0x01
|
|
line.word 0x00 "CLB_SPI_DATA_CTRL_HI,CLB to SPI buffer control High"
|
|
bitfld.word 0x00 8.--12. " SHIFT ,Shift value select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " STRB ,Select value for strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb4LogicCtrlRegs"
|
|
width 24.
|
|
group.word (d:0x00003100+0x00)++0x01
|
|
line.word 0x00 "CLB_LOAD_EN,Global enable and indirect load enable control"
|
|
bitfld.word 0x00 4. " PIPELINE_EN ,Enable input pipelining" "0,1"
|
|
bitfld.word 0x00 3. " NMI_EN ,NMI output enable" "0,1"
|
|
bitfld.word 0x00 2. " STOP ,Debug stop control" "0,1"
|
|
bitfld.word 0x00 1. " GLOBAL_EN ,Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " LOAD_EN ,Load Enable" "0,1"
|
|
group.long (d:0x00003100+0x02)++0x03
|
|
line.long 0x00 "CLB_LOAD_ADDR,Indirect address"
|
|
bitfld.long 0x00 0.--5. " ADDR ,Indirect Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x04)++0x03
|
|
line.long 0x00 "CLB_LOAD_DATA,Data for indirect loads"
|
|
group.long (d:0x00003100+0x06)++0x03
|
|
line.long 0x00 "CLB_INPUT_FILTER,Input filter selection for both edge detection and synchronizers"
|
|
bitfld.long 0x00 31. " PIPE7 ,Enable pipeline 7" "0,1"
|
|
bitfld.long 0x00 30. " PIPE6 ,Enable pipeline 6" "0,1"
|
|
bitfld.long 0x00 29. " PIPE5 ,Enable pipeline 5" "0,1"
|
|
bitfld.long 0x00 28. " PIPE4 ,Enable pipeline 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " PIPE3 ,Enable pipeline 3" "0,1"
|
|
bitfld.long 0x00 26. " PIPE2 ,Enable pipeline 2" "0,1"
|
|
bitfld.long 0x00 25. " PIPE1 ,Enable pipeline 1" "0,1"
|
|
bitfld.long 0x00 24. " PIPE0 ,Enable pipeline 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SYNC7 ,Synchronizer control 7" "0,1"
|
|
bitfld.long 0x00 22. " SYNC6 ,Synchronizer control 6" "0,1"
|
|
bitfld.long 0x00 21. " SYNC5 ,Synchronizer control 5" "0,1"
|
|
bitfld.long 0x00 20. " SYNC4 ,Synchronizer control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SYNC3 ,Synchronizer control 3" "0,1"
|
|
bitfld.long 0x00 18. " SYNC2 ,Synchronizer control 2" "0,1"
|
|
bitfld.long 0x00 17. " SYNC1 ,Synchronizer control 1" "0,1"
|
|
bitfld.long 0x00 16. " SYNC0 ,Synchronizer control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " FIN7 ,Input filter control 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FIN6 ,Input filter control 6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " FIN5 ,Input filter control 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " FIN4 ,Input filter control 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " FIN3 ,Input filter control 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " FIN2 ,Input filter control 2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " FIN1 ,Input filter control 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " FIN0 ,Input filter control 0" "0,1,2,3"
|
|
group.long (d:0x00003100+0x08)++0x03
|
|
line.long 0x00 "CLB_IN_MUX_SEL_0,Input selection to decide between Signals and GP register"
|
|
bitfld.long 0x00 31. " SW_GATING_CTRL_7 ,Software gating control 7" "0,1"
|
|
bitfld.long 0x00 30. " SW_GATING_CTRL_6 ,Software gating control 6" "0,1"
|
|
bitfld.long 0x00 29. " SW_GATING_CTRL_5 ,Software gating control 5" "0,1"
|
|
bitfld.long 0x00 28. " SW_GATING_CTRL_4 ,Software gating control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SW_GATING_CTRL_3 ,Software gating control 3" "0,1"
|
|
bitfld.long 0x00 26. " SW_GATING_CTRL_2 ,Software gating control 2" "0,1"
|
|
bitfld.long 0x00 25. " SW_GATING_CTRL_1 ,Software gating control 1" "0,1"
|
|
bitfld.long 0x00 24. " SW_GATING_CTRL_0 ,Software gating control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SW_RLS_CTRL_7 ,Software release control 7" "0,1"
|
|
bitfld.long 0x00 22. " SW_RLS_CTRL_6 ,Software release control 6" "0,1"
|
|
bitfld.long 0x00 21. " SW_RLS_CTRL_5 ,Software release control 5" "0,1"
|
|
bitfld.long 0x00 20. " SW_RLS_CTRL_4 ,Software release control 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SW_RLS_CTRL_3 ,Software release control 3" "0,1"
|
|
bitfld.long 0x00 18. " SW_RLS_CTRL_2 ,Software release control 2" "0,1"
|
|
bitfld.long 0x00 17. " SW_RLS_CTRL_1 ,Software release control 1" "0,1"
|
|
bitfld.long 0x00 16. " SW_RLS_CTRL_0 ,Software release control 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL_GP_IN_7 ,Select GP register 7" "0,1"
|
|
bitfld.long 0x00 6. " SEL_GP_IN_6 ,Select GP register 6" "0,1"
|
|
bitfld.long 0x00 5. " SEL_GP_IN_5 ,Select GP register 5" "0,1"
|
|
bitfld.long 0x00 4. " SEL_GP_IN_4 ,Select GP register 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SEL_GP_IN_3 ,Select GP register 3" "0,1"
|
|
bitfld.long 0x00 2. " SEL_GP_IN_2 ,Select GP register 2" "0,1"
|
|
bitfld.long 0x00 1. " SEL_GP_IN_1 ,Select GP register 1" "0,1"
|
|
bitfld.long 0x00 0. " SEL_GP_IN_0 ,Select GP register 0" "0,1"
|
|
group.long (d:0x00003100+0x0A)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_1,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_3 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_2 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_1 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_0 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_3 ,Local Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_2 ,Local Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_1 ,Local Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_0 ,Local Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0C)++0x03
|
|
line.long 0x00 "CLB_LCL_MUX_SEL_2,Input Mux selection for local mux"
|
|
bitfld.long 0x00 31. " MISC_INPUT_SEL_7 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 30. " MISC_INPUT_SEL_6 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 29. " MISC_INPUT_SEL_5 ,Select MISC_INPUT" "0,1"
|
|
bitfld.long 0x00 28. " MISC_INPUT_SEL_4 ,Select MISC_INPUT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15.--19. " LCL_MUX_SEL_IN_7 ,Local Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--14. " LCL_MUX_SEL_IN_6 ,Local Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " LCL_MUX_SEL_IN_5 ,Local Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LCL_MUX_SEL_IN_4 ,Local Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00003100+0x0E)++0x03
|
|
line.long 0x00 "CLB_BUF_PTR,PUSH and PULL pointers"
|
|
hexmask.long 0x00 16.--23. 1. "PUSH,Data pointer for pull"
|
|
hexmask.long 0x00 0.--7. 1. "PULL,Data pointer for pull"
|
|
group.long (d:0x00003100+0x10)++0x03
|
|
line.long 0x00 "CLB_GP_REG,General purpose register for CELL inputs"
|
|
hexmask.long 0x00 0.--7. 1. "REG,General Purpose bit register"
|
|
group.long (d:0x00003100+0x12)++0x03
|
|
line.long 0x00 "CLB_OUT_EN,CELL output enable register"
|
|
group.long (d:0x00003100+0x14)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_1,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_3 ,Global Mux select 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_2 ,Global Mux select 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_1 ,Global Mux select 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_0 ,Global Mux select 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x16)++0x03
|
|
line.long 0x00 "CLB_GLBL_MUX_SEL_2,Global Mux select for CELL inputs"
|
|
bitfld.long 0x00 21.--27. " GLBL_MUX_SEL_IN_7 ,Global Mux select 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14.--20. " GLBL_MUX_SEL_IN_6 ,Global Mux select 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7.--13. " GLBL_MUX_SEL_IN_5 ,Global Mux select 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " GLBL_MUX_SEL_IN_4 ,Global Mux select 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00003100+0x18)++0x03
|
|
line.long 0x00 "CLB_PRESCALE_CTRL,Prescaler register control"
|
|
hexmask.long 0x00 16.--31. 1. "PRESCALE,Value of prescale register"
|
|
bitfld.long 0x00 2.--5. " TAP ,TAP Select value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " STRB ,Enable the Strobe mode of operation" "0,1"
|
|
bitfld.long 0x00 0. " CLKEN ,Enable the prescale clock generator" "0,1"
|
|
group.word (d:0x00003100+0x20)++0x01
|
|
line.word 0x00 "CLB_INTR_TAG_REG,Interrupt Tag register"
|
|
bitfld.word 0x00 0.--5. " TAG ,Interrupt tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x00003100+0x22)++0x03
|
|
line.long 0x00 "CLB_LOCK,Lock control register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key for enabling write"
|
|
bitfld.long 0x00 0. " LOCK ,LOCK enable" "0,1"
|
|
group.word (d:0x00003100+0x24)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_READ_PTR,HLC instruction read pointer"
|
|
bitfld.word 0x00 0.--4. " READ_PTR ,HLC instruction read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00003100+0x26)++0x01
|
|
line.word 0x00 "CLB_HLC_INSTR_VALUE,HLC instruction read value"
|
|
hexmask.word 0x00 0.--11. 1. "INSTR,HLC instruction value"
|
|
group.long (d:0x00003100+0x2E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT_2,Visibility for CLB inputs and final asynchronous outputs"
|
|
hexmask.long 0x00 8.--15. 1. "IN,CLB CELL Inputs"
|
|
hexmask.long 0x00 0.--7. 1. "OUT,Outputs of CLB Async block"
|
|
rgroup.long (d:0x00003100+0x30)++0x03
|
|
line.long 0x00 "CLB_DBG_R0,R0 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x32)++0x03
|
|
line.long 0x00 "CLB_DBG_R1,R1 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x34)++0x03
|
|
line.long 0x00 "CLB_DBG_R2,R2 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x36)++0x03
|
|
line.long 0x00 "CLB_DBG_R3,R3 of High level Controller"
|
|
rgroup.long (d:0x00003100+0x38)++0x03
|
|
line.long 0x00 "CLB_DBG_C0,Count of Unit 0"
|
|
rgroup.long (d:0x00003100+0x3A)++0x03
|
|
line.long 0x00 "CLB_DBG_C1,Count of Unit 1"
|
|
rgroup.long (d:0x00003100+0x3C)++0x03
|
|
line.long 0x00 "CLB_DBG_C2,Count of Unit 2"
|
|
rgroup.long (d:0x00003100+0x3E)++0x03
|
|
line.long 0x00 "CLB_DBG_OUT,Outputs of various units in the Cell"
|
|
bitfld.long 0x00 31. " OUT7 ,CELL Output 7" "0,1"
|
|
bitfld.long 0x00 30. " OUT6 ,CELL Output 6" "0,1"
|
|
bitfld.long 0x00 29. " OUT5 ,CELL Output 5" "0,1"
|
|
bitfld.long 0x00 28. " OUT4 ,CELL Output 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " OUT3 ,CELL Output 3" "0,1"
|
|
bitfld.long 0x00 26. " OUT2 ,CELL Output 2" "0,1"
|
|
bitfld.long 0x00 25. " OUT1 ,CELL Output 1" "0,1"
|
|
bitfld.long 0x00 24. " OUT0 ,CELL Output 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " LUT42_OUT ,LUT4_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 22. " FSM2_LUTOUT ,FSM_LUT_OUT UNIT 2" "0,1"
|
|
bitfld.long 0x00 21. " FSM2_S1 ,FSM_S1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 20. " FSM2_S0 ,FSM_S0 UNIT 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " COUNT2_MATCH1 ,COUNT_MATCH1 UNIT 2" "0,1"
|
|
bitfld.long 0x00 18. " COUNT2_ZERO ,COUNT_ZERO UNIT 2" "0,1"
|
|
bitfld.long 0x00 17. " COUNT2_MATCH2 ,COUNT_MATCH2 UNIT 2" "0,1"
|
|
bitfld.long 0x00 15. " LUT41_OUT ,LUT4_OUT UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " FSM1_LUTOUT ,FSM_LUT_OUT UNIT 1" "0,1"
|
|
bitfld.long 0x00 13. " FSM1_S1 ,FSM_S1 UNIT 1" "0,1"
|
|
bitfld.long 0x00 12. " FSM1_S0 ,FSM_S0 UNIT 1" "0,1"
|
|
bitfld.long 0x00 11. " COUNT1_MATCH1 ,COUNT_MATCH1 UNIT 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " COUNT1_ZERO ,COUNT_ZERO UNIT 1" "0,1"
|
|
bitfld.long 0x00 9. " COUNT1_MATCH2 ,COUNT_MATCH2 UNIT 1" "0,1"
|
|
bitfld.long 0x00 7. " LUT40_OUT ,LUT4_OUT UNIT 0" "0,1"
|
|
bitfld.long 0x00 6. " FSM0_LUTOUT ,FSM_LUT_OUT UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " FSM0_S1 ,FSM_S1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 4. " FSM0_S0 ,FSM_S0 UNIT 0" "0,1"
|
|
bitfld.long 0x00 3. " COUNT0_MATCH1 ,COUNT_MATCH1 UNIT 0" "0,1"
|
|
bitfld.long 0x00 2. " COUNT0_ZERO ,COUNT_ZERO UNIT 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " COUNT0_MATCH2 ,COUNT_MATCH2 UNIT 0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clb4DataExchRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00003180+0x00)++0x03
|
|
line.long 0x00 "CLB_PUSH,CLB_PUSH FIFO Registers (from HLC)"
|
|
group.long (d:0x00003180+0x40)++0x03
|
|
line.long 0x00 "CLB_PULL,CLB_PULL FIFO Registers (TO HLC)"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "Comparator Subsystems (CMPSS)"
|
|
tree "1"
|
|
width 17.
|
|
group.word (d:0x00005C80+0x0)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0x0+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0x0+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0x0+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0x0+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0x0+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x0+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x0+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0x0+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x0+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0x0+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x0+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0x0+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x0+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x0+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x0+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x0+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x0+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x0+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x0+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x0+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "2"
|
|
width 17.
|
|
group.word (d:0x00005C80+0x20)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0x20+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0x20+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0x20+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0x20+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0x20+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x20+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x20+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0x20+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x20+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0x20+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x20+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0x20+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x20+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x20+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x20+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x20+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x20+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x20+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x20+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x20+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "3"
|
|
width 17.
|
|
group.word (d:0x00005C80+0x40)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0x40+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0x40+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0x40+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0x40+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0x40+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x40+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x40+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0x40+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x40+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0x40+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x40+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0x40+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x40+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x40+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x40+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x40+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x40+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x40+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x40+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x40+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "4"
|
|
width 17.
|
|
group.word (d:0x00005C80+0x60)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0x60+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0x60+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0x60+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0x60+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0x60+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x60+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x60+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0x60+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x60+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0x60+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x60+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0x60+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x60+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x60+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x60+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x60+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x60+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x60+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x60+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x60+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "5"
|
|
width 17.
|
|
group.word (d:0x00005C80+0x80)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0x80+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0x80+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0x80+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0x80+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0x80+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x80+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x80+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0x80+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x80+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0x80+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0x80+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0x80+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x80+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0x80+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x80+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0x80+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x80+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x80+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0x80+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0x80+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "6"
|
|
width 17.
|
|
group.word (d:0x00005C80+0xA0)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0xA0+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0xA0+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0xA0+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0xA0+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0xA0+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xA0+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xA0+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0xA0+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xA0+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0xA0+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xA0+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0xA0+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xA0+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xA0+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xA0+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xA0+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xA0+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xA0+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xA0+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xA0+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "7"
|
|
width 17.
|
|
group.word (d:0x00005C80+0xC0)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0xC0+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0xC0+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0xC0+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0xC0+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0xC0+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xC0+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xC0+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0xC0+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xC0+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0xC0+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xC0+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0xC0+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xC0+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xC0+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xC0+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xC0+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xC0+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xC0+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xC0+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xC0+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "8"
|
|
width 17.
|
|
group.word (d:0x00005C80+0xE0)++0x01
|
|
line.word 0x00 "COMPCTL,CMPSS Comparator Control Register"
|
|
bitfld.word 0x00 15. " COMPDACE ,Comparator/DAC Enable" "0,1"
|
|
bitfld.word 0x00 14. " ASYNCLEN ,Low Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 12.--13. " CTRIPOUTLSEL ,Low Comparator Trip Output Select" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " CTRIPLSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 9. " COMPLINV ,Low Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSOURCE ,Low Comparator Source Select" "0,1"
|
|
bitfld.word 0x00 6. " ASYNCHEN ,High Comparator Asynchronous Path Enable" "0,1"
|
|
bitfld.word 0x00 4.--5. " CTRIPOUTHSEL ,High Comparator Trip Output Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " CTRIPHSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 1. " COMPHINV ,High Comparator Invert Select" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSOURCE ,High Comparator Source Select" "0,1"
|
|
group.word (d:0x00005C80+0xE0+0x01)++0x01
|
|
line.word 0x00 "COMPHYSCTL,CMPSS Comparator Hysteresis Control Register"
|
|
bitfld.word 0x00 0.--2. " COMPHYS ,Comparator Hysteresis Trim" "0,1,2,3,4,5,6,7"
|
|
rgroup.word (d:0x00005C80+0xE0+0x02)++0x01
|
|
line.word 0x00 "COMPSTS,CMPSS Comparator Status Register"
|
|
bitfld.word 0x00 9. " COMPLLATCH ,Low Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 8. " COMPLSTS ,Low Comparator Status" "0,1"
|
|
bitfld.word 0x00 1. " COMPHLATCH ,High Comparator Latched Status" "0,1"
|
|
bitfld.word 0x00 0. " COMPHSTS ,High Comparator Status" "0,1"
|
|
group.word (d:0x00005C80+0xE0+0x03)++0x01
|
|
line.word 0x00 "COMPSTSCLR,CMPSS Comparator Status Clear Register"
|
|
bitfld.word 0x00 10. " LSYNCCLREN ,Low Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 9. " LLATCHCLR ,Low Comparator Latched Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " HSYNCCLREN ,High Comparator EPWMSYNCPER Clear Enable" "0,1"
|
|
bitfld.word 0x00 1. " HLATCHCLR ,High Comparator Latched Status Clear" "0,1"
|
|
group.word (d:0x00005C80+0xE0+0x04)++0x01
|
|
line.word 0x00 "COMPDACCTL,CMPSS DAC Control Register"
|
|
bitfld.word 0x00 14.--15. " FREESOFT ,Free/Soft Emulation Bits" "0,1,2,3"
|
|
bitfld.word 0x00 12. " BLANKEN ,EPWMBLANK Enable" "0,1"
|
|
bitfld.word 0x00 8.--11. " BLANKSOURCE ,EPWMBLANK Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 7. " SWLOADSEL ,Software Load Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " RAMPLOADSEL ,Ramp Load Select" "0,1"
|
|
bitfld.word 0x00 5. " SELREF ,DAC Reference Select" "0,1"
|
|
bitfld.word 0x00 1.--4. " RAMPSOURCE ,Ramp Generator Source Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " DACSOURCE ,DAC Source Control" "0,1"
|
|
group.word (d:0x00005C80+0xE0+0x06)++0x01
|
|
line.word 0x00 "DACHVALS,CMPSS High DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xE0+0x07)++0x01
|
|
line.word 0x00 "DACHVALA,CMPSS High DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xE0+0x08)++0x01
|
|
line.word 0x00 "RAMPMAXREFA,CMPSS Ramp Max Reference Active Register"
|
|
group.word (d:0x00005C80+0xE0+0x0A)++0x01
|
|
line.word 0x00 "RAMPMAXREFS,CMPSS Ramp Max Reference Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xE0+0x0C)++0x01
|
|
line.word 0x00 "RAMPDECVALA,CMPSS Ramp Decrement Value Active Register"
|
|
group.word (d:0x00005C80+0xE0+0x0E)++0x01
|
|
line.word 0x00 "RAMPDECVALS,CMPSS Ramp Decrement Value Shadow Register"
|
|
rgroup.word (d:0x00005C80+0xE0+0x10)++0x01
|
|
line.word 0x00 "RAMPSTS,CMPSS Ramp Status Register"
|
|
group.word (d:0x00005C80+0xE0+0x12)++0x01
|
|
line.word 0x00 "DACLVALS,CMPSS Low DAC Value Shadow Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xE0+0x13)++0x01
|
|
line.word 0x00 "DACLVALA,CMPSS Low DAC Value Active Register"
|
|
hexmask.word 0x00 0.--11. 1. "DACVAL,DAC Value Control"
|
|
rgroup.word (d:0x00005C80+0xE0+0x14)++0x01
|
|
line.word 0x00 "RAMPDLYA,CMPSS Ramp Delay Active Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xE0+0x15)++0x01
|
|
line.word 0x00 "RAMPDLYS,CMPSS Ramp Delay Shadow Register"
|
|
hexmask.word 0x00 0.--12. 1. "DELAY,Ramp Delay Value"
|
|
group.word (d:0x00005C80+0xE0+0x16)++0x01
|
|
line.word 0x00 "CTRIPLFILCTL,CTRIPL Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xE0+0x17)++0x01
|
|
line.word 0x00 "CTRIPLFILCLKCTL,CTRIPL Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xE0+0x18)++0x01
|
|
line.word 0x00 "CTRIPHFILCTL,CTRIPH Filter Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005C80+0xE0+0x19)++0x01
|
|
line.word 0x00 "CTRIPHFILCLKCTL,CTRIPH Filter Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005C80+0xE0+0x1A)++0x01
|
|
line.word 0x00 "COMPLOCK,CMPSS Lock Register"
|
|
bitfld.word 0x00 3. " CTRIP ,CTRIP Lock" "0,1"
|
|
bitfld.word 0x00 2. " DACCTL ,DACCTL Lock" "0,1"
|
|
bitfld.word 0x00 1. " COMPHYSCTL ,COMPHYSCTL Lock" "0,1"
|
|
bitfld.word 0x00 0. " COMPCTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Buffered Digital to Analog Converter (DAC)"
|
|
tree "DAC A"
|
|
width 10.
|
|
rgroup.word (d:0x00005C00+0x00)++0x01
|
|
line.word 0x00 "DACREV,DAC Revision Register"
|
|
hexmask.word 0x00 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word (d:0x00005C00+0x01)++0x01
|
|
line.word 0x00 "DACCTL,DAC Control Register"
|
|
bitfld.word 0x00 4.--7. " SYNCSEL ,DAC EPWMSYNCPER Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " LOADMODE ,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x00 0. " DACREFSEL ,DAC Reference Select" "0,1"
|
|
rgroup.word (d:0x00005C00+0x02)++0x01
|
|
line.word 0x00 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word (d:0x00005C00+0x03)++0x01
|
|
line.word 0x00 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
group.word (d:0x00005C00+0x04)++0x01
|
|
line.word 0x00 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x00 0. " DACOUTEN ,DAC Output Code" "0,1"
|
|
group.word (d:0x00005C00+0x05)++0x01
|
|
line.word 0x00 "DACLOCK,DAC Lock Register"
|
|
bitfld.word 0x00 12.--15. " KEY ,DAC Register Lock Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " DACOUTEN ,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x00 1. " DACVAL ,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x00 0. " DACCTL ,DAC Control Register Lock" "0,1"
|
|
group.word (d:0x00005C00+0x06)++0x01
|
|
line.word 0x00 "DACTRIM,DAC Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC B"
|
|
width 10.
|
|
rgroup.word (d:0x00005C10+0x00)++0x01
|
|
line.word 0x00 "DACREV,DAC Revision Register"
|
|
hexmask.word 0x00 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word (d:0x00005C10+0x01)++0x01
|
|
line.word 0x00 "DACCTL,DAC Control Register"
|
|
bitfld.word 0x00 4.--7. " SYNCSEL ,DAC EPWMSYNCPER Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " LOADMODE ,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x00 0. " DACREFSEL ,DAC Reference Select" "0,1"
|
|
rgroup.word (d:0x00005C10+0x02)++0x01
|
|
line.word 0x00 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word (d:0x00005C10+0x03)++0x01
|
|
line.word 0x00 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
group.word (d:0x00005C10+0x04)++0x01
|
|
line.word 0x00 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x00 0. " DACOUTEN ,DAC Output Code" "0,1"
|
|
group.word (d:0x00005C10+0x05)++0x01
|
|
line.word 0x00 "DACLOCK,DAC Lock Register"
|
|
bitfld.word 0x00 12.--15. " KEY ,DAC Register Lock Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " DACOUTEN ,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x00 1. " DACVAL ,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x00 0. " DACCTL ,DAC Control Register Lock" "0,1"
|
|
group.word (d:0x00005C10+0x06)++0x01
|
|
line.word 0x00 "DACTRIM,DAC Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC C"
|
|
width 10.
|
|
rgroup.word (d:0x00005C20+0x00)++0x01
|
|
line.word 0x00 "DACREV,DAC Revision Register"
|
|
hexmask.word 0x00 0.--7. 1. "REV,DAC Revision Register"
|
|
group.word (d:0x00005C20+0x01)++0x01
|
|
line.word 0x00 "DACCTL,DAC Control Register"
|
|
bitfld.word 0x00 4.--7. " SYNCSEL ,DAC EPWMSYNCPER Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " LOADMODE ,DACVALA Load Mode" "0,1"
|
|
bitfld.word 0x00 0. " DACREFSEL ,DAC Reference Select" "0,1"
|
|
rgroup.word (d:0x00005C20+0x02)++0x01
|
|
line.word 0x00 "DACVALA,DAC Value Register - Active"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALA,DAC Active Output Code"
|
|
group.word (d:0x00005C20+0x03)++0x01
|
|
line.word 0x00 "DACVALS,DAC Value Register - Shadow"
|
|
hexmask.word 0x00 0.--11. 1. "DACVALS,DAC Shadow Output Code"
|
|
group.word (d:0x00005C20+0x04)++0x01
|
|
line.word 0x00 "DACOUTEN,DAC Output Enable Register"
|
|
bitfld.word 0x00 0. " DACOUTEN ,DAC Output Code" "0,1"
|
|
group.word (d:0x00005C20+0x05)++0x01
|
|
line.word 0x00 "DACLOCK,DAC Lock Register"
|
|
bitfld.word 0x00 12.--15. " KEY ,DAC Register Lock Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " DACOUTEN ,DAC Output Enable Register Lock" "0,1"
|
|
bitfld.word 0x00 1. " DACVAL ,DAC Value Register Lock" "0,1"
|
|
bitfld.word 0x00 0. " DACCTL ,DAC Control Register Lock" "0,1"
|
|
group.word (d:0x00005C20+0x06)++0x01
|
|
line.word 0x00 "DACTRIM,DAC Trim Register"
|
|
hexmask.word 0x00 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Dual-Clock Comparator (DCC)"
|
|
tree "DCC 1"
|
|
width 15.
|
|
group.long (d:0x0005E700+0x0+0x00)++0x03
|
|
line.long 0x00 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
bitfld.long 0x00 12.--15. " DONEENA ,DONE Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single-Shot Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E700+0x0+0x08)++0x03
|
|
line.long 0x00 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
group.long (d:0x0005E700+0x0+0x0C)++0x03
|
|
line.long 0x00 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
group.long (d:0x0005E700+0x0+0x10)++0x03
|
|
line.long 0x00 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
group.long (d:0x0005E700+0x0+0x14)++0x03
|
|
line.long 0x00 "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0x00 1. " DONE ,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0x00 0. " ERR ,Error Flag" "0,1"
|
|
rgroup.long (d:0x0005E700+0x0+0x18)++0x03
|
|
line.long 0x00 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
rgroup.long (d:0x0005E700+0x0+0x1C)++0x03
|
|
line.long 0x00 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
rgroup.long (d:0x0005E700+0x0+0x20)++0x03
|
|
line.long 0x00 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long (d:0x0005E700+0x0+0x24)++0x03
|
|
line.long 0x00 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " CLKSRC1 ,Clock Source Select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x0005E700+0x0+0x28)++0x03
|
|
line.long 0x00 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CLKSRC0 ,Clock Source Select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCC 2"
|
|
width 15.
|
|
group.long (d:0x0005E700+0x40+0x00)++0x03
|
|
line.long 0x00 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
bitfld.long 0x00 12.--15. " DONEENA ,DONE Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single-Shot Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E700+0x40+0x08)++0x03
|
|
line.long 0x00 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
group.long (d:0x0005E700+0x40+0x0C)++0x03
|
|
line.long 0x00 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
group.long (d:0x0005E700+0x40+0x10)++0x03
|
|
line.long 0x00 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
group.long (d:0x0005E700+0x40+0x14)++0x03
|
|
line.long 0x00 "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0x00 1. " DONE ,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0x00 0. " ERR ,Error Flag" "0,1"
|
|
rgroup.long (d:0x0005E700+0x40+0x18)++0x03
|
|
line.long 0x00 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
rgroup.long (d:0x0005E700+0x40+0x1C)++0x03
|
|
line.long 0x00 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
rgroup.long (d:0x0005E700+0x40+0x20)++0x03
|
|
line.long 0x00 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long (d:0x0005E700+0x40+0x24)++0x03
|
|
line.long 0x00 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " CLKSRC1 ,Clock Source Select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x0005E700+0x40+0x28)++0x03
|
|
line.long 0x00 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CLKSRC0 ,Clock Source Select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCC 3"
|
|
width 15.
|
|
group.long (d:0x0005E700+0x80+0x00)++0x03
|
|
line.long 0x00 "DCCGCTRL,Starts / stops the counters. Clears the error signal."
|
|
bitfld.long 0x00 12.--15. " DONEENA ,DONE Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single-Shot Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E700+0x80+0x08)++0x03
|
|
line.long 0x00 "DCCCNTSEED0,Seed value for the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED0,Seed Value for Counter 0"
|
|
group.long (d:0x0005E700+0x80+0x0C)++0x03
|
|
line.long 0x00 "DCCVALIDSEED0,Seed value for the timeout counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALIDSEED,Seed Value for Valid Duration Counter 0"
|
|
group.long (d:0x0005E700+0x80+0x10)++0x03
|
|
line.long 0x00 "DCCCNTSEED1,Seed value for the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNTSEED1,Seed Value for Counter 1"
|
|
group.long (d:0x0005E700+0x80+0x14)++0x03
|
|
line.long 0x00 "DCCSTATUS,Specifies the status of the DCC Module."
|
|
bitfld.long 0x00 1. " DONE ,Single-Shot Done Flag" "0,1"
|
|
bitfld.long 0x00 0. " ERR ,Error Flag" "0,1"
|
|
rgroup.long (d:0x0005E700+0x80+0x18)++0x03
|
|
line.long 0x00 "DCCCNT0,Value of the counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT0,Current Value of Counter 0"
|
|
rgroup.long (d:0x0005E700+0x80+0x1C)++0x03
|
|
line.long 0x00 "DCCVALID0,Value of the valid counter attached to Clock Source 0."
|
|
hexmask.long 0x00 0.--15. 1. "VALID0,Current Value of Valid 0"
|
|
rgroup.long (d:0x0005E700+0x80+0x20)++0x03
|
|
line.long 0x00 "DCCCNT1,Value of the counter attached to Clock Source 1."
|
|
hexmask.long 0x00 0.--19. 1. "COUNT1,Current Value of Counter 1"
|
|
group.long (d:0x0005E700+0x80+0x24)++0x03
|
|
line.long 0x00 "DCCCLKSRC1,Selects the clock source for Counter 1."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " CLKSRC1 ,Clock Source Select for Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x0005E700+0x80+0x28)++0x03
|
|
line.long 0x00 "DCCCLKSRC0,Selects the clock source for Counter 0."
|
|
bitfld.long 0x00 12.--15. " KEY ,Enables or Disables Clock Source Selection for COUNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CLKSRC0 ,Clock Source Select for Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Dual Code Security Module (DCSM)"
|
|
tree "Common"
|
|
width 12.
|
|
group.long (d:0x0005F0C0+0x00)++0x03
|
|
line.long 0x00 "FLSEM,Flash Wrapper Semaphore Register"
|
|
hexmask.long 0x00 8.--15. 1. "KEY,Semaphore Key"
|
|
bitfld.long 0x00 0.--1. " SEM ,Flash Semaphore Bit" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x08)++0x03
|
|
line.long 0x00 "SECTSTAT1,Flash Sectors Status Register 1"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CPU1 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CPU1 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CPU1 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CPU1 BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CPU1 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CPU1 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CPU1 BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CPU1 BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CPU1 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CPU1 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CPU1 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CPU1 BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CPU1 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CPU1 BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x0A)++0x03
|
|
line.long 0x00 "SECTSTAT2,Flash Sectors Status Register 2"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CM BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CM BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CM BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CM BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CM BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CM BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CM BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CM BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CM BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CM BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CM BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CM BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CM BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CM BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x0C)++0x03
|
|
line.long 0x00 "SECTSTAT3,Flash Sectors Status Register 3"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CPU2 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CPU2 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CPU2 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CPU2 BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CPU2 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CPU2 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CPU2 BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CPU2 BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CPU2 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CPU2 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CPU2 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CPU2 BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CPU2 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CPU2 BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x10)++0x03
|
|
line.long 0x00 "RAMSTAT1,RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_RAM3 ,Zone Status RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_RAM2 ,Zone Status RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x12)++0x03
|
|
line.long 0x00 "RAMSTAT2,RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " STATUS_RAM15 ,Zone Status RAM CPU2 to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " STATUS_RAM14 ,Zone Status RAM CPU2 to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " STATUS_RAM13 ,Zone Status RAM CPU1 to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_RAM12 ,Zone Status RAM CPU1 to CPU2 MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " STATUS_RAM11 ,Zone Status RAM CM to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_RAM10 ,Zone Status RAM CM to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU2 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU2 to CM MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CM to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CM to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU1 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU1 to CM MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x14)++0x03
|
|
line.long 0x00 "RAMSTAT3,RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_RAM3 ,Zone Status RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_RAM2 ,Zone Status RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F0C0+0x18)++0x03
|
|
line.long 0x00 "SECERRSTAT,Security Error Status Register"
|
|
bitfld.long 0x00 0. " ERR ,Security Configuration load Error Status" "0,1"
|
|
group.long (d:0x0005F0C0+0x1A)++0x03
|
|
line.long 0x00 "SECERRCLR,Security Error Clear Register"
|
|
bitfld.long 0x00 0. " ERR ,Clear Security Configuration Load Error Status Bit" "0,1"
|
|
group.long (d:0x0005F0C0+0x1C)++0x03
|
|
line.long 0x00 "SECERRFRC,Security Error Force Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Valid Register Write Key"
|
|
bitfld.long 0x00 0. " ERR ,Set Security Configuration Load Error Status Bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Zone 1"
|
|
width 19.
|
|
rgroup.long (d:0x0005F000+0x00)++0x03
|
|
line.long 0x00 "Z1_LINKPOINTER,Zone 1 Link Pointer"
|
|
hexmask.long 0x00 0.--13. 1. "LINKPOINTER,Zone1 LINK Pointer"
|
|
rgroup.long (d:0x0005F000+0x02)++0x03
|
|
line.long 0x00 "Z1_OTPSECLOCK,Zone 1 OTP Secure Lock"
|
|
bitfld.long 0x00 8.--11. " CRCLOCK ,Zone1 CRC Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PSWDLOCK ,Zone1 Password Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " JTAGLOCK ,JTAG Lock Status" "0,1"
|
|
rgroup.long (d:0x0005F000+0x04)++0x03
|
|
line.long 0x00 "Z1_JLM_ENABLE,Zone 1 JTAGLOCK Enable Register"
|
|
bitfld.long 0x00 0.--3. " Z1_JLM_ENABLE ,Zone1 JLM_ENABLE register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x0005F000+0x06)++0x03
|
|
line.long 0x00 "Z1_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long 0x00 0.--13. 1. "Z1_LINKPOINTERERR,Error to Resolve Z1 Link pointer from OTP loaded values"
|
|
rgroup.long (d:0x0005F000+0x08)++0x03
|
|
line.long 0x00 "Z1_GPREG1,Zone 1 General Purpose Register-1"
|
|
rgroup.long (d:0x0005F000+0x0A)++0x03
|
|
line.long 0x00 "Z1_GPREG2,Zone 1 General Purpose Register-2"
|
|
rgroup.long (d:0x0005F000+0x0C)++0x03
|
|
line.long 0x00 "Z1_GPREG3,Zone 1 General Purpose Register-3"
|
|
rgroup.long (d:0x0005F000+0x0E)++0x03
|
|
line.long 0x00 "Z1_GPREG4,Zone 1 General Purpose Register-4"
|
|
group.long (d:0x0005F000+0x10)++0x03
|
|
line.long 0x00 "Z1_CSMKEY0,Zone 1 CSM Key 0"
|
|
group.long (d:0x0005F000+0x12)++0x03
|
|
line.long 0x00 "Z1_CSMKEY1,Zone 1 CSM Key 1"
|
|
group.long (d:0x0005F000+0x14)++0x03
|
|
line.long 0x00 "Z1_CSMKEY2,Zone 1 CSM Key 2"
|
|
group.long (d:0x0005F000+0x16)++0x03
|
|
line.long 0x00 "Z1_CSMKEY3,Zone 1 CSM Key 3"
|
|
group.long (d:0x0005F000+0x18)++0x03
|
|
line.long 0x00 "Z1_CR,Zone 1 CSM Control Register"
|
|
bitfld.long 0x00 31. " FORCESEC ,Force Secure" "0,1"
|
|
rbitfld.long 0x00 22. " ARMED ,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x00 21. " UNSECURE ,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x00 20. " ALLONE ,CSMPSWD All Ones" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. " ALLZERO ,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long (d:0x0005F000+0x1A)++0x03
|
|
line.long 0x00 "Z1_GRABSECT1R,Zone 1 Grab Flash Status Register 1"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x1C)++0x03
|
|
line.long 0x00 "Z1_GRABSECT2R,Zone 1 Grab Flash Status Register 2"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x1E)++0x03
|
|
line.long 0x00 "Z1_GRABSECT3R,Zone 1 Grab Flash Status Register 3"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x20)++0x03
|
|
line.long 0x00 "Z1_GRABRAM1R,Zone 1 Grab RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x22)++0x03
|
|
line.long 0x00 "Z1_GRABRAM2R,Zone 1 Grab RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " GRAB_RAM15 ,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GRAB_RAM14 ,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GRAB_RAM13 ,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_RAM12 ,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GRAB_RAM11 ,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_RAM10 ,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x24)++0x03
|
|
line.long 0x00 "Z1_GRABRAM3R,Zone 1 Grab RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F000+0x26)++0x03
|
|
line.long 0x00 "Z1_EXEONLYSECT1R,Zone 1 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x00 29. " EXEONLY_CM_SECT13 ,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_CM_SECT12 ,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 27. " EXEONLY_CM_SECT11 ,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_CM_SECT10 ,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " EXEONLY_CM_SECT9 ,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_CM_SECT8 ,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 23. " EXEONLY_CM_SECT7 ,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_CM_SECT6 ,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " EXEONLY_CM_SECT5 ,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 20. " EXEONLY_CM_SECT4 ,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 19. " EXEONLY_CM_SECT3 ,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 18. " EXEONLY_CM_SECT2 ,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " EXEONLY_CM_SECT1 ,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_CM_SECT0 ,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU1_SECT13 ,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU1_SECT12 ,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EXEONLY_CPU1_SECT11 ,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU1_SECT10 ,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 9. " EXEONLY_CPU1_SECT9 ,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU1_SECT8 ,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EXEONLY_CPU1_SECT7 ,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU1_SECT6 ,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 5. " EXEONLY_CPU1_SECT5 ,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU1_SECT4 ,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EXEONLY_CPU1_SECT3 ,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU1_SECT2 ,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 1. " EXEONLY_CPU1_SECT1 ,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU1_SECT0 ,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
rgroup.long (d:0x0005F000+0x28)++0x03
|
|
line.long 0x00 "Z1_EXEONLYSECT2R,Zone 1 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU2_SECT13 ,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU2_SECT12 ,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 11. " EXEONLY_CPU2_SECT11 ,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU2_SECT10 ,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_CPU2_SECT9 ,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU2_SECT8 ,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_CPU2_SECT7 ,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU2_SECT6 ,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_CPU2_SECT5 ,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU2_SECT4 ,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_CPU2_SECT3 ,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU2_SECT2 ,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_CPU2_SECT1 ,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU2_SECT0 ,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
rgroup.long (d:0x0005F000+0x2A)++0x03
|
|
line.long 0x00 "Z1_EXEONLYRAM1R,Zone 1 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x00 31. " EXEONLY_RAM31 ,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x00 30. " EXEONLY_RAM30 ,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x00 29. " EXEONLY_RAM29 ,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_RAM28 ,Execute-Only RAM CPU2.LS3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " EXEONLY_RAM27 ,Execute-Only RAM CPU2.LS4" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_RAM26 ,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x00 25. " EXEONLY_RAM25 ,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_RAM24 ,Execute-Only RAM CPU2.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " EXEONLY_RAM23 ,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_RAM22 ,Execute-Only RAM CPU2.D1" "0,1"
|
|
bitfld.long 0x00 17. " EXEONLY_RAM17 ,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_RAM16 ,Execute-Only RAM on CM.C0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_RAM9 ,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_RAM8 ,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_RAM7 ,Execute-Only RAM CPU1.LS7" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_RAM6 ,Execute-Only RAM CPU1.LS6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_RAM5 ,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_RAM4 ,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_RAM3 ,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_RAM2 ,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_RAM1 ,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_RAM0 ,Execute-Only RAM CPU1.LS0" "0,1"
|
|
rgroup.long (d:0x0005F000+0x2E)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY0,JTAG Unlock Key Register 0"
|
|
rgroup.long (d:0x0005F000+0x30)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY1,JTAG Unlock Key Register 1"
|
|
rgroup.long (d:0x0005F000+0x32)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY2,JTAG Unlock Key Register 2"
|
|
rgroup.long (d:0x0005F000+0x34)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY3,JTAG Unlock Key Register 3"
|
|
rgroup.long (d:0x0005F000+0x36)++0x03
|
|
line.long 0x00 "Z1_CMACKEY0,Secure Boot CMAC Key Status Register 0"
|
|
rgroup.long (d:0x0005F000+0x38)++0x03
|
|
line.long 0x00 "Z1_CMACKEY1,Secure Boot CMAC Key Status Register 1"
|
|
rgroup.long (d:0x0005F000+0x3A)++0x03
|
|
line.long 0x00 "Z1_CMACKEY2,Secure Boot CMAC Key Status Register 2"
|
|
rgroup.long (d:0x0005F000+0x3C)++0x03
|
|
line.long 0x00 "Z1_CMACKEY3,Secure Boot CMAC Key Status Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Zone 2"
|
|
width 19.
|
|
rgroup.long (d:0x0005F080+0x00)++0x03
|
|
line.long 0x00 "Z2_LINKPOINTER,Zone 2 Link Pointer"
|
|
hexmask.long 0x00 0.--13. 1. "LINKPOINTER,Zone2 LINK Pointer"
|
|
rgroup.long (d:0x0005F080+0x02)++0x03
|
|
line.long 0x00 "Z2_OTPSECLOCK,Zone 2 OTP Secure Lock"
|
|
bitfld.long 0x00 8.--11. " CRCLOCK ,Zone2 CRC Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PSWDLOCK ,Zone2 Password Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " JTAGLOCK ,JTAG Lock Status" "0,1"
|
|
rgroup.long (d:0x0005F080+0x06)++0x03
|
|
line.long 0x00 "Z2_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long 0x00 0.--13. 1. "Z2_LINKPOINTERERR,Error to Resolve Z2 Link pointer from OTP loaded values"
|
|
rgroup.long (d:0x0005F080+0x08)++0x03
|
|
line.long 0x00 "Z2_GPREG1,Zone 2 General Purpose Register-1"
|
|
rgroup.long (d:0x0005F080+0x0A)++0x03
|
|
line.long 0x00 "Z2_GPREG2,Zone 2 General Purpose Register-2"
|
|
rgroup.long (d:0x0005F080+0x0C)++0x03
|
|
line.long 0x00 "Z2_GPREG3,Zone 2 General Purpose Register-3"
|
|
rgroup.long (d:0x0005F080+0x0E)++0x03
|
|
line.long 0x00 "Z2_GPREG4,Zone 2 General Purpose Register-4"
|
|
group.long (d:0x0005F080+0x10)++0x03
|
|
line.long 0x00 "Z2_CSMKEY0,Zone 2 CSM Key 0"
|
|
group.long (d:0x0005F080+0x12)++0x03
|
|
line.long 0x00 "Z2_CSMKEY1,Zone 2 CSM Key 1"
|
|
group.long (d:0x0005F080+0x14)++0x03
|
|
line.long 0x00 "Z2_CSMKEY2,Zone 2 CSM Key 2"
|
|
group.long (d:0x0005F080+0x16)++0x03
|
|
line.long 0x00 "Z2_CSMKEY3,Zone 2 CSM Key 3"
|
|
group.long (d:0x0005F080+0x18)++0x03
|
|
line.long 0x00 "Z2_CR,Zone 2 CSM Control Register"
|
|
bitfld.long 0x00 31. " FORCESEC ,Force Secure" "0,1"
|
|
rbitfld.long 0x00 22. " ARMED ,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x00 21. " UNSECURE ,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x00 20. " ALLONE ,CSMPSWD All Ones" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. " ALLZERO ,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long (d:0x0005F080+0x1A)++0x03
|
|
line.long 0x00 "Z2_GRABSECT1R,Zone 2 Grab Flash Status Register 1"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x1C)++0x03
|
|
line.long 0x00 "Z2_GRABSECT2R,Zone 2 Grab Flash Status Register 2"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x1E)++0x03
|
|
line.long 0x00 "Z2_GRABSECT3R,Zone 2 Grab Flash Status Register 3"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x20)++0x03
|
|
line.long 0x00 "Z2_GRABRAM1R,Zone 2 Grab RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x22)++0x03
|
|
line.long 0x00 "Z2_GRABRAM2R,Zone 2 Grab RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " GRAB_RAM15 ,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GRAB_RAM14 ,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GRAB_RAM13 ,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_RAM12 ,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GRAB_RAM11 ,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_RAM10 ,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x24)++0x03
|
|
line.long 0x00 "Z2_GRABRAM3R,Zone 2 Grab RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x0005F080+0x26)++0x03
|
|
line.long 0x00 "Z2_EXEONLYSECT1R,Zone 2 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x00 29. " EXEONLY_CM_SECT13 ,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_CM_SECT12 ,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 27. " EXEONLY_CM_SECT11 ,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_CM_SECT10 ,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " EXEONLY_CM_SECT9 ,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_CM_SECT8 ,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 23. " EXEONLY_CM_SECT7 ,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_CM_SECT6 ,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " EXEONLY_CM_SECT5 ,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 20. " EXEONLY_CM_SECT4 ,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 19. " EXEONLY_CM_SECT3 ,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 18. " EXEONLY_CM_SECT2 ,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " EXEONLY_CM_SECT1 ,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_CM_SECT0 ,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU1_SECT13 ,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU1_SECT12 ,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EXEONLY_CPU1_SECT11 ,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU1_SECT10 ,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 9. " EXEONLY_CPU1_SECT9 ,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU1_SECT8 ,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EXEONLY_CPU1_SECT7 ,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU1_SECT6 ,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 5. " EXEONLY_CPU1_SECT5 ,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU1_SECT4 ,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EXEONLY_CPU1_SECT3 ,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU1_SECT2 ,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 1. " EXEONLY_CPU1_SECT1 ,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU1_SECT0 ,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
rgroup.long (d:0x0005F080+0x28)++0x03
|
|
line.long 0x00 "Z2_EXEONLYSECT2R,Zone 2 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU2_SECT13 ,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU2_SECT12 ,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 11. " EXEONLY_CPU2_SECT11 ,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU2_SECT10 ,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_CPU2_SECT9 ,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU2_SECT8 ,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_CPU2_SECT7 ,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU2_SECT6 ,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_CPU2_SECT5 ,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU2_SECT4 ,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_CPU2_SECT3 ,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU2_SECT2 ,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_CPU2_SECT1 ,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU2_SECT0 ,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
rgroup.long (d:0x0005F080+0x2A)++0x03
|
|
line.long 0x00 "Z2_EXEONLYRAM1R,Zone 2 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x00 31. " EXEONLY_RAM31 ,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x00 30. " EXEONLY_RAM30 ,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x00 29. " EXEONLY_RAM29 ,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_RAM28 ,Execute-Only RAM CPU2.LS3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " EXEONLY_RAM27 ,Execute-Only RAM CPU2.LS4" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_RAM26 ,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x00 25. " EXEONLY_RAM25 ,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_RAM24 ,Execute-Only RAM CPU2.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " EXEONLY_RAM23 ,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_RAM22 ,Execute-Only RAM CPU2.D1" "0,1"
|
|
bitfld.long 0x00 17. " EXEONLY_RAM17 ,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_RAM16 ,Execute-Only RAM on CM.C0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_RAM9 ,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_RAM8 ,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_RAM7 ,Execute-Only RAM CPU1.LS7" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_RAM6 ,Execute-Only RAM CPU1.LS6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_RAM5 ,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_RAM4 ,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_RAM3 ,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_RAM2 ,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_RAM1 ,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_RAM0 ,Execute-Only RAM CPU1.LS0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Direct Memory Access (DMA)"
|
|
tree "DmaRegs"
|
|
width 15.
|
|
group.word (d:0x00001000+0x00)++0x01
|
|
line.word 0x00 "DMACTRL,DMA Control Register"
|
|
bitfld.word 0x00 1. " PRIORITYRESET ,Priority Reset Bit" "0,1"
|
|
bitfld.word 0x00 0. " HARDRESET ,Hard Reset Bit" "0,1"
|
|
group.word (d:0x00001000+0x01)++0x01
|
|
line.word 0x00 "DEBUGCTRL,Debug Control Register"
|
|
bitfld.word 0x00 15. " FREE ,Debug Mode Bit" "0,1"
|
|
group.word (d:0x00001000+0x04)++0x01
|
|
line.word 0x00 "PRIORITYCTRL1,Priority Control 1 Register"
|
|
bitfld.word 0x00 0. " CH1PRIORITY ,Ch1 Priority Bit" "0,1"
|
|
rgroup.word (d:0x00001000+0x06)++0x01
|
|
line.word 0x00 "PRIORITYSTAT,Priority Status Register"
|
|
bitfld.word 0x00 4.--6. " ACTIVESTS_SHADOW ,Active Channel Status Shadow Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " ACTIVESTS ,Active Channel Status Bits" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 21.
|
|
group.word (d:0x00001020+0x0)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x0+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0x0+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0x0+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x0+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0x0+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0x0+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0x0+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0x0+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0x0+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0x0+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0x0+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0x0+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0x0+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0x0+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0x0+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0x0+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x0+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0x0+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0x0+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0x0+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x0+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0x0+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0x0+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 21.
|
|
group.word (d:0x00001020+0x20)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x20+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0x20+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0x20+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x20+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0x20+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0x20+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0x20+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0x20+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0x20+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0x20+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0x20+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0x20+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0x20+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0x20+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0x20+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0x20+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x20+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0x20+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0x20+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0x20+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x20+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0x20+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0x20+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 21.
|
|
group.word (d:0x00001020+0x40)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x40+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0x40+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0x40+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x40+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0x40+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0x40+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0x40+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0x40+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0x40+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0x40+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0x40+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0x40+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0x40+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0x40+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0x40+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0x40+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x40+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0x40+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0x40+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0x40+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x40+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0x40+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0x40+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
width 21.
|
|
group.word (d:0x00001020+0x60)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x60+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0x60+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0x60+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x60+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0x60+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0x60+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0x60+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0x60+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0x60+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0x60+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0x60+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0x60+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0x60+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0x60+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0x60+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0x60+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x60+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0x60+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0x60+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0x60+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x60+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0x60+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0x60+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
width 21.
|
|
group.word (d:0x00001020+0x80)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x80+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0x80+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0x80+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0x80+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0x80+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0x80+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0x80+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0x80+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0x80+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0x80+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0x80+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0x80+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0x80+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0x80+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0x80+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0x80+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x80+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0x80+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0x80+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0x80+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0x80+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0x80+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0x80+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6"
|
|
width 21.
|
|
group.word (d:0x00001020+0xA0)++0x01
|
|
line.word 0x00 "MODE,Mode Register"
|
|
bitfld.word 0x00 15. " CHINTE ,Channel Interrupt Enable Bit" "0,1"
|
|
bitfld.word 0x00 14. " DATASIZE ,Data Size Mode Bit" "0,1"
|
|
bitfld.word 0x00 11. " CONTINUOUS ,Continuous Mode Bit" "0,1"
|
|
bitfld.word 0x00 10. " ONESHOT ,One Shot Mode Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CHINTMODE ,Channel Interrupt Mode" "0,1"
|
|
bitfld.word 0x00 8. " PERINTE ,Peripheral Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 7. " OVRINTE ,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " PERINTSEL ,Peripheral Interrupt and Sync Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0xA0+0x01)++0x01
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
rbitfld.word 0x00 14. " OVRFLG ,Overflow Flag Bit" "0,1"
|
|
rbitfld.word 0x00 13. " RUNSTS ,Run Status Bit" "0,1"
|
|
rbitfld.word 0x00 12. " BURSTSTS ,Burst Status Bit" "0,1"
|
|
rbitfld.word 0x00 11. " TRANSFERSTS ,Transfer Status Bit" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 8. " PERINTFLG ,Interrupt Flag Bit" "0,1"
|
|
bitfld.word 0x00 7. " ERRCLR ,Error Clear Bit" "0,1"
|
|
bitfld.word 0x00 4. " PERINTCLR ,Interrupt Clear Bit" "0,1"
|
|
bitfld.word 0x00 3. " PERINTFRC ,Interrupt Force Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " SOFTRESET ,Soft Reset Bit" "0,1"
|
|
bitfld.word 0x00 1. " HALT ,Halt Bit" "0,1"
|
|
bitfld.word 0x00 0. " RUN ,Run Bit" "0,1"
|
|
group.word (d:0x00001020+0xA0+0x02)++0x01
|
|
line.word 0x00 "BURST_SIZE,Burst Size Register"
|
|
bitfld.word 0x00 0.--4. " BURSTSIZE ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word (d:0x00001020+0xA0+0x03)++0x01
|
|
line.word 0x00 "BURST_COUNT,Burst Count Register"
|
|
bitfld.word 0x00 0.--4. " BURSTCOUNT ,Burst Transfer Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00001020+0xA0+0x04)++0x01
|
|
line.word 0x00 "SRC_BURST_STEP,Source Burst Step Register"
|
|
group.word (d:0x00001020+0xA0+0x05)++0x01
|
|
line.word 0x00 "DST_BURST_STEP,Destination Burst Step Register"
|
|
group.word (d:0x00001020+0xA0+0x06)++0x01
|
|
line.word 0x00 "TRANSFER_SIZE,Transfer Size Register"
|
|
group.word (d:0x00001020+0xA0+0x07)++0x01
|
|
line.word 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
group.word (d:0x00001020+0xA0+0x08)++0x01
|
|
line.word 0x00 "SRC_TRANSFER_STEP,Source Transfer Step Register"
|
|
group.word (d:0x00001020+0xA0+0x09)++0x01
|
|
line.word 0x00 "DST_TRANSFER_STEP,Destination Transfer Step Register"
|
|
group.word (d:0x00001020+0xA0+0x0A)++0x01
|
|
line.word 0x00 "SRC_WRAP_SIZE,Source Wrap Size Register"
|
|
group.word (d:0x00001020+0xA0+0x0B)++0x01
|
|
line.word 0x00 "SRC_WRAP_COUNT,Source Wrap Count Register"
|
|
group.word (d:0x00001020+0xA0+0x0C)++0x01
|
|
line.word 0x00 "SRC_WRAP_STEP,Source Wrap Step Register"
|
|
group.word (d:0x00001020+0xA0+0x0D)++0x01
|
|
line.word 0x00 "DST_WRAP_SIZE,Destination Wrap Size Register"
|
|
group.word (d:0x00001020+0xA0+0x0E)++0x01
|
|
line.word 0x00 "DST_WRAP_COUNT,Destination Wrap Count Register"
|
|
group.word (d:0x00001020+0xA0+0x0F)++0x01
|
|
line.word 0x00 "DST_WRAP_STEP,Destination Wrap Step Register"
|
|
group.long (d:0x00001020+0xA0+0x10)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_SHADOW,Source Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0xA0+0x12)++0x03
|
|
line.long 0x00 "SRC_ADDR_SHADOW,Source Address Shadow Register"
|
|
group.long (d:0x00001020+0xA0+0x14)++0x03
|
|
line.long 0x00 "SRC_BEG_ADDR_ACTIVE,Source Begin Address Active Register"
|
|
group.long (d:0x00001020+0xA0+0x16)++0x03
|
|
line.long 0x00 "SRC_ADDR_ACTIVE,Source Address Active Register"
|
|
group.long (d:0x00001020+0xA0+0x18)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_SHADOW,Destination Begin Address Shadow Register"
|
|
group.long (d:0x00001020+0xA0+0x1A)++0x03
|
|
line.long 0x00 "DST_ADDR_SHADOW,Destination Address Shadow Register"
|
|
group.long (d:0x00001020+0xA0+0x1C)++0x03
|
|
line.long 0x00 "DST_BEG_ADDR_ACTIVE,Destination Begin Address Active Register"
|
|
group.long (d:0x00001020+0xA0+0x1E)++0x03
|
|
line.long 0x00 "DST_ADDR_ACTIVE,Destination Address Active Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Enhanced Capture (ECap)"
|
|
tree "Channel 1"
|
|
width 15.
|
|
group.long (d:0x00005200+0x0)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0x0+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0x0+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0x0+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0x0+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0x0+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0x0+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0x0+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0x0+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0x0+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0x0+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0x0+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0x0+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0x0+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 15.
|
|
group.long (d:0x00005200+0x20)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0x20+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0x20+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0x20+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0x20+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0x20+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0x20+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0x20+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0x20+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0x20+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0x20+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0x20+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0x20+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0x20+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 15.
|
|
group.long (d:0x00005200+0x40)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0x40+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0x40+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0x40+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0x40+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0x40+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0x40+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0x40+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0x40+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0x40+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0x40+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0x40+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0x40+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0x40+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
width 15.
|
|
group.long (d:0x00005200+0x60)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0x60+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0x60+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0x60+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0x60+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0x60+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0x60+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0x60+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0x60+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0x60+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0x60+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0x60+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0x60+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0x60+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
width 15.
|
|
group.long (d:0x00005200+0x80)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0x80+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0x80+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0x80+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0x80+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0x80+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0x80+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0x80+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0x80+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0x80+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0x80+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0x80+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0x80+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0x80+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6"
|
|
width 15.
|
|
group.long (d:0x00005200+0xA0)++0x03
|
|
line.long 0x00 "TSCTR,Time-Stamp Counter"
|
|
group.long (d:0x00005200+0xA0+0x02)++0x03
|
|
line.long 0x00 "CTRPHS,Counter Phase Offset Value Register"
|
|
group.long (d:0x00005200+0xA0+0x04)++0x03
|
|
line.long 0x00 "CAP1,Capture 1 Register"
|
|
group.long (d:0x00005200+0xA0+0x06)++0x03
|
|
line.long 0x00 "CAP2,Capture 2 Register"
|
|
group.long (d:0x00005200+0xA0+0x08)++0x03
|
|
line.long 0x00 "CAP3,Capture 3 Register"
|
|
group.long (d:0x00005200+0xA0+0x0A)++0x03
|
|
line.long 0x00 "CAP4,Capture 4 Register"
|
|
group.long (d:0x00005200+0xA0+0x12)++0x03
|
|
line.long 0x00 "ECCTL0,Capture Control Register 0"
|
|
bitfld.long 0x00 0.--6. " INPUTSEL ,INPUT source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00005200+0xA0+0x14)++0x01
|
|
line.word 0x00 "ECCTL1,Capture Control Register 1"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " CAPLDEN ,Enable Loading CAP1-4 regs on a Cap Event" "0,1"
|
|
bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "0,1"
|
|
bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "0,1"
|
|
bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "0,1"
|
|
bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "0,1"
|
|
bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "0,1"
|
|
bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "0,1"
|
|
group.word (d:0x00005200+0xA0+0x15)++0x01
|
|
line.word 0x00 "ECCTL2,Capture Control Register 2"
|
|
rbitfld.word 0x00 14.--15. " MODCNTRSTS ,modulo counter status" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " DMAEVTSEL ,DMA event select" "0,1,2,3"
|
|
bitfld.word 0x00 11. " CTRFILTRESET ,Reset event filter, modulus counter, and interrupt flags." "0,1"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "0,1"
|
|
bitfld.word 0x00 8. " SWSYNC ,SW forced counter sync" "0,1"
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out mode" "0,1,2,3"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,TSCNT counter stop" "0,1"
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arm" "0,1"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot, Wrap for continuous" "0,1,2,3"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot" "0,1"
|
|
group.word (d:0x00005200+0xA0+0x16)++0x01
|
|
line.word 0x00 "ECEINT,Capture Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_EQ_CMP ,Compare Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 6. " CTR_EQ_PRD ,Period Equal Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "0,1"
|
|
rgroup.word (d:0x00005200+0xA0+0x17)++0x01
|
|
line.word 0x00 "ECFLG,Capture Interrupt Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Flag" "0,1"
|
|
group.word (d:0x00005200+0xA0+0x18)++0x01
|
|
line.word 0x00 "ECCLR,Capture Interrupt Clear Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Status Clear" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Status Clear" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Clear" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Clear" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,ECAP Global Interrupt Status Clear" "0,1"
|
|
group.word (d:0x00005200+0xA0+0x19)++0x01
|
|
line.word 0x00 "ECFRC,Capture Interrupt Force Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Compare Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Period Equal Force Interrupt" "0,1"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter Overflow Force Interrupt" "0,1"
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Force Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Force Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Force Interrupt" "0,1"
|
|
group.long (d:0x00005200+0xA0+0x1E)++0x03
|
|
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
|
|
bitfld.long 0x00 0.--4. " SEL ,SYNCIN source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "High Resolution Capture (HRCAP)"
|
|
tree "Submodule 6"
|
|
width 13.
|
|
group.long (d:0x00005360+0x00)++0x03
|
|
line.long 0x00 "HRCTL,High-Res Control Register"
|
|
bitfld.long 0x00 5. " CALIBCONT ,Continuous mode Calibration Select" "0,1"
|
|
rbitfld.long 0x00 4. " CALIBSTS ,Calibration status" "0,1"
|
|
bitfld.long 0x00 3. " CALIBSTART ,Calibration start" "0,1"
|
|
bitfld.long 0x00 2. " PRDSEL ,Calibration Period Match" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " HRCLKE ,High Resolution Clock Enable" "0,1"
|
|
bitfld.long 0x00 0. " HRE ,High Resolution Enable" "0,1"
|
|
group.long (d:0x00005360+0x04)++0x03
|
|
line.long 0x00 "HRINTEN,High-Res Calibration Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Calibration period check status enable" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Calibration doe interrupt enable" "0,1"
|
|
rgroup.long (d:0x00005360+0x06)++0x03
|
|
line.long 0x00 "HRFLG,High-Res Calibration Interrupt Flag Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Calibration period check status Flag Bi" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x00 0. " CALIBINT ,Global calibration Interrupt Status Flag" "0,1"
|
|
group.long (d:0x00005360+0x08)++0x03
|
|
line.long 0x00 "HRCLR,High-Res Calibration Interrupt Clear Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Clear Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Clear Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x00 0. " CALIBINT ,Clear Global calibration Interrupt Flag" "0,1"
|
|
group.long (d:0x00005360+0x0A)++0x03
|
|
line.long 0x00 "HRFRC,High-Res Calibration Interrupt Force Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Force Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Force Calibration Done Interrupt Flag Bit" "0,1"
|
|
group.long (d:0x00005360+0x0C)++0x03
|
|
line.long 0x00 "HRCALPRD,High-Res Calibration Period Register"
|
|
rgroup.long (d:0x00005360+0x0E)++0x03
|
|
line.long 0x00 "HRSYSCLKCTR,High-Res Calibration SYSCLK Counter Register"
|
|
rgroup.long (d:0x00005360+0x10)++0x03
|
|
line.long 0x00 "HRSYSCLKCAP,High-Res Calibration SYSCLK Capture Register"
|
|
rgroup.long (d:0x00005360+0x12)++0x03
|
|
line.long 0x00 "HRCLKCTR,High-Res Calibration HRCLK Counter Register"
|
|
rgroup.long (d:0x00005360+0x14)++0x03
|
|
line.long 0x00 "HRCLKCAP,High-Res Calibration HRCLK Capture Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 7"
|
|
width 13.
|
|
group.long (d:0x000053A0+0x00)++0x03
|
|
line.long 0x00 "HRCTL,High-Res Control Register"
|
|
bitfld.long 0x00 5. " CALIBCONT ,Continuous mode Calibration Select" "0,1"
|
|
rbitfld.long 0x00 4. " CALIBSTS ,Calibration status" "0,1"
|
|
bitfld.long 0x00 3. " CALIBSTART ,Calibration start" "0,1"
|
|
bitfld.long 0x00 2. " PRDSEL ,Calibration Period Match" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " HRCLKE ,High Resolution Clock Enable" "0,1"
|
|
bitfld.long 0x00 0. " HRE ,High Resolution Enable" "0,1"
|
|
group.long (d:0x000053A0+0x04)++0x03
|
|
line.long 0x00 "HRINTEN,High-Res Calibration Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Calibration period check status enable" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Calibration doe interrupt enable" "0,1"
|
|
rgroup.long (d:0x000053A0+0x06)++0x03
|
|
line.long 0x00 "HRFLG,High-Res Calibration Interrupt Flag Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Calibration period check status Flag Bi" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x00 0. " CALIBINT ,Global calibration Interrupt Status Flag" "0,1"
|
|
group.long (d:0x000053A0+0x08)++0x03
|
|
line.long 0x00 "HRCLR,High-Res Calibration Interrupt Clear Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Clear Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Clear Calibration Done Interrupt Flag Bit" "0,1"
|
|
bitfld.long 0x00 0. " CALIBINT ,Clear Global calibration Interrupt Flag" "0,1"
|
|
group.long (d:0x000053A0+0x0A)++0x03
|
|
line.long 0x00 "HRFRC,High-Res Calibration Interrupt Force Register"
|
|
bitfld.long 0x00 2. " CALPRDCHKSTS ,Force Calibration period check status Flag Bit" "0,1"
|
|
bitfld.long 0x00 1. " CALIBDONE ,Force Calibration Done Interrupt Flag Bit" "0,1"
|
|
group.long (d:0x000053A0+0x0C)++0x03
|
|
line.long 0x00 "HRCALPRD,High-Res Calibration Period Register"
|
|
rgroup.long (d:0x000053A0+0x0E)++0x03
|
|
line.long 0x00 "HRSYSCLKCTR,High-Res Calibration SYSCLK Counter Register"
|
|
rgroup.long (d:0x000053A0+0x10)++0x03
|
|
line.long 0x00 "HRSYSCLKCAP,High-Res Calibration SYSCLK Capture Register"
|
|
rgroup.long (d:0x000053A0+0x12)++0x03
|
|
line.long 0x00 "HRCLKCTR,High-Res Calibration HRCLK Counter Register"
|
|
rgroup.long (d:0x000053A0+0x14)++0x03
|
|
line.long 0x00 "HRCLKCAP,High-Res Calibration HRCLK Capture Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "External Memory Interface (EMIF)"
|
|
tree "EMIF 1 Configuration"
|
|
width 15.
|
|
group.long (d:0x0005F4C0+0x00)++0x03
|
|
line.long 0x00 "EMIF1LOCK,EMIF1 Config Lock Register"
|
|
bitfld.long 0x00 0. " LOCK_EMIF1 ,EMIF1 access protection and master select fields lock bit" "0,1"
|
|
group.long (d:0x0005F4C0+0x02)++0x03
|
|
line.long 0x00 "EMIF1COMMIT,EMIF1 Config Lock Commit Register"
|
|
bitfld.long 0x00 0. " COMMIT_EMIF1 ,EMIF1 access protection and master select permanent lock" "0,1"
|
|
group.long (d:0x0005F4C0+0x04)++0x03
|
|
line.long 0x00 "EMIF1MSEL,EMIF1 Master Sel Register"
|
|
hexmask.long 0x00 4.--31. 1. "KEY,KEY to enable the write into MSEL_EMIF1 bits"
|
|
bitfld.long 0x00 0.--1. " MSEL_EMIF1 ,Master Select for EMIF1." "0,1,2,3"
|
|
group.long (d:0x0005F4C0+0x08)++0x03
|
|
line.long 0x00 "EMIF1ACCPROT0,EMIF1 Config Register 0"
|
|
bitfld.long 0x00 2. " DMAWRPROT_EMIF1 ,DMA WR Protection For EMIF1" "0,1"
|
|
bitfld.long 0x00 1. " CPUWRPROT_EMIF1 ,CPU WR Protection For EMIF1" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_EMIF1 ,Fetch Protection For EMIF1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMIF 2 Configuration"
|
|
width 15.
|
|
group.long (d:0x0005F4E0+0x00)++0x03
|
|
line.long 0x00 "EMIF2LOCK,EMIF2 Config Lock Register"
|
|
bitfld.long 0x00 0. " LOCK_EMIF2 ,EMIF2 access protection and master select permanent lock" "0,1"
|
|
group.long (d:0x0005F4E0+0x02)++0x03
|
|
line.long 0x00 "EMIF2COMMIT,EMIF2 Config Lock Commit Register"
|
|
bitfld.long 0x00 0. " COMMIT_EMIF2 ,EMIF2 access protection and master select permanent lock" "0,1"
|
|
group.long (d:0x0005F4E0+0x08)++0x03
|
|
line.long 0x00 "EMIF2ACCPROT0,EMIF2 Config Register 0"
|
|
bitfld.long 0x00 1. " CPUWRPROT_EMIF2 ,CPU WR Protection For EMIF2" "0,1"
|
|
bitfld.long 0x00 0. " FETCHPROT_EMIF2 ,Fetch Protection For EMIF2" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMIF 1"
|
|
width 18.
|
|
rgroup.long (d:0x00047000+0x00)++0x03
|
|
line.long 0x00 "RCSR,Revision Code and Status Register"
|
|
bitfld.long 0x00 31. " BE ,EMIF endian mode." "0,1"
|
|
bitfld.long 0x00 30. " FR ,EMIF is running in full rate or half rate." "0,1"
|
|
hexmask.long 0x00 16.--29. 1. "MODULE_ID,EMIF module ID."
|
|
hexmask.long 0x00 8.--15. 1. "MAJOR_REVISION,Major Revision."
|
|
newline
|
|
hexmask.long 0x00 0.--7. 1. "MINOR_REVISION,Minor Revision."
|
|
group.long (d:0x00047000+0x02)++0x03
|
|
line.long 0x00 "ASYNC_WCCR,Async Wait Cycle Config Register"
|
|
bitfld.long 0x00 28. " WP0 ,Polarity for EMxWAIT." "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MAX_EXT_WAIT,Maximum Extended Wait cycles."
|
|
group.long (d:0x00047000+0x04)++0x03
|
|
line.long 0x00 "SDRAM_CR,SDRAM (EMxCS0n) Config Register"
|
|
bitfld.long 0x00 31. " SR ,Self Refresh." "0,1"
|
|
bitfld.long 0x00 30. " PD ,Power Down." "0,1"
|
|
bitfld.long 0x00 29. " PDWR ,Perform refreshes during Power Down." "0,1"
|
|
bitfld.long 0x00 14. " NM ,Narrow Mode." "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " CL ,CAS Latency." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. " BIT_11_9_LOCK ,Bits 11 to 9 are writable only if this bit is set." "0,1"
|
|
bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup of SDRAM devices." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PAGESIGE ,Page Size." "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00047000+0x06)++0x03
|
|
line.long 0x00 "SDRAM_RCR,SDRAM Refresh Control Register"
|
|
hexmask.long 0x00 0.--12. 1. "REFRESH_RATE,Refresh Rate."
|
|
group.long (d:0x00047000+0x08)++0x03
|
|
line.long 0x00 "ASYNC_CS2_CR,Async 1 (EMxCS2n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047000+0x0A)++0x03
|
|
line.long 0x00 "ASYNC_CS3_CR,Async 2 (EMxCS3n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047000+0x0C)++0x03
|
|
line.long 0x00 "ASYNC_CS4_CR,Async 3 (EMxCS4n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047000+0x10)++0x03
|
|
line.long 0x00 "SDRAM_TR,SDRAM Timing Register"
|
|
bitfld.long 0x00 27.--31. " T_RFC ,Refresh/Load Mode to Refresh/Activate timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " T_RP ,Precharge to Activate/Refresh timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " T_RCD ,Activate to Read/Write timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " T_WR ,Last Write to Precharge timing." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " T_RAS ,Activate to Precharge timing." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " T_RC ,Activate to Activate timing ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " T_RRD ,Activate to Activate timing for different bank." "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x00047000+0x18)++0x03
|
|
line.long 0x00 "TOTAL_SDRAM_AR,Total SDRAM Accesses Register"
|
|
rgroup.long (d:0x00047000+0x1A)++0x03
|
|
line.long 0x00 "TOTAL_SDRAM_ACTR,Total SDRAM Activate Register"
|
|
group.long (d:0x00047000+0x1E)++0x03
|
|
line.long 0x00 "SDR_EXT_TMNG,SDRAM SR/PD Exit Timing Register"
|
|
bitfld.long 0x00 0.--4. " T_XS ,Self Refresh exit to new command timing." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00047000+0x20)++0x03
|
|
line.long 0x00 "INT_RAW,Interrupt Raw Register"
|
|
bitfld.long 0x00 2.--5. " WR ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT ,Asynchronous Timeout." "0,1"
|
|
group.long (d:0x00047000+0x22)++0x03
|
|
line.long 0x00 "INT_MSK,Interrupt Masked Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASKED ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASKED ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASKED ,Asynchronous Timeout." "0,1"
|
|
group.long (d:0x00047000+0x24)++0x03
|
|
line.long 0x00 "INT_MSK_SET,Interrupt Mask Set Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASK_SET ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASK_SET ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASK_SET ,Asynchronous Timeout." "0,1"
|
|
group.long (d:0x00047000+0x26)++0x03
|
|
line.long 0x00 "INT_MSK_CLR,Interrupt Mask Clear Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASK_CLR ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASK_CLR ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASK_CLR ,Asynchronous Timeout." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMIF 2"
|
|
width 18.
|
|
rgroup.long (d:0x00047800+0x00)++0x03
|
|
line.long 0x00 "RCSR,Revision Code and Status Register"
|
|
bitfld.long 0x00 31. " BE ,EMIF endian mode." "0,1"
|
|
bitfld.long 0x00 30. " FR ,EMIF is running in full rate or half rate." "0,1"
|
|
hexmask.long 0x00 16.--29. 1. "MODULE_ID,EMIF module ID."
|
|
hexmask.long 0x00 8.--15. 1. "MAJOR_REVISION,Major Revision."
|
|
newline
|
|
hexmask.long 0x00 0.--7. 1. "MINOR_REVISION,Minor Revision."
|
|
group.long (d:0x00047800+0x02)++0x03
|
|
line.long 0x00 "ASYNC_WCCR,Async Wait Cycle Config Register"
|
|
bitfld.long 0x00 28. " WP0 ,Polarity for EMxWAIT." "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MAX_EXT_WAIT,Maximum Extended Wait cycles."
|
|
group.long (d:0x00047800+0x04)++0x03
|
|
line.long 0x00 "SDRAM_CR,SDRAM (EMxCS0n) Config Register"
|
|
bitfld.long 0x00 31. " SR ,Self Refresh." "0,1"
|
|
bitfld.long 0x00 30. " PD ,Power Down." "0,1"
|
|
bitfld.long 0x00 29. " PDWR ,Perform refreshes during Power Down." "0,1"
|
|
bitfld.long 0x00 14. " NM ,Narrow Mode." "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. " CL ,CAS Latency." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. " BIT_11_9_LOCK ,Bits 11 to 9 are writable only if this bit is set." "0,1"
|
|
bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup of SDRAM devices." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PAGESIGE ,Page Size." "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00047800+0x06)++0x03
|
|
line.long 0x00 "SDRAM_RCR,SDRAM Refresh Control Register"
|
|
hexmask.long 0x00 0.--12. 1. "REFRESH_RATE,Refresh Rate."
|
|
group.long (d:0x00047800+0x08)++0x03
|
|
line.long 0x00 "ASYNC_CS2_CR,Async 1 (EMxCS2n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047800+0x0A)++0x03
|
|
line.long 0x00 "ASYNC_CS3_CR,Async 2 (EMxCS3n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047800+0x0C)++0x03
|
|
line.long 0x00 "ASYNC_CS4_CR,Async 3 (EMxCS4n) Config Register"
|
|
bitfld.long 0x00 31. " SS ,Select Strobe mode." "0,1"
|
|
bitfld.long 0x00 30. " EW ,Extend Wait mode." "0,1"
|
|
bitfld.long 0x00 26.--29. " W_SETUP ,Write Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " W_STROBE ,Write Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " W_HOLD ,Write Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. " R_SETUP ,Read Strobe Setup cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7.--12. " R_STROBE ,Read Strobe Duration cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--6. " R_HOLD ,Read Strobe Hold cycles." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " TA ,Turn Around cycles." "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous Memory Size." "0,1,2,3"
|
|
group.long (d:0x00047800+0x10)++0x03
|
|
line.long 0x00 "SDRAM_TR,SDRAM Timing Register"
|
|
bitfld.long 0x00 27.--31. " T_RFC ,Refresh/Load Mode to Refresh/Activate timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " T_RP ,Precharge to Activate/Refresh timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " T_RCD ,Activate to Read/Write timing." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " T_WR ,Last Write to Precharge timing." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " T_RAS ,Activate to Precharge timing." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " T_RC ,Activate to Activate timing ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " T_RRD ,Activate to Activate timing for different bank." "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x00047800+0x18)++0x03
|
|
line.long 0x00 "TOTAL_SDRAM_AR,Total SDRAM Accesses Register"
|
|
rgroup.long (d:0x00047800+0x1A)++0x03
|
|
line.long 0x00 "TOTAL_SDRAM_ACTR,Total SDRAM Activate Register"
|
|
group.long (d:0x00047800+0x1E)++0x03
|
|
line.long 0x00 "SDR_EXT_TMNG,SDRAM SR/PD Exit Timing Register"
|
|
bitfld.long 0x00 0.--4. " T_XS ,Self Refresh exit to new command timing." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long (d:0x00047800+0x20)++0x03
|
|
line.long 0x00 "INT_RAW,Interrupt Raw Register"
|
|
bitfld.long 0x00 2.--5. " WR ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1. " LT ,Line Trap." "0,1"
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|
bitfld.long 0x00 0. " AT ,Asynchronous Timeout." "0,1"
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group.long (d:0x00047800+0x22)++0x03
|
|
line.long 0x00 "INT_MSK,Interrupt Masked Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASKED ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASKED ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASKED ,Asynchronous Timeout." "0,1"
|
|
group.long (d:0x00047800+0x24)++0x03
|
|
line.long 0x00 "INT_MSK_SET,Interrupt Mask Set Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASK_SET ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASK_SET ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASK_SET ,Asynchronous Timeout." "0,1"
|
|
group.long (d:0x00047800+0x26)++0x03
|
|
line.long 0x00 "INT_MSK_CLR,Interrupt Mask Clear Register"
|
|
bitfld.long 0x00 2.--5. " WR_MASK_CLR ,Wait Rise." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LT_MASK_CLR ,Line Trap." "0,1"
|
|
bitfld.long 0x00 0. " AT_MASK_CLR ,Asynchronous Timeout." "0,1"
|
|
width 0x0B
|
|
tree.end
|
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tree.end
|
|
tree "Enhanced Pulse Width Modulator (ePWM)"
|
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tree "Submodule 1"
|
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width 15.
|
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group.word (d:0x00004000+0x0)++0x01
|
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line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
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bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x01)++0x01
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line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
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bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
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bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x0+0x03)++0x01
|
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line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
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bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x0+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
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group.word (d:0x00004000+0x0+0x05)++0x01
|
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line.word 0x00 "TBSTS,Time Base Status Register"
|
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bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
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bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
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group.word (d:0x00004000+0x0+0x06)++0x01
|
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line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
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bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
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bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
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newline
|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
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bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x0+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x0+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
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bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x0+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x0+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x0+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x0+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x0+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x0+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x0+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x0+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x0+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x0+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x0+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x0+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x0+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x0+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x0+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x0+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x0+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x0+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x0+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0x0+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0x0+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0x0+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x0+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x0+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0x0+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x0+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x0+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x0+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x0+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0x0+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0x0+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0x0+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x0+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0x0+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x0+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x0+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x0+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x0+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x0+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0x0+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x0+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x0+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0x0+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0x0+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
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group.word (d:0x00004000+0x0+0xB4)++0x01
|
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x0+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0x0+0xC3)++0x01
|
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x0+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x0+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x0+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x0+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x0+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x0+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x0+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x0+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x0+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x0+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x0+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x0+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x0+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x0+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x0+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 2"
|
|
width 15.
|
|
group.word (d:0x00004000+0x100)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x100+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x100+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x100+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x100+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x100+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
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|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x100+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x100+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
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|
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bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
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|
group.word (d:0x00004000+0x100+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x100+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
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bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
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|
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
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group.word (d:0x00004000+0x100+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
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bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
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|
group.word (d:0x00004000+0x100+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
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|
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bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
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|
group.word (d:0x00004000+0x100+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
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bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x100+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
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group.word (d:0x00004000+0x100+0x18)++0x01
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line.word 0x00 "VCAPCTL,Valley Capture Control Register"
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bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
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|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
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bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
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group.word (d:0x00004000+0x100+0x19)++0x01
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line.word 0x00 "VCNTCFG,Valley Counter Config Register"
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rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
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bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
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bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x100+0x20)++0x01
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line.word 0x00 "HRCNFG,HRPWM Configuration Register"
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bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
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bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
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bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
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bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
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bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
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|
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bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
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group.word (d:0x00004000+0x100+0x21)++0x01
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line.word 0x00 "HRPWR,HRPWM Power Register"
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bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
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group.word (d:0x00004000+0x100+0x26)++0x01
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line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
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hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
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group.word (d:0x00004000+0x100+0x27)++0x01
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line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
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bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
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group.word (d:0x00004000+0x100+0x2D)++0x01
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line.word 0x00 "HRPCTL,High Resolution Period Control Register"
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bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
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bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
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bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
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group.word (d:0x00004000+0x100+0x2E)++0x01
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line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
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hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
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group.word (d:0x00004000+0x100+0x34)++0x01
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line.word 0x00 "GLDCTL,Global PWM Load Control Register"
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rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
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bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
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group.word (d:0x00004000+0x100+0x35)++0x01
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line.word 0x00 "GLDCFG,Global PWM Load Config Register"
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bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
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bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
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bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
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bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
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bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
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bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
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bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
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bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
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|
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bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
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bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
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bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
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group.long (d:0x00004000+0x100+0x38)++0x03
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line.long 0x00 "EPWMXLINK,EPWMx Link Register"
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bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x100+0x40)++0x01
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line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
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bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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|
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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group.word (d:0x00004000+0x100+0x41)++0x01
|
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line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
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bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
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bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
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bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
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bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
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group.word (d:0x00004000+0x100+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
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bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
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bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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|
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
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group.word (d:0x00004000+0x100+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x100+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x100+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x100+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x100+0x51)++0x01
|
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line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x100+0x52)++0x01
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x100+0x53)++0x01
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0x100+0x60)++0x03
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|
line.long 0x00 "TBPHS,Time Base Phase High"
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|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0x100+0x62)++0x01
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x100+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x100+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x100+0x6C)++0x03
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|
line.long 0x00 "CMPB,Compare B Register"
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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|
group.word (d:0x00004000+0x100+0x6F)++0x01
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0x100+0x71)++0x01
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|
line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0x100+0x74)++0x01
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x100+0x77)++0x01
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|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
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group.word (d:0x00004000+0x100+0x80)++0x01
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|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
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bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
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bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
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newline
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
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bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
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newline
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|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
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newline
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
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bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
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bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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|
group.word (d:0x00004000+0x100+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x100+0x84)++0x01
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line.word 0x00 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
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newline
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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group.word (d:0x00004000+0x100+0x85)++0x01
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line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x100+0x86)++0x01
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line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x100+0x87)++0x01
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line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x100+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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newline
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0x100+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
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newline
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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rgroup.word (d:0x00004000+0x100+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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newline
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0x100+0x95)++0x01
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|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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|
newline
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
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|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
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|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0x100+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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newline
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0x100+0x98)++0x01
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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newline
|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x100+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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newline
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x100+0x9B)++0x01
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line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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|
newline
|
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
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|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word (d:0x00004000+0x100+0xA4)++0x01
|
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
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|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
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newline
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x100+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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|
newline
|
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x100+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
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group.word (d:0x00004000+0x100+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x100+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x100+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x100+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x100+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0x100+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x100+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x100+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x100+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x100+0xC7)++0x01
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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newline
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0x100+0xC8)++0x01
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
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rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
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|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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newline
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x100+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x100+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
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|
group.word (d:0x00004000+0x100+0xCB)++0x01
|
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line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word (d:0x00004000+0x100+0xCC)++0x01
|
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line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
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rgroup.word (d:0x00004000+0x100+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x100+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
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|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
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group.word (d:0x00004000+0x100+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x100+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
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group.word (d:0x00004000+0x100+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
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group.long (d:0x00004000+0x100+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
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bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
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rgroup.word (d:0x00004000+0x100+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x100+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 3"
|
|
width 15.
|
|
group.word (d:0x00004000+0x200)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x200+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x200+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x200+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x200+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x200+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x200+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x200+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x200+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x200+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x200+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x200+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x200+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x200+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x200+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x200+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x200+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x200+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x200+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x200+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x200+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x200+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x200+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x200+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x200+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x200+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0x200+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0x200+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0x200+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x200+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x200+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0x200+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0x200+0x84)++0x01
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line.word 0x00 "TZCTL,Trip Zone Control Register"
|
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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group.word (d:0x00004000+0x200+0x85)++0x01
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line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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|
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x200+0x86)++0x01
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line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x200+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
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bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0x200+0x8D)++0x01
|
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0x200+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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rgroup.word (d:0x00004000+0x200+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0x200+0x95)++0x01
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line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0x200+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0x200+0x98)++0x01
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x200+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x200+0x9B)++0x01
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line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word (d:0x00004000+0x200+0xA4)++0x01
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x200+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0x200+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0x200+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0x200+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0x200+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x200+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x200+0xB2)++0x01
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0x200+0xB4)++0x01
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x200+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x200+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x200+0xC4)++0x01
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0x200+0xC7)++0x01
|
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x200+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x200+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x200+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x200+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x200+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x200+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x200+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x200+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x200+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x200+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x200+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x200+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x200+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 4"
|
|
width 15.
|
|
group.word (d:0x00004000+0x300)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
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bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x300+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x300+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x300+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x300+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x300+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x300+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x300+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x300+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x300+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x300+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x300+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x300+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x300+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x300+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x300+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x300+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x300+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x300+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
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group.word (d:0x00004000+0x300+0x52)++0x01
|
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x300+0x53)++0x01
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0x300+0x60)++0x03
|
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line.long 0x00 "TBPHS,Time Base Phase High"
|
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0x300+0x62)++0x01
|
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
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group.word (d:0x00004000+0x300+0x63)++0x01
|
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line.word 0x00 "TBPRD,Time Base Period Register"
|
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group.long (d:0x00004000+0x300+0x6A)++0x03
|
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line.long 0x00 "CMPA,Counter Compare A Register"
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
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group.long (d:0x00004000+0x300+0x6C)++0x03
|
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line.long 0x00 "CMPB,Compare B Register"
|
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word (d:0x00004000+0x300+0x6F)++0x01
|
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0x300+0x71)++0x01
|
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line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0x300+0x74)++0x01
|
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
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bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
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group.word (d:0x00004000+0x300+0x77)++0x01
|
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line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
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group.word (d:0x00004000+0x300+0x80)++0x01
|
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line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0x300+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x300+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x300+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x300+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x300+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x300+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0x300+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0x300+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0x300+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word (d:0x00004000+0x300+0x97)++0x01
|
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
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group.word (d:0x00004000+0x300+0x98)++0x01
|
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
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group.word (d:0x00004000+0x300+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x300+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x300+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x300+0xA6)++0x01
|
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0x300+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
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group.word (d:0x00004000+0x300+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0x300+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0x300+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x300+0xB0)++0x01
|
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x300+0xB2)++0x01
|
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0x300+0xB4)++0x01
|
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x300+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x300+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x300+0xC4)++0x01
|
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x300+0xC7)++0x01
|
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
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bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
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bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0x300+0xC8)++0x01
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
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rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
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bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
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group.word (d:0x00004000+0x300+0xC9)++0x01
|
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line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
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rgroup.word (d:0x00004000+0x300+0xCA)++0x01
|
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line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
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group.word (d:0x00004000+0x300+0xCB)++0x01
|
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line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word (d:0x00004000+0x300+0xCC)++0x01
|
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line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x300+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x300+0xD2)++0x01
|
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line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x300+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x300+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x300+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x300+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x300+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x300+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 5"
|
|
width 15.
|
|
group.word (d:0x00004000+0x400)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
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bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
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bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x400+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x400+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x400+0x05)++0x01
|
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line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x400+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x400+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x400+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
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|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
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|
group.word (d:0x00004000+0x400+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
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bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
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bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x400+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x400+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x400+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x400+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x400+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x400+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x400+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x400+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x400+0x40)++0x01
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|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
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|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
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|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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|
newline
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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|
group.word (d:0x00004000+0x400+0x41)++0x01
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|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
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|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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|
group.word (d:0x00004000+0x400+0x42)++0x01
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line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
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bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
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|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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|
newline
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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group.word (d:0x00004000+0x400+0x43)++0x01
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line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
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bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word (d:0x00004000+0x400+0x47)++0x01
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line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
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bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
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bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
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bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
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bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
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newline
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bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
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group.word (d:0x00004000+0x400+0x49)++0x01
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line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
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bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
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bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
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group.word (d:0x00004000+0x400+0x50)++0x01
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line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x400+0x51)++0x01
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line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
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group.word (d:0x00004000+0x400+0x52)++0x01
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x400+0x53)++0x01
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0x400+0x60)++0x03
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line.long 0x00 "TBPHS,Time Base Phase High"
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0x400+0x62)++0x01
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
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group.word (d:0x00004000+0x400+0x63)++0x01
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line.word 0x00 "TBPRD,Time Base Period Register"
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group.long (d:0x00004000+0x400+0x6A)++0x03
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line.long 0x00 "CMPA,Counter Compare A Register"
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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group.long (d:0x00004000+0x400+0x6C)++0x03
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line.long 0x00 "CMPB,Compare B Register"
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word (d:0x00004000+0x400+0x6F)++0x01
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0x400+0x71)++0x01
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line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0x400+0x74)++0x01
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
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bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
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group.word (d:0x00004000+0x400+0x77)++0x01
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line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
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group.word (d:0x00004000+0x400+0x80)++0x01
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line.word 0x00 "TZSEL,Trip Zone Select Register"
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bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
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bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
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newline
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
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bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
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bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
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bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
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newline
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
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bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
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newline
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
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bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
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bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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group.word (d:0x00004000+0x400+0x82)++0x01
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line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x400+0x84)++0x01
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line.word 0x00 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
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newline
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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group.word (d:0x00004000+0x400+0x85)++0x01
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line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x400+0x86)++0x01
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line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x400+0x87)++0x01
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line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x400+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0x400+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
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newline
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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rgroup.word (d:0x00004000+0x400+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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newline
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0x400+0x95)++0x01
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line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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|
newline
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
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|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
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|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0x400+0x97)++0x01
|
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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|
newline
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0x400+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
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group.word (d:0x00004000+0x400+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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|
newline
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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|
group.word (d:0x00004000+0x400+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x400+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x400+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x400+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0x400+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x400+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x400+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0x400+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x400+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x400+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x400+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x400+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x400+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x400+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x400+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x400+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x400+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x400+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x400+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x400+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x400+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x400+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x400+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x400+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 6"
|
|
width 15.
|
|
group.word (d:0x00004000+0x500)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x500+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x500+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x500+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x500+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x500+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x500+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x500+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x500+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
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bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x500+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x500+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
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bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x500+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x500+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
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bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
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group.word (d:0x00004000+0x500+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
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group.word (d:0x00004000+0x500+0x34)++0x01
|
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line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x500+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x500+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x500+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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|
group.word (d:0x00004000+0x500+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x500+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x500+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x500+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x500+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x500+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x500+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x500+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0x500+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0x500+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0x500+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x500+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x500+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0x500+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x500+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x500+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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|
group.word (d:0x00004000+0x500+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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|
group.word (d:0x00004000+0x500+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x500+0x8D)++0x01
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|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
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|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
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|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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|
newline
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0x500+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
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|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
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|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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|
rgroup.word (d:0x00004000+0x500+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
newline
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
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|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
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|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0x500+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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|
newline
|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
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|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0x500+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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|
newline
|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0x500+0x98)++0x01
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x500+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x500+0x9B)++0x01
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|
line.word 0x00 "TZFRC,Trip Zone Force Register"
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|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x500+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x500+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x500+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0x500+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x500+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x500+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x500+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x500+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0x500+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x500+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x500+0xC3)++0x01
|
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x500+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x500+0xC7)++0x01
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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|
newline
|
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0x500+0xC8)++0x01
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|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x500+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x500+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
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group.word (d:0x00004000+0x500+0xCB)++0x01
|
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line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x500+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x500+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x500+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
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|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
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newline
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
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group.word (d:0x00004000+0x500+0xD3)++0x01
|
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line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
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|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
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group.word (d:0x00004000+0x500+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
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group.word (d:0x00004000+0x500+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x500+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
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bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x500+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x500+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 7"
|
|
width 15.
|
|
group.word (d:0x00004000+0x600)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x600+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x600+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x600+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x600+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x600+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x600+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x600+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x600+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x600+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x600+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x600+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x600+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x600+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x600+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x600+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x600+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x600+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x600+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x600+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x600+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x600+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x600+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x600+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x600+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x600+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0x600+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0x600+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0x600+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x600+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x600+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
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bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
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bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
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bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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group.word (d:0x00004000+0x600+0x82)++0x01
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line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x600+0x84)++0x01
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line.word 0x00 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
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bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
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group.word (d:0x00004000+0x600+0x85)++0x01
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line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
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bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x600+0x86)++0x01
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line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x600+0x87)++0x01
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line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
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bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x600+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0x600+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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rgroup.word (d:0x00004000+0x600+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0x600+0x95)++0x01
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line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0x600+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0x600+0x98)++0x01
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x600+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0x600+0x9B)++0x01
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line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word (d:0x00004000+0x600+0xA4)++0x01
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0x600+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0x600+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0x600+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0x600+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0x600+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x600+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x600+0xB2)++0x01
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0x600+0xB4)++0x01
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x600+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x600+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0x600+0xC4)++0x01
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x600+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x600+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x600+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x600+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x600+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x600+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x600+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x600+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x600+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x600+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x600+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x600+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x600+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x600+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 8"
|
|
width 15.
|
|
group.word (d:0x00004000+0x700)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
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|
group.word (d:0x00004000+0x700+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
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bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x700+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x700+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x700+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x700+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x700+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x700+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x700+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x700+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x700+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x700+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x700+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x700+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x700+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x700+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x700+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x700+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x700+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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|
newline
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|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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group.word (d:0x00004000+0x700+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
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|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word (d:0x00004000+0x700+0x47)++0x01
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line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
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bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
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bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
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|
newline
|
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bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x49)++0x01
|
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line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
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bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
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bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
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group.word (d:0x00004000+0x700+0x50)++0x01
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line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x700+0x51)++0x01
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line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
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group.word (d:0x00004000+0x700+0x52)++0x01
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0x700+0x53)++0x01
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0x700+0x60)++0x03
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line.long 0x00 "TBPHS,Time Base Phase High"
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0x700+0x62)++0x01
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
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group.word (d:0x00004000+0x700+0x63)++0x01
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line.word 0x00 "TBPRD,Time Base Period Register"
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group.long (d:0x00004000+0x700+0x6A)++0x03
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line.long 0x00 "CMPA,Counter Compare A Register"
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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group.long (d:0x00004000+0x700+0x6C)++0x03
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line.long 0x00 "CMPB,Compare B Register"
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word (d:0x00004000+0x700+0x6F)++0x01
|
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0x700+0x71)++0x01
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line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0x700+0x74)++0x01
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
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bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
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group.word (d:0x00004000+0x700+0x77)++0x01
|
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line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
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group.word (d:0x00004000+0x700+0x80)++0x01
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line.word 0x00 "TZSEL,Trip Zone Select Register"
|
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bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
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|
newline
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
newline
|
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
newline
|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
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bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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group.word (d:0x00004000+0x700+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x700+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x700+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x700+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x700+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x700+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0x700+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0x700+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0x700+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x700+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0x700+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x700+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
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group.word (d:0x00004000+0x700+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x700+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x700+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
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|
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0x700+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0x700+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0x700+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0x700+0xAE)++0x01
|
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x700+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x700+0xB2)++0x01
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0x700+0xB4)++0x01
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x700+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x700+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0x700+0xC4)++0x01
|
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0x700+0xC7)++0x01
|
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
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bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
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bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
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group.word (d:0x00004000+0x700+0xC8)++0x01
|
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x700+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x700+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x700+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x700+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x700+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x700+0xD2)++0x01
|
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line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
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|
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x700+0xD3)++0x01
|
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line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x700+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x700+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
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|
group.long (d:0x00004000+0x700+0xFA)++0x03
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line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
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hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
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bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x700+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x700+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
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width 0x0B
|
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tree.end
|
|
tree "Submodule 9"
|
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width 15.
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group.word (d:0x00004000+0x800)++0x01
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line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
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bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
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group.word (d:0x00004000+0x800+0x01)++0x01
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line.word 0x00 "TBCTL2,Time Base Control Register 2"
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bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x800+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x800+0x04)++0x01
|
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line.word 0x00 "TBCTR,Time Base Counter Register"
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group.word (d:0x00004000+0x800+0x05)++0x01
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line.word 0x00 "TBSTS,Time Base Status Register"
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bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
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bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
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rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x800+0x06)++0x01
|
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line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
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bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
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|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
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bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
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bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
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bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
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group.word (d:0x00004000+0x800+0x07)++0x01
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line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
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hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
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bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
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group.word (d:0x00004000+0x800+0x08)++0x01
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line.word 0x00 "CMPCTL,Counter Compare Control Register"
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bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
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rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
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rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
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bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
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bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
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bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
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|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
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group.word (d:0x00004000+0x800+0x09)++0x01
|
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line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
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bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
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bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
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bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
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bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
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group.word (d:0x00004000+0x800+0x0C)++0x01
|
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line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
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bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
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bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
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bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
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bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
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bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
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bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
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bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
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bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
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bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
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group.word (d:0x00004000+0x800+0x0D)++0x01
|
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line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
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bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x10)++0x01
|
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line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
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bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
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bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
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group.word (d:0x00004000+0x800+0x11)++0x01
|
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line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x800+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x800+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x800+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x800+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x800+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x800+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x800+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x800+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x800+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x800+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x800+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x800+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x800+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x800+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x800+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x800+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x800+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x800+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x800+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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|
group.word (d:0x00004000+0x800+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
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|
group.word (d:0x00004000+0x800+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
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|
group.word (d:0x00004000+0x800+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
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|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
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|
group.word (d:0x00004000+0x800+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x800+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
newline
|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
newline
|
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
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|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
newline
|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
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|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
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|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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|
group.word (d:0x00004000+0x800+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
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|
group.word (d:0x00004000+0x800+0x84)++0x01
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line.word 0x00 "TZCTL,Trip Zone Control Register"
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|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
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|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
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|
newline
|
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
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|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x800+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x800+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x800+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0x800+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0x800+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0x800+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x800+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0x800+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x800+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x800+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x800+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x800+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x800+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0x800+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x800+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x800+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x800+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x800+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0x800+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x800+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x800+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
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|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0x800+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
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|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x800+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
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|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x800+0xC8)++0x01
|
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
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|
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x800+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x800+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x800+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x800+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x800+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x800+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x800+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x800+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x800+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x800+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x800+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x800+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 10"
|
|
width 15.
|
|
group.word (d:0x00004000+0x900)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
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|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0x900+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0x900+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0x900+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0x900+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x900+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0x900+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
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bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
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bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
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|
newline
|
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bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
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|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
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|
group.word (d:0x00004000+0x900+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x900+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0x900+0x18)++0x01
|
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line.word 0x00 "VCAPCTL,Valley Capture Control Register"
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|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0x900+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0x900+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
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bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
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bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
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bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
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bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
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bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
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bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0x900+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0x900+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0x900+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0x900+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0x900+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0x900+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x900+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x900+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0x900+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0x900+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0x900+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0x900+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0x900+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0x900+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0x900+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0x900+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0x900+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0x900+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0x900+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0x900+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0x900+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x900+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x900+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x900+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x900+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0x900+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0x900+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0x900+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x900+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0x900+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x900+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0x900+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0x900+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0x900+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0x900+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0x900+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0x900+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0x900+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x900+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0x900+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0x900+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.word (d:0x00004000+0x900+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0x900+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x900+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0x900+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0x900+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0x900+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0x900+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0x900+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0x900+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0x900+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0x900+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0x900+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0x900+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0x900+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0x900+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0x900+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0x900+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 11"
|
|
width 15.
|
|
group.word (d:0x00004000+0xA00)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0xA00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0xA00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xA00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xA00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xA00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xA00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xA00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
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bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
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bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
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bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
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bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x09)++0x01
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line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
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bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
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bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
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bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
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bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x0C)++0x01
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line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
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bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
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bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
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bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
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bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
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bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
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bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
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bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
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bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
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bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x0D)++0x01
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line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
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bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
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bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x10)++0x01
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line.word 0x00 "AQCTL,Action Qualifier Control Register"
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bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
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bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
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bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
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bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
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bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x11)++0x01
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line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
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bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0x14)++0x01
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line.word 0x00 "PCCTL,PWM Chopper Control Register"
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bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
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group.word (d:0x00004000+0xA00+0x18)++0x01
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line.word 0x00 "VCAPCTL,Valley Capture Control Register"
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bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
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bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
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bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
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group.word (d:0x00004000+0xA00+0x19)++0x01
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line.word 0x00 "VCNTCFG,Valley Counter Config Register"
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rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
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bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
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bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0x20)++0x01
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line.word 0x00 "HRCNFG,HRPWM Configuration Register"
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bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
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bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
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bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
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bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
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bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
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bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x21)++0x01
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line.word 0x00 "HRPWR,HRPWM Power Register"
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bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
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group.word (d:0x00004000+0xA00+0x26)++0x01
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line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
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hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
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group.word (d:0x00004000+0xA00+0x27)++0x01
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line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
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bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
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bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x2D)++0x01
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line.word 0x00 "HRPCTL,High Resolution Period Control Register"
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bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
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bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
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bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
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group.word (d:0x00004000+0xA00+0x2E)++0x01
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line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
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hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
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group.word (d:0x00004000+0xA00+0x34)++0x01
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line.word 0x00 "GLDCTL,Global PWM Load Control Register"
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rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
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bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
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group.word (d:0x00004000+0xA00+0x35)++0x01
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line.word 0x00 "GLDCFG,Global PWM Load Config Register"
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bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
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bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
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bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
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bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
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bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
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bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
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bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
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bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
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bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
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bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
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bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
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group.long (d:0x00004000+0xA00+0x38)++0x03
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line.long 0x00 "EPWMXLINK,EPWMx Link Register"
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bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0x40)++0x01
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line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
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bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x41)++0x01
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line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
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bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x42)++0x01
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line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
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bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
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bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
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bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
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bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
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bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x43)++0x01
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line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
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bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
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bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
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bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x47)++0x01
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line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
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bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
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bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
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bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
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bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
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bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x49)++0x01
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line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
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bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
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bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
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group.word (d:0x00004000+0xA00+0x50)++0x01
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line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0xA00+0x51)++0x01
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line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
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group.word (d:0x00004000+0xA00+0x52)++0x01
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0xA00+0x53)++0x01
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0xA00+0x60)++0x03
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line.long 0x00 "TBPHS,Time Base Phase High"
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0xA00+0x62)++0x01
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
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group.word (d:0x00004000+0xA00+0x63)++0x01
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line.word 0x00 "TBPRD,Time Base Period Register"
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group.long (d:0x00004000+0xA00+0x6A)++0x03
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line.long 0x00 "CMPA,Counter Compare A Register"
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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group.long (d:0x00004000+0xA00+0x6C)++0x03
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line.long 0x00 "CMPB,Compare B Register"
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word (d:0x00004000+0xA00+0x6F)++0x01
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0xA00+0x71)++0x01
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line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0xA00+0x74)++0x01
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
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bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
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group.word (d:0x00004000+0xA00+0x77)++0x01
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line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
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group.word (d:0x00004000+0xA00+0x80)++0x01
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line.word 0x00 "TZSEL,Trip Zone Select Register"
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|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
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bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
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bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0xA00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0xA00+0x84)++0x01
|
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line.word 0x00 "TZCTL,Trip Zone Control Register"
|
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
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bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
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group.word (d:0x00004000+0xA00+0x85)++0x01
|
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line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
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bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0xA00+0x86)++0x01
|
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line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xA00+0x87)++0x01
|
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line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0xA00+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0xA00+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0xA00+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
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rgroup.word (d:0x00004000+0xA00+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0xA00+0x97)++0x01
|
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
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|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0xA00+0x98)++0x01
|
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xA00+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xA00+0x9B)++0x01
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line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word (d:0x00004000+0xA00+0xA4)++0x01
|
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0xA00+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0xA00+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0xA00+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
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group.word (d:0x00004000+0xA00+0xAC)++0x01
|
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
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group.word (d:0x00004000+0xA00+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0xB2)++0x01
|
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
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group.word (d:0x00004000+0xA00+0xB4)++0x01
|
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0xC0)++0x01
|
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xA00+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xA00+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xA00+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xA00+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0xA00+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0xA00+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0xA00+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0xA00+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0xA00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0xA00+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0xA00+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xA00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
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group.word (d:0x00004000+0xA00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xA00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0xA00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xA00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 12"
|
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width 15.
|
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group.word (d:0x00004000+0xB00)++0x01
|
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line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
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group.word (d:0x00004000+0xB00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
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bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xB00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xB00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xB00+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xB00+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0xB00+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0xB00+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0xB00+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xB00+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
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|
group.word (d:0x00004000+0xB00+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
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|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
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bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
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group.word (d:0x00004000+0xB00+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0xB00+0x51)++0x01
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line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
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hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
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group.word (d:0x00004000+0xB00+0x52)++0x01
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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group.word (d:0x00004000+0xB00+0x53)++0x01
|
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
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group.long (d:0x00004000+0xB00+0x60)++0x03
|
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line.long 0x00 "TBPHS,Time Base Phase High"
|
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0xB00+0x62)++0x01
|
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
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group.word (d:0x00004000+0xB00+0x63)++0x01
|
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line.word 0x00 "TBPRD,Time Base Period Register"
|
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group.long (d:0x00004000+0xB00+0x6A)++0x03
|
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line.long 0x00 "CMPA,Counter Compare A Register"
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
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group.long (d:0x00004000+0xB00+0x6C)++0x03
|
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line.long 0x00 "CMPB,Compare B Register"
|
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0xB00+0x6F)++0x01
|
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line.word 0x00 "CMPC,Counter Compare C Register"
|
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group.word (d:0x00004000+0xB00+0x71)++0x01
|
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line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0xB00+0x74)++0x01
|
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
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bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
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group.word (d:0x00004000+0xB00+0x80)++0x01
|
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line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0xB00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xB00+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0xB00+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xB00+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xB00+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0xB00+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
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rgroup.word (d:0x00004000+0xB00+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
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rgroup.word (d:0x00004000+0xB00+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
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bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
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rgroup.word (d:0x00004000+0xB00+0x95)++0x01
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line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
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bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word (d:0x00004000+0xB00+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
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group.word (d:0x00004000+0xB00+0x98)++0x01
|
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
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group.word (d:0x00004000+0xB00+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xB00+0x9B)++0x01
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line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
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bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0xB00+0xA4)++0x01
|
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0xB00+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0xB00+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0xB00+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0xB00+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0xB00+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xB00+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xB00+0xB2)++0x01
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0xB00+0xB4)++0x01
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xB00+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xB00+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0xB00+0xC4)++0x01
|
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0xB00+0xC7)++0x01
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
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bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
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bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0xB00+0xC8)++0x01
|
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
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bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
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group.word (d:0x00004000+0xB00+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
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rgroup.word (d:0x00004000+0xB00+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0xB00+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word (d:0x00004000+0xB00+0xCC)++0x01
|
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line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
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rgroup.word (d:0x00004000+0xB00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0xB00+0xD2)++0x01
|
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line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0xB00+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xB00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0xB00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xB00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0xB00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xB00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 13"
|
|
width 15.
|
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group.word (d:0x00004000+0xC00)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
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bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
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|
group.word (d:0x00004000+0xC00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xC00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xC00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
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bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
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bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
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bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
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bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xC00+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xC00+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0xC00+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0xC00+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0xC00+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xC00+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xC00+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0xC00+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xC00+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0xC00+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
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group.word (d:0x00004000+0xC00+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0xC00+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0xC00+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
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|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
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|
group.long (d:0x00004000+0xC00+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
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|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
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group.word (d:0x00004000+0xC00+0x6F)++0x01
|
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line.word 0x00 "CMPC,Counter Compare C Register"
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group.word (d:0x00004000+0xC00+0x71)++0x01
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line.word 0x00 "CMPD,Counter Compare D Register"
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group.word (d:0x00004000+0xC00+0x74)++0x01
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
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bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
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|
group.word (d:0x00004000+0xC00+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
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group.word (d:0x00004000+0xC00+0x80)++0x01
|
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line.word 0x00 "TZSEL,Trip Zone Select Register"
|
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bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
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bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
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bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
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bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
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bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
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|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
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bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
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bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
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bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
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bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
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group.word (d:0x00004000+0xC00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
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bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xC00+0x84)++0x01
|
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line.word 0x00 "TZCTL,Trip Zone Control Register"
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bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
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bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
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bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
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bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0xC00+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
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bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xC00+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
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bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xC00+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xC00+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0xC00+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0xC00+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0xC00+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xC00+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
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|
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xC00+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
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|
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0xC00+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xAA)++0x01
|
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0xC00+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xC00+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xB4)++0x01
|
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xC00+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xC00+0xC3)++0x01
|
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
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|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0xC00+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
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|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
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group.word (d:0x00004000+0xC00+0xC7)++0x01
|
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
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rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
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bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
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bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0xC00+0xC8)++0x01
|
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
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rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
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bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
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group.word (d:0x00004000+0xC00+0xC9)++0x01
|
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line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
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rgroup.word (d:0x00004000+0xC00+0xCA)++0x01
|
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line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
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group.word (d:0x00004000+0xC00+0xCB)++0x01
|
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line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word (d:0x00004000+0xC00+0xCC)++0x01
|
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line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
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rgroup.word (d:0x00004000+0xC00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
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group.word (d:0x00004000+0xC00+0xD2)++0x01
|
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line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
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bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
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group.word (d:0x00004000+0xC00+0xD3)++0x01
|
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line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
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bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
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bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
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|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
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|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
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|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0xC00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
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|
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bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xC00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0xC00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xC00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 14"
|
|
width 15.
|
|
group.word (d:0x00004000+0xD00)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xD00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xD00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
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bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0xD00+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0xD00+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0xD00+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xD00+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0xD00+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xD00+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0xD00+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0xD00+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0xD00+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0xD00+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0xD00+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0xD00+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0xD00+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0xD00+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0xD00+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
|
bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xD00+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xD00+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xD00+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xD00+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0xD00+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0xD00+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0xD00+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x98)++0x01
|
|
line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x99)++0x01
|
|
line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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|
|
bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
|
|
group.word (d:0x00004000+0xD00+0x9B)++0x01
|
|
line.word 0x00 "TZFRC,Trip Zone Force Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xA4)++0x01
|
|
line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
|
bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
|
bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
|
bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xD00+0xA6)++0x01
|
|
line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
|
|
rgroup.word (d:0x00004000+0xD00+0xA8)++0x01
|
|
line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xAA)++0x01
|
|
line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0xC0)++0x01
|
|
line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xD00+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xD00+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0xD00+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0xD00+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0xD00+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0xD00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0xD00+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0xD00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xD00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0xD00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xD00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 15"
|
|
width 15.
|
|
group.word (d:0x00004000+0xE00)++0x01
|
|
line.word 0x00 "TBCTL,Time Base Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xE00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xE00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
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|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xE00+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xE00+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
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|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0xE00+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0xE00+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0xE00+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xE00+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
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|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xE00+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
|
group.word (d:0x00004000+0xE00+0x52)++0x01
|
|
line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
|
bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xE00+0x53)++0x01
|
|
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
|
group.long (d:0x00004000+0xE00+0x60)++0x03
|
|
line.long 0x00 "TBPHS,Time Base Phase High"
|
|
hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
|
hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
|
group.word (d:0x00004000+0xE00+0x62)++0x01
|
|
line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
|
group.word (d:0x00004000+0xE00+0x63)++0x01
|
|
line.word 0x00 "TBPRD,Time Base Period Register"
|
|
group.long (d:0x00004000+0xE00+0x6A)++0x03
|
|
line.long 0x00 "CMPA,Counter Compare A Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0xE00+0x6C)++0x03
|
|
line.long 0x00 "CMPB,Compare B Register"
|
|
hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
|
hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0xE00+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
|
group.word (d:0x00004000+0xE00+0x71)++0x01
|
|
line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0xE00+0x74)++0x01
|
|
line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0xE00+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0xE00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xE00+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
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|
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bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
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bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xE00+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0xE00+0x87)++0x01
|
|
line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xE00+0x8D)++0x01
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line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0xE00+0x93)++0x01
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line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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|
bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
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bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
|
rgroup.word (d:0x00004000+0xE00+0x94)++0x01
|
|
line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
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bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0xE00+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
|
bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
|
|
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
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bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
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group.word (d:0x00004000+0xE00+0x97)++0x01
|
|
line.word 0x00 "TZCLR,Trip Zone Clear Register"
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bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0xE00+0x98)++0x01
|
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
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bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xE00+0x99)++0x01
|
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
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bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
|
|
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
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bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xE00+0x9B)++0x01
|
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line.word 0x00 "TZFRC,Trip Zone Force Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
|
|
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|
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
|
|
bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
|
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group.word (d:0x00004000+0xE00+0xA4)++0x01
|
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
|
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
|
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
|
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
|
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
|
|
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
|
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group.word (d:0x00004000+0xE00+0xA6)++0x01
|
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
|
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
|
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|
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
|
|
bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
|
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
|
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0xE00+0xA8)++0x01
|
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
|
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group.word (d:0x00004000+0xE00+0xAA)++0x01
|
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
|
|
bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xAC)++0x01
|
|
line.word 0x00 "ETFRC,Event Trigger Force Register"
|
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
|
|
bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
|
|
bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xAE)++0x01
|
|
line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
|
|
rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xE00+0xB0)++0x01
|
|
line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
|
|
rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.word (d:0x00004000+0xE00+0xB2)++0x01
|
|
line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
|
|
bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
|
|
bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
|
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
|
|
bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xB4)++0x01
|
|
line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
|
|
bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xE00+0xC0)++0x01
|
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
|
|
bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xE00+0xC3)++0x01
|
|
line.word 0x00 "DCACTL,Digital Compare A Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xC4)++0x01
|
|
line.word 0x00 "DCBCTL,Digital Compare B Control Register"
|
|
rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
|
|
bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
|
bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
|
rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
|
|
bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
|
bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xC7)++0x01
|
|
line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
|
bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xE00+0xC8)++0x01
|
|
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
|
|
bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
|
bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0xE00+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0xE00+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
|
rgroup.word (d:0x00004000+0xE00+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0xE00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0xE00+0xD2)++0x01
|
|
line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0xE00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
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bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xE00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
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bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
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rgroup.word (d:0x00004000+0xE00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xE00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Submodule 16"
|
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width 15.
|
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group.word (d:0x00004000+0xF00)++0x01
|
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line.word 0x00 "TBCTL,Time Base Control Register"
|
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bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "0,1,2,3"
|
|
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "0,1"
|
|
bitfld.word 0x00 10.--12. " CLKDIV ,Time Base Clock Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed TBCLK Pre-scaler" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.word 0x00 6. " SWFSYNC ,Software Force Sync Pulse" "0,1"
|
|
bitfld.word 0x00 3. " PRDLD ,Active Period Load" "0,1"
|
|
bitfld.word 0x00 2. " PHSEN ,Phase Load Enable" "0,1"
|
|
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x01)++0x01
|
|
line.word 0x00 "TBCTL2,Time Base Control Register 2"
|
|
bitfld.word 0x00 14.--15. " PRDLDSYNC ,PRD Shadow to Active Load on SYNC Event" "0,1,2,3"
|
|
bitfld.word 0x00 7. " OSHTSYNC ,One shot sync" "0,1"
|
|
bitfld.word 0x00 6. " OSHTSYNCMODE ,One shot sync mode" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x03)++0x01
|
|
line.word 0x00 "EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register"
|
|
bitfld.word 0x00 0.--4. " SEL ,EPWMxSYNCI source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00004000+0xF00+0x04)++0x01
|
|
line.word 0x00 "TBCTR,Time Base Counter Register"
|
|
group.word (d:0x00004000+0xF00+0x05)++0x01
|
|
line.word 0x00 "TBSTS,Time Base Status Register"
|
|
bitfld.word 0x00 2. " CTRMAX ,Counter Max Latched Status" "0,1"
|
|
bitfld.word 0x00 1. " SYNCI ,External Input Sync Status" "0,1"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Counter Direction Status" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x06)++0x01
|
|
line.word 0x00 "EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register"
|
|
bitfld.word 0x00 6. " DCBEVT1EN ,EPWMxSYNCO Digital Compare B Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 5. " DCAEVT1EN ,EPWMxSYNCO Digital Compare A Event 1 Sync Enable" "0,1"
|
|
bitfld.word 0x00 4. " CMPDEN ,EPWMxSYNCO Compare D Event Enable" "0,1"
|
|
bitfld.word 0x00 3. " CMPCEN ,EPWMxSYNCO Compare C Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CMPBEN ,EPWMxSYNCO Compare B Event Enable" "0,1"
|
|
bitfld.word 0x00 1. " ZEROEN ,EPWMxSYNCO Zero Count Event Enable" "0,1"
|
|
bitfld.word 0x00 0. " SWEN ,EPWMxSYNCO Software Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x07)++0x01
|
|
line.word 0x00 "TBCTL3,Time Base Control Register 3"
|
|
hexmask.word 0x00 1.--15. 1. "Rerserved,Reserved"
|
|
bitfld.word 0x00 0. " OSSFRCEN ,One Shot Sync Force Enable" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x08)++0x01
|
|
line.word 0x00 "CMPCTL,Counter Compare Control Register"
|
|
bitfld.word 0x00 12.--13. " LOADBSYNC ,Active Compare B Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADASYNC ,Active Compare A Load on SYNC" "0,1,2,3"
|
|
rbitfld.word 0x00 9. " SHDWBFULL ,Compare B Shadow Register Full Status" "0,1"
|
|
rbitfld.word 0x00 8. " SHDWAFULL ,Compare A Shadow Register Full Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " SHDWBMODE ,Compare B Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAMODE ,Compare A Register Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Compare B Load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Compare A Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x09)++0x01
|
|
line.word 0x00 "CMPCTL2,Counter Compare Control Register 2"
|
|
bitfld.word 0x00 12.--13. " LOADDSYNC ,Active Compare D Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " LOADCSYNC ,Active Compare C Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWDMODE ,Compare D Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWCMODE ,Compare C Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LOADDMODE ,Active Compare D load" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LOADCMODE ,Active Compare C Load" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x0C)++0x01
|
|
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
|
|
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable" "0,1"
|
|
bitfld.word 0x00 14. " DEDB_MODE ,Dead Band Dual-Edge B Mode Control" "0,1"
|
|
bitfld.word 0x00 12.--13. " OUTSWAP ,Dead Band Output Swap Control" "0,1,2,3"
|
|
bitfld.word 0x00 11. " SHDWDBFEDMODE ,DBFED Block Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SHDWDBREDMODE ,DBRED Block Operating Mode" "0,1"
|
|
bitfld.word 0x00 8.--9. " LOADFEDMODE ,Active DBFED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " LOADREDMODE ,Active DBRED Load Mode" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Select Mode Control" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead Band Output Mode Control" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x0D)++0x01
|
|
line.word 0x00 "DBCTL2,Dead-Band Generator Control Register 2"
|
|
bitfld.word 0x00 2. " SHDWDBCTLMODE ,DBCTL Load mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " LOADDBCTLMODE ,DBCTL Load from Shadow Mode Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x10)++0x01
|
|
line.word 0x00 "AQCTL,Action Qualifier Control Register"
|
|
bitfld.word 0x00 10.--11. " LDAQBSYNC ,AQCTLB Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " LDAQASYNC ,AQCTLA Register Load on SYNC" "0,1,2,3"
|
|
bitfld.word 0x00 6. " SHDWAQBMODE ,Action Qualifier B Operating Mode" "0,1"
|
|
bitfld.word 0x00 4. " SHDWAQAMODE ,Action Qualifer A Operating Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " LDAQBMODE ,Action Qualifier B Load Select" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " LDAQAMODE ,Action Qualifier A Load Select" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x11)++0x01
|
|
line.word 0x00 "AQTSRCSEL,Action Qualifier Trigger Event Source Select Register"
|
|
bitfld.word 0x00 4.--7. " T2SEL ,T2 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " T1SEL ,T1 Event Source Select Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xF00+0x14)++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopper Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock Duty cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM chopping enable" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x18)++0x01
|
|
line.word 0x00 "VCAPCTL,Valley Capture Control Register"
|
|
bitfld.word 0x00 10. " EDGEFILTDLYSEL ,Valley Switching Mode Delay Select" "0,1"
|
|
bitfld.word 0x00 7.--9. " VDELAYDIV ,Valley Delay Mode Divide Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2.--4. " TRIGSEL ,Capture Trigger Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1. " VCAPSTART ,Valley Capture Start" "0,1"
|
|
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|
|
bitfld.word 0x00 0. " VCAPE ,Valley Capture mode" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x19)++0x01
|
|
line.word 0x00 "VCNTCFG,Valley Counter Config Register"
|
|
rbitfld.word 0x00 15. " STOPEDGESTS ,Stop Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 8.--11. " STOPEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 7. " STARTEDGESTS ,Start Edge Status Bit" "0,1"
|
|
bitfld.word 0x00 0.--3. " STARTEDGE ,Counter Start Edge Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xF00+0x20)++0x01
|
|
line.word 0x00 "HRCNFG,HRPWM Configuration Register"
|
|
bitfld.word 0x00 11.--12. " HRLOADB ,ePWMxB Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 10. " CTLMODEB ,ePWMxB Control Mode Select Bits" "0,1"
|
|
bitfld.word 0x00 8.--9. " EDGMODEB ,ePWMxB Edge Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAPAB ,Swap EPWMA and EPWMB Outputs Bit" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " AUTOCONV ,Autoconversion Bit" "0,1"
|
|
bitfld.word 0x00 5. " SELOUTB ,EPWMB Output Selection Bit" "0,1"
|
|
bitfld.word 0x00 3.--4. " HRLOAD ,ePWMxA Shadow Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2. " CTLMODE ,ePWMxA Control Mode Select Bits" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " EDGMODE ,ePWMxA Edge Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x21)++0x01
|
|
line.word 0x00 "HRPWR,HRPWM Power Register"
|
|
bitfld.word 0x00 15. " CALPWRON ,Calibration Power On" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x26)++0x01
|
|
line.word 0x00 "HRMSTEP,HRPWM MEP Step Register"
|
|
hexmask.word 0x00 0.--7. 1. "HRMSTEP,High Resolution Micro Step Value"
|
|
group.word (d:0x00004000+0xF00+0x27)++0x01
|
|
line.word 0x00 "HRCNFG2,HRPWM Configuration 2 Register"
|
|
bitfld.word 0x00 4.--5. " CTLMODEDBFED ,DBFED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CTLMODEDBRED ,DBRED Control Mode Select Bits" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " EDGMODEDB ,Dead-Band Edge-Mode Select Bits" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x2D)++0x01
|
|
line.word 0x00 "HRPCTL,High Resolution Period Control Register"
|
|
bitfld.word 0x00 4.--6. " PWMSYNCSELX ,EPWMSYNCPER Extended Source Select Bit:" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " TBPHSHRLOADE ,TBPHSHR Load Enable" "0,1"
|
|
bitfld.word 0x00 1. " PWMSYNCSEL ,EPWMSYNCPER Source Select" "0,1"
|
|
bitfld.word 0x00 0. " HRPE ,High Resolution Period Enable" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x2E)++0x01
|
|
line.word 0x00 "TRREM,Translator High Resolution Remainder Register"
|
|
hexmask.word 0x00 0.--10. 1. "TRREM,Translator Remainder Bits"
|
|
group.word (d:0x00004000+0xF00+0x34)++0x01
|
|
line.word 0x00 "GLDCTL,Global PWM Load Control Register"
|
|
rbitfld.word 0x00 10.--12. " GLDCNT ,Global Load Strobe Counter Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 7.--9. " GLDPRD ,Global Load Strobe Period Select Register" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 5. " OSHTMODE ,One Shot Load mode control bit" "0,1"
|
|
bitfld.word 0x00 1.--4. " GLDMODE ,Shadow to Active Global Load Pulse Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.word 0x00 0. " GLD ,Global Shadow to Active load event control" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x35)++0x01
|
|
line.word 0x00 "GLDCFG,Global PWM Load Config Register"
|
|
bitfld.word 0x00 10. " AQCSFRC ,Global load event configuration for AQCSFRC" "0,1"
|
|
bitfld.word 0x00 9. " AQCTLB_AQCTLB2 ,Global load event configuration for AQCTLB/B2" "0,1"
|
|
bitfld.word 0x00 8. " AQCTLA_AQCTLA2 ,Global load event configuration for AQCTLA/A2" "0,1"
|
|
bitfld.word 0x00 7. " DBCTL ,Global load event configuration for DBCTL" "0,1"
|
|
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|
|
bitfld.word 0x00 6. " DBFED_DBFEDHR ,Global load event configuration for DBFED:DBFEDHR" "0,1"
|
|
bitfld.word 0x00 5. " DBRED_DBREDHR ,Global load event configuration for DBRED:DBREDHR" "0,1"
|
|
bitfld.word 0x00 4. " CMPD ,Global load event configuration for CMPD" "0,1"
|
|
bitfld.word 0x00 3. " CMPC ,Global load event configuration for CMPC" "0,1"
|
|
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|
|
bitfld.word 0x00 2. " CMPB_CMPBHR ,Global load event configuration for CMPB:CMPBHR" "0,1"
|
|
bitfld.word 0x00 1. " CMPA_CMPAHR ,Global load event configuration for CMPA:CMPAHR" "0,1"
|
|
bitfld.word 0x00 0. " TBPRD_TBPRDHR ,Global load event configuration for TBPRD:TBPRDHR" "0,1"
|
|
group.long (d:0x00004000+0xF00+0x38)++0x03
|
|
line.long 0x00 "EPWMXLINK,EPWMx Link Register"
|
|
bitfld.long 0x00 28.--31. " GLDCTL2LINK ,GLDCTL2 Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMPDLINK ,CMPD Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " CMPCLINK ,CMPC Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CMPBLINK ,CMPB:CMPBHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CMPALINK ,CMPA:CMPAHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TBPRDLINK ,TBPRD:TBPRDHR Link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00004000+0xF00+0x40)++0x01
|
|
line.word 0x00 "AQCTLA,Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x41)++0x01
|
|
line.word 0x00 "AQCTLA2,Additional Action Qualifier Control Register For Output A"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x42)++0x01
|
|
line.word 0x00 "AQCTLB,Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action Counter = Compare B Down" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action Counter = Compare B Up" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action Counter = Compare A Down" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " CAU ,Action Counter = Compare A Up" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " PRD ,Action Counter = Period" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action Counter = Zero" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x43)++0x01
|
|
line.word 0x00 "AQCTLB2,Additional Action Qualifier Control Register For Output B"
|
|
bitfld.word 0x00 6.--7. " T2D ,Action when event occurs on T2 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " T2U ,Action when event occurs on T2 in UP-Count" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " T1D ,Action when event occurs on T1 in DOWN-Count" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " T1U ,Action when event occurs on T1 in UP-Count" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x47)++0x01
|
|
line.word 0x00 "AQSFRC,Action Qualifier Software Force Register"
|
|
bitfld.word 0x00 6.--7. " RLDCSF ,Reload from Shadow Options" "0,1,2,3"
|
|
bitfld.word 0x00 5. " OTSFB ,One-time SW Force A Output" "0,1"
|
|
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-time SW Force B Invoked" "0,1,2,3"
|
|
bitfld.word 0x00 2. " OTSFA ,One-time SW Force A Output" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " ACTSFA ,Action when One-time SW Force A Invoked" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x49)++0x01
|
|
line.word 0x00 "AQCSFRC,Action Qualifier Continuous S/W Force Register"
|
|
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on output B" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on output A" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x50)++0x01
|
|
line.word 0x00 "DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
bitfld.word 0x00 9.--15. " DBREDHR ,DBREDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00004000+0xF00+0x51)++0x01
|
|
line.word 0x00 "DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register"
|
|
hexmask.word 0x00 0.--13. 1. "DBRED,Rising edge delay value"
|
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group.word (d:0x00004000+0xF00+0x52)++0x01
|
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line.word 0x00 "DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register"
|
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bitfld.word 0x00 9.--15. " DBFEDHR ,DBFEDHR High Resolution Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
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group.word (d:0x00004000+0xF00+0x53)++0x01
|
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line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
|
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hexmask.word 0x00 0.--13. 1. "DBFED,Falling edge delay value"
|
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group.long (d:0x00004000+0xF00+0x60)++0x03
|
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line.long 0x00 "TBPHS,Time Base Phase High"
|
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hexmask.long 0x00 16.--31. 1. "TBPHS,Phase Offset Register"
|
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hexmask.long 0x00 0.--15. 1. "TBPHSHR,Extension Register for HRPWM Phase (8-bits)"
|
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group.word (d:0x00004000+0xF00+0x62)++0x01
|
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line.word 0x00 "TBPRDHR,Time Base Period High Resolution Register"
|
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group.word (d:0x00004000+0xF00+0x63)++0x01
|
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line.word 0x00 "TBPRD,Time Base Period Register"
|
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group.long (d:0x00004000+0xF00+0x6A)++0x03
|
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line.long 0x00 "CMPA,Counter Compare A Register"
|
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hexmask.long 0x00 16.--31. 1. "CMPA,Compare A Register"
|
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hexmask.long 0x00 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register"
|
|
group.long (d:0x00004000+0xF00+0x6C)++0x03
|
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line.long 0x00 "CMPB,Compare B Register"
|
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hexmask.long 0x00 16.--31. 1. "CMPB,Compare B Register"
|
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hexmask.long 0x00 0.--15. 1. "CMPBHR,Compare B High Resolution Bits"
|
|
group.word (d:0x00004000+0xF00+0x6F)++0x01
|
|
line.word 0x00 "CMPC,Counter Compare C Register"
|
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group.word (d:0x00004000+0xF00+0x71)++0x01
|
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line.word 0x00 "CMPD,Counter Compare D Register"
|
|
group.word (d:0x00004000+0xF00+0x74)++0x01
|
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line.word 0x00 "GLDCTL2,Global PWM Load Control Register 2"
|
|
bitfld.word 0x00 1. " GFRCLD ,Force reload event in one shot mode" "0,1"
|
|
bitfld.word 0x00 0. " OSHTLD ,Enable reload event in one shot mode" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x77)++0x01
|
|
line.word 0x00 "SWVDELVAL,Software Valley Mode Delay Register"
|
|
group.word (d:0x00004000+0xF00+0x80)++0x01
|
|
line.word 0x00 "TZSEL,Trip Zone Select Register"
|
|
bitfld.word 0x00 15. " DCBEVT1 ,One-shot DCBEVT1 select" "0,1"
|
|
bitfld.word 0x00 14. " DCAEVT1 ,One-shot DCAEVT1 select" "0,1"
|
|
bitfld.word 0x00 13. " OSHT6 ,One-shot TZ6 select" "0,1"
|
|
bitfld.word 0x00 12. " OSHT5 ,One-shot TZ5 select" "0,1"
|
|
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|
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bitfld.word 0x00 11. " OSHT4 ,One-shot TZ4 select" "0,1"
|
|
bitfld.word 0x00 10. " OSHT3 ,One-shot TZ3 select" "0,1"
|
|
bitfld.word 0x00 9. " OSHT2 ,One-shot TZ2 select" "0,1"
|
|
bitfld.word 0x00 8. " OSHT1 ,One-shot TZ1 select" "0,1"
|
|
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|
|
bitfld.word 0x00 7. " DCBEVT2 ,DCBEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 6. " DCAEVT2 ,DCAEVT2 CBC select" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,TZ6 CBC select" "0,1"
|
|
bitfld.word 0x00 4. " CBC5 ,TZ5 CBC select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CBC4 ,TZ4 CBC select" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,TZ3 CBC select" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,TZ2 CBC select" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,TZ1 CBC select" "0,1"
|
|
group.word (d:0x00004000+0xF00+0x82)++0x01
|
|
line.word 0x00 "TZDCSEL,Trip Zone Digital Comparator Select Register"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xF00+0x84)++0x01
|
|
line.word 0x00 "TZCTL,Trip Zone Control Register"
|
|
bitfld.word 0x00 10.--11. " DCBEVT2 ,EPWMxB action on DCBEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " DCBEVT1 ,EPWMxB action on DCBEVT1" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " DCAEVT2 ,EPWMxA action on DCAEVT2" "0,1,2,3"
|
|
bitfld.word 0x00 4.--5. " DCAEVT1 ,EPWMxA action on DCAEVT1" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2.--3. " TZB ,TZ1 to TZ6 Trip Action On EPWMxB" "0,1,2,3"
|
|
bitfld.word 0x00 0.--1. " TZA ,TZ1 to TZ6 Trip Action On EPWMxA" "0,1,2,3"
|
|
group.word (d:0x00004000+0xF00+0x85)++0x01
|
|
line.word 0x00 "TZCTL2,Additional Trip Zone Control Register"
|
|
bitfld.word 0x00 15. " ETZE ,TZCTL2 Enable" "0,1"
|
|
bitfld.word 0x00 9.--11. " TZBD ,Trip Action On EPWMxB while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " TZBU ,Trip Action On EPWMxB while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " TZAD ,Trip Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " TZAU ,Trip Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xF00+0x86)++0x01
|
|
line.word 0x00 "TZCTLDCA,Trip Zone Control Register Digital Compare A"
|
|
bitfld.word 0x00 9.--11. " DCAEVT2D ,DCAEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCAEVT2U ,DCAEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 3.--5. " DCAEVT1D ,DCAEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCAEVT1U ,DCAEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xF00+0x87)++0x01
|
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line.word 0x00 "TZCTLDCB,Trip Zone Control Register Digital Compare B"
|
|
bitfld.word 0x00 9.--11. " DCBEVT2D ,DCBEVT2 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6.--8. " DCBEVT2U ,DCBEVT2 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 3.--5. " DCBEVT1D ,DCBEVT1 Action On EPWMxA while Count direction is DOWN" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " DCBEVT1U ,DCBEVT1 Action On EPWMxA while Count direction is UP" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00004000+0xF00+0x8D)++0x01
|
|
line.word 0x00 "TZEINT,Trip Zone Enable Interrupt Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Int Enable" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Int Enable" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Int Enable" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Int Enable" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Int Enable" "0,1"
|
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Int Enable" "0,1"
|
|
rgroup.word (d:0x00004000+0xF00+0x93)++0x01
|
|
line.word 0x00 "TZFLG,Trip Zone Flag Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Digital Compare B Event 2 Flag" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Digital Compare B Event 1 Flag" "0,1"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Digital Compare A Event 2 Flag" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,Digital Compare A Event 1 Flag" "0,1"
|
|
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bitfld.word 0x00 2. " OST ,Trip Zones One Shot Flag" "0,1"
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bitfld.word 0x00 1. " CBC ,Trip Zones Cycle By Cycle Flag" "0,1"
|
|
bitfld.word 0x00 0. " INT ,Global Int Status Flag" "0,1"
|
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rgroup.word (d:0x00004000+0xF00+0x94)++0x01
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line.word 0x00 "TZCBCFLG,Trip Zone CBC Flag Register"
|
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bitfld.word 0x00 7. " DCBEVT2 ,Latched Status Flag for Digital Compare Output B Event 2" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Latched Status Flag for Digital Compare Output A Event 2" "0,1"
|
|
bitfld.word 0x00 5. " CBC6 ,Latched Status Flag for CBC6 Trip Latch" "0,1"
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|
bitfld.word 0x00 4. " CBC5 ,Latched Status Flag for CBC5 Trip Latch" "0,1"
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|
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|
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bitfld.word 0x00 3. " CBC4 ,Latched Status Flag for CBC4 Trip Latch" "0,1"
|
|
bitfld.word 0x00 2. " CBC3 ,Latched Status Flag for CBC3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " CBC2 ,Latched Status Flag for CBC2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " CBC1 ,Latched Status Flag for CBC1 Trip Latch" "0,1"
|
|
rgroup.word (d:0x00004000+0xF00+0x95)++0x01
|
|
line.word 0x00 "TZOSTFLG,Trip Zone OST Flag Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Latched Status Flag for Digital Compare Output B Event 1" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT1 ,Latched Status Flag for Digital Compare Output A Event 1" "0,1"
|
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bitfld.word 0x00 5. " OST6 ,Latched Status Flag for OST6 Trip Latch" "0,1"
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bitfld.word 0x00 4. " OST5 ,Latched Status Flag for OST5 Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Latched Status Flag for OST4 Trip Latch" "0,1"
|
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bitfld.word 0x00 2. " OST3 ,Latched Status Flag for OST3 Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Latched Status Flag for OST2 Trip Latch" "0,1"
|
|
bitfld.word 0x00 0. " OST1 ,Latched Status Flag for OST1 Trip Latch" "0,1"
|
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group.word (d:0x00004000+0xF00+0x97)++0x01
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line.word 0x00 "TZCLR,Trip Zone Clear Register"
|
|
bitfld.word 0x00 14.--15. " CBCPULSE ,Clear Pulse for CBC Trip Latch" "0,1,2,3"
|
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bitfld.word 0x00 6. " DCBEVT2 ,DCBEVT2 Flag Clear" "0,1"
|
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bitfld.word 0x00 5. " DCBEVT1 ,DCBEVT1 Flag Clear" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,DCAEVT2 Flag Clear" "0,1"
|
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bitfld.word 0x00 3. " DCAEVT1 ,DCAVET1 Flag Clear" "0,1"
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bitfld.word 0x00 2. " OST ,One-Shot Flag Clear" "0,1"
|
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bitfld.word 0x00 1. " CBC ,Cycle-By-Cycle Flag Clear" "0,1"
|
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bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "0,1"
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group.word (d:0x00004000+0xF00+0x98)++0x01
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line.word 0x00 "TZCBCCLR,Trip Zone CBC Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT2 ,Clear Flag for DCBEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 6. " DCAEVT2 ,Clear Flag forDCAEVT2 selected for CBC" "0,1"
|
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bitfld.word 0x00 5. " CBC6 ,Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch" "0,1"
|
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bitfld.word 0x00 4. " CBC5 ,Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch" "0,1"
|
|
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bitfld.word 0x00 3. " CBC4 ,Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " CBC3 ,Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch" "0,1"
|
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bitfld.word 0x00 1. " CBC2 ,Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch" "0,1"
|
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bitfld.word 0x00 0. " CBC1 ,Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xF00+0x99)++0x01
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line.word 0x00 "TZOSTCLR,Trip Zone OST Clear Register"
|
|
bitfld.word 0x00 7. " DCBEVT1 ,Clear Flag for DCBEVT1 selected for OST" "0,1"
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bitfld.word 0x00 6. " DCAEVT1 ,Clear Flag for DCAEVT1 selected for OST" "0,1"
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bitfld.word 0x00 5. " OST6 ,Clear Flag for Oneshot (OST6) Trip Latch" "0,1"
|
|
bitfld.word 0x00 4. " OST5 ,Clear Flag for Oneshot (OST5) Trip Latch" "0,1"
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bitfld.word 0x00 3. " OST4 ,Clear Flag for Oneshot (OST4) Trip Latch" "0,1"
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bitfld.word 0x00 2. " OST3 ,Clear Flag for Oneshot (OST3) Trip Latch" "0,1"
|
|
bitfld.word 0x00 1. " OST2 ,Clear Flag for Oneshot (OST2) Trip Latch" "0,1"
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bitfld.word 0x00 0. " OST1 ,Clear Flag for Oneshot (OST1) Trip Latch" "0,1"
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group.word (d:0x00004000+0xF00+0x9B)++0x01
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|
line.word 0x00 "TZFRC,Trip Zone Force Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Force Digital Compare B Event 2" "0,1"
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bitfld.word 0x00 5. " DCBEVT1 ,Force Digital Compare B Event 1" "0,1"
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bitfld.word 0x00 4. " DCAEVT2 ,Force Digital Compare A Event 2" "0,1"
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bitfld.word 0x00 3. " DCAEVT1 ,Force Digital Compare A Event 1" "0,1"
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bitfld.word 0x00 2. " OST ,Force Trip Zones One Shot Event" "0,1"
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bitfld.word 0x00 1. " CBC ,Force Trip Zones Cycle By Cycle Event" "0,1"
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group.word (d:0x00004000+0xF00+0xA4)++0x01
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line.word 0x00 "ETSEL,Event Trigger Selection Register"
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bitfld.word 0x00 15. " SOCBEN ,Start of Conversion B Enable" "0,1"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of Conversion B Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 11. " SOCAEN ,Start of Conversion A Enable" "0,1"
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of Conversion A Select" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6. " INTSELCMP ,EPWMxINT Compare Select" "0,1"
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bitfld.word 0x00 5. " SOCBSELCMP ,EPWMxSOCB Compare Select" "0,1"
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bitfld.word 0x00 4. " SOCASELCMP ,EPWMxSOCA Compare Select" "0,1"
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bitfld.word 0x00 3. " INTEN ,EPWMxINTn Enable" "0,1"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWMxINTn Select" "0,1,2,3,4,5,6,7"
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group.word (d:0x00004000+0xF00+0xA6)++0x01
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line.word 0x00 "ETPS,Event Trigger Pre-Scale Register"
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rbitfld.word 0x00 14.--15. " SOCBCNT ,EPWMxSOCB Counter" "0,1,2,3"
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bitfld.word 0x00 12.--13. " SOCBPRD ,EPWMxSOCB Period Select" "0,1,2,3"
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rbitfld.word 0x00 10.--11. " SOCACNT ,EPWMxSOCA Counter Register" "0,1,2,3"
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bitfld.word 0x00 8.--9. " SOCAPRD ,EPWMxSOCA Period Select" "0,1,2,3"
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bitfld.word 0x00 5. " SOCPSSEL ,EPWMxSOC A/B Pre-Scale Selection Bits" "0,1"
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bitfld.word 0x00 4. " INTPSSEL ,EPWMxINTn Pre-Scale Selection Bits" "0,1"
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rbitfld.word 0x00 2.--3. " INTCNT ,EPWMxINTn Counter Register" "0,1,2,3"
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bitfld.word 0x00 0.--1. " INTPRD ,EPWMxINTn Period Select" "0,1,2,3"
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rgroup.word (d:0x00004000+0xF00+0xA8)++0x01
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line.word 0x00 "ETFLG,Event Trigger Flag Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Flag" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Flag" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Flag" "0,1"
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group.word (d:0x00004000+0xF00+0xAA)++0x01
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line.word 0x00 "ETCLR,Event Trigger Clear Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Clear" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Clear" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Clear" "0,1"
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group.word (d:0x00004000+0xF00+0xAC)++0x01
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line.word 0x00 "ETFRC,Event Trigger Force Register"
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bitfld.word 0x00 3. " SOCB ,EPWMxSOCB Force" "0,1"
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bitfld.word 0x00 2. " SOCA ,EPWMxSOCA Force" "0,1"
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bitfld.word 0x00 0. " INT ,EPWMxINTn Force" "0,1"
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group.word (d:0x00004000+0xF00+0xAE)++0x01
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line.word 0x00 "ETINTPS,Event-Trigger Interrupt Pre-Scale Register"
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rbitfld.word 0x00 4.--7. " INTCNT2 ,EPWMxINTn Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTPRD2 ,EPWMxINTn Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xF00+0xB0)++0x01
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line.word 0x00 "ETSOCPS,Event-Trigger SOC Pre-Scale Register"
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rbitfld.word 0x00 12.--15. " SOCBCNT2 ,EPWMxSOCB Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " SOCBPRD2 ,EPWMxSOCB Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.word 0x00 4.--7. " SOCACNT2 ,EPWMxSOCA Counter Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " SOCAPRD2 ,EPWMxSOCA Period Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xF00+0xB2)++0x01
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line.word 0x00 "ETCNTINITCTL,Event-Trigger Counter Initialization Control Register"
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bitfld.word 0x00 15. " SOCBINITEN ,EPWMxSOCB Counter Initialization Enable" "0,1"
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bitfld.word 0x00 14. " SOCAINITEN ,EPWMxSOCA Counter Initialization Enable" "0,1"
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bitfld.word 0x00 13. " INTINITEN ,EPWMxINT Counter Initialization Enable" "0,1"
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bitfld.word 0x00 12. " SOCBINITFRC ,EPWMxSOCB Counter Initialization Force" "0,1"
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bitfld.word 0x00 11. " SOCAINITFRC ,EPWMxSOCA Counter Initialization Force" "0,1"
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bitfld.word 0x00 10. " INTINITFRC ,EPWMxINT Counter Initialization Force" "0,1"
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group.word (d:0x00004000+0xF00+0xB4)++0x01
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line.word 0x00 "ETCNTINIT,Event-Trigger Counter Initialization Register"
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bitfld.word 0x00 8.--11. " SOCBINIT ,EPWMxSOCB Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " SOCAINIT ,EPWMxSOCA Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " INTINIT ,EPWMxINT Counter Initialization Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xF00+0xC0)++0x01
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line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select Register"
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bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High COMP Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.word (d:0x00004000+0xF00+0xC3)++0x01
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line.word 0x00 "DCACTL,Digital Compare A Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCAEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCAEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCAEVT2 Latched signal select" "0,1"
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCAEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCAEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCAEVT1 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 4. " EVT1LATSEL ,DCAEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Enable" "0,1"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Enable" "0,1"
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bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCAEVT1 Force Sync Signal" "0,1"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0xF00+0xC4)++0x01
|
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line.word 0x00 "DCBCTL,Digital Compare B Control Register"
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rbitfld.word 0x00 15. " EVT2LAT ,Indicates the status of DCBEVT2LAT signal." "0,1"
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bitfld.word 0x00 13.--14. " EVT2LATCLRSEL ,DCBEVT2 Latched clear source select" "0,1,2,3"
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bitfld.word 0x00 12. " EVT2LATSEL ,DCBEVT2 Latched signal select" "0,1"
|
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bitfld.word 0x00 9. " EVT2FRCSYNCSEL ,DCBEVT2 Force Sync Signal" "0,1"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCBEVT2 Source Signal" "0,1"
|
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rbitfld.word 0x00 7. " EVT1LAT ,Indicates the status of DCBEVT1LAT signal." "0,1"
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bitfld.word 0x00 5.--6. " EVT1LATCLRSEL ,DCBEVT1 Latched clear source select" "0,1,2,3"
|
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bitfld.word 0x00 4. " EVT1LATSEL ,DCBEVT1 Latched signal select" "0,1"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCBEVT1 SYNC Enable" "0,1"
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCBEVT1 SOC Enable" "0,1"
|
|
bitfld.word 0x00 1. " EVT1FRCSYNCSEL ,DCBEVT1 Force Sync Signal" "0,1"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCBEVT1 Source Signal" "0,1"
|
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group.word (d:0x00004000+0xF00+0xC7)++0x01
|
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line.word 0x00 "DCFCTL,Digital Compare Filter Control Register"
|
|
rbitfld.word 0x00 13.--15. " EDGESTATUS ,Edge Status" "0,1,2,3,4,5,6,7"
|
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bitfld.word 0x00 10.--12. " EDGECOUNT ,Edge Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--9. " EDGEMODE ,Edge Mode" "0,1,2,3"
|
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bitfld.word 0x00 6. " EDGEFILTSEL ,Edge Filter Select" "0,1"
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bitfld.word 0x00 4.--5. " PULSESEL ,Pulse Select for Blanking and Capture Alignment" "0,1,2,3"
|
|
bitfld.word 0x00 3. " BLANKINV ,Blanking Window Inversion" "0,1"
|
|
bitfld.word 0x00 2. " BLANKE ,Blanking Enable/Disable" "0,1"
|
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bitfld.word 0x00 0.--1. " SRCSEL ,Filter Block Signal Source Select" "0,1,2,3"
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group.word (d:0x00004000+0xF00+0xC8)++0x01
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line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
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bitfld.word 0x00 15. " CAPMODE ,Counter Capture Mode" "0,1"
|
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bitfld.word 0x00 14. " CAPCLR ,DC Capture Latched Status Clear Flag" "0,1"
|
|
rbitfld.word 0x00 13. " CAPSTS ,Latched Status Flag for Capture Event" "0,1"
|
|
bitfld.word 0x00 1. " SHDWMODE ,Counter Capture Mode" "0,1"
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bitfld.word 0x00 0. " CAPE ,Counter Capture Enable" "0,1"
|
|
group.word (d:0x00004000+0xF00+0xC9)++0x01
|
|
line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register"
|
|
rgroup.word (d:0x00004000+0xF00+0xCA)++0x01
|
|
line.word 0x00 "DCFOFFSETCNT,Digital Compare Filter Offset Counter Register"
|
|
group.word (d:0x00004000+0xF00+0xCB)++0x01
|
|
line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register"
|
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rgroup.word (d:0x00004000+0xF00+0xCC)++0x01
|
|
line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register"
|
|
rgroup.word (d:0x00004000+0xF00+0xCF)++0x01
|
|
line.word 0x00 "DCCAP,Digital Compare Counter Capture Register"
|
|
group.word (d:0x00004000+0xF00+0xD2)++0x01
|
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line.word 0x00 "DCAHTRIPSEL,Digital Compare AH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAH Mux" "0,1"
|
|
group.word (d:0x00004000+0xF00+0xD3)++0x01
|
|
line.word 0x00 "DCALTRIPSEL,Digital Compare AL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCAL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCAL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCAL Mux" "0,1"
|
|
group.word (d:0x00004000+0xF00+0xD4)++0x01
|
|
line.word 0x00 "DCBHTRIPSEL,Digital Compare BH Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBH Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBH Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBH Mux" "0,1"
|
|
group.word (d:0x00004000+0xF00+0xD5)++0x01
|
|
line.word 0x00 "DCBLTRIPSEL,Digital Compare BL Trip Select"
|
|
bitfld.word 0x00 14. " TRIPINPUT15 ,Trip Input 15 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 13. " TRIPINPUT14 ,Trip Input 14 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 11. " TRIPINPUT12 ,Trip Input 12 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 10. " TRIPINPUT11 ,Trip Input 11 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " TRIPINPUT10 ,Trip Input 10 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 8. " TRIPINPUT9 ,Trip Input 9 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 7. " TRIPINPUT8 ,Trip Input 8 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 6. " TRIPINPUT7 ,Trip Input 7 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " TRIPINPUT6 ,Trip Input 6 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 4. " TRIPINPUT5 ,Trip Input 5 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 3. " TRIPINPUT4 ,Trip Input 4 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 2. " TRIPINPUT3 ,Trip Input 3 Select to DCBL Mux" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TRIPINPUT2 ,Trip Input 2 Select to DCBL Mux" "0,1"
|
|
bitfld.word 0x00 0. " TRIPINPUT1 ,Trip Input 1 Select to DCBL Mux" "0,1"
|
|
group.long (d:0x00004000+0xF00+0xFA)++0x03
|
|
line.long 0x00 "EPWMLOCK,EPWM Lock Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key to write to this register"
|
|
bitfld.long 0x00 4. " DCLOCK ,Digital Compare Register Set Lock" "0,1"
|
|
bitfld.long 0x00 3. " TZCLRLOCK ,TripZone Clear Register Set Lock" "0,1"
|
|
bitfld.long 0x00 2. " TZCFGLOCK ,TripZone Register Set Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " GLLOCK ,Global Load Register Set Lock" "0,1"
|
|
bitfld.long 0x00 0. " HRLOCK ,HRPWM Register Set Lock" "0,1"
|
|
rgroup.word (d:0x00004000+0xF00+0xFD)++0x01
|
|
line.word 0x00 "HWVDELVAL,Hardware Valley Mode Delay Register"
|
|
rgroup.word (d:0x00004000+0xF00+0xFE)++0x01
|
|
line.word 0x00 "VCNTVAL,Hardware Valley Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif !cpuis("F28386D*")&&!cpuis("F28384D*")&&!cpuis("F28386S*")&&!cpuis("F28384S*")
|
|
tree "EtherCAT Slave Controller (ESC)"
|
|
tree "ESCSSConfigRegs"
|
|
width 23.
|
|
group.long (d:0x00057F00+0x00)++0x03
|
|
line.long 0x00 "ESCSS_CONFIG_LOCK,EtherCATSS Configuration Lock"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " IO_CONFIG_ENABLE ,Locking the IO Configuration" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_ENABLE ,Locking writes to ECATSS" "0,1"
|
|
group.long (d:0x00057F00+0x02)++0x03
|
|
line.long 0x00 "ESCSS_MISC_IO_CONFIG,RESET_IN, EEPROM IO connections select"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 1. " EEPROM_I2C_IO_EN ,Enables the EEPROM I2C IOPAD connection" "0,1"
|
|
bitfld.long 0x00 0. " RESETIN_GPIO_EN ,Enabled ResetIN from GPIO" "0,1"
|
|
group.long (d:0x00057F00+0x04)++0x03
|
|
line.long 0x00 "ESCSS_PHY_IO_CONFIG,Control Register of ESCSS"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 6. " TX_CLK_AUTO_COMP ,Selects TX_CLK IO to do Auto compensation" "0,1"
|
|
bitfld.long 0x00 4.--5. " PHY_INTF_IOPAD_SEL ,IO Combination select for PHY Interface" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " PHY_PORT_CNT ,Number of PHY port counts" "0,1,2,3"
|
|
group.long (d:0x00057F00+0x06)++0x03
|
|
line.long 0x00 "ESCSS_SYNC_IO_CONFIG,SYNC Signals IO configurations"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " SYNC1_GPIO_EN ,SYNC1 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0x00 4.--5. " SYNC1_IOPAD_SEL ,SYNC1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SYNC0_GPIO_EN ,SYNC0 connection to OUT pad enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SYNC0_IOPAD_SEL ,SYNC0 IO PAD select option" "0,1,2,3"
|
|
group.long (d:0x00057F00+0x08)++0x03
|
|
line.long 0x00 "ESCSS_LATCH_IO_CONFIG,LATCH inputs IO pad select"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " LATCH1_GPIO_EN ,LATCH1 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x00 4.--5. " LATCH1_IOPAD_SEL ,LATCH1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x00 3. " LATCH0_GPIO_EN ,LATCH0 connection to IN pad enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " LATCH0_IOPAD_SEL ,LATCH0 IO PAD select option" "0,1,2,3"
|
|
group.long (d:0x00057F00+0x0A)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_SEL,GPIN Select between IO PAD and tieoff"
|
|
group.long (d:0x00057F00+0x0C)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_IOPAD_SEL,GPIN IO pad Select"
|
|
group.long (d:0x00057F00+0x0E)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_SEL,GPOUT IO pad connect select"
|
|
group.long (d:0x00057F00+0x10)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_IOPAD_SEL,GPOUT IO pad select"
|
|
group.long (d:0x00057F00+0x12)++0x03
|
|
line.long 0x00 "ESCSS_LED_CONFIG,Selection of LED o/p connect to IO pad"
|
|
bitfld.long 0x00 14.--15. " RUN_IOPAD_SEL ,RUN LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " ERR_IOPAD_SEL ,ERROR LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " STATE_IOPAD_SEL ,STATE LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " LINKACT1_IOPAD_SEL ,LINKACT1 LED IO PAD select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " LINKACT0_IOPAD_SEL ,LINKACT0 LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 4. " RUN ,GPIO enable for RUN LED" "0,1"
|
|
bitfld.long 0x00 3. " ERR ,GPIO enable for ERR LED" "0,1"
|
|
bitfld.long 0x00 2. " STATE ,GPIO enable for STATE LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " LINKACT1 ,GPIO enable for LINKACT1 LED" "0,1"
|
|
bitfld.long 0x00 0. " LINKACT0 ,GPIO enable for LINKACT0 LED" "0,1"
|
|
group.long (d:0x00057F00+0x14)++0x03
|
|
line.long 0x00 "ESCSS_MISC_CONFIG,Miscelleneous Configuration"
|
|
bitfld.long 0x00 6.--10. " PHY_ADDR ,PHY Address Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " PDI_EMULATION ,PDI Emulation enable" "0,1"
|
|
bitfld.long 0x00 4. " EEPROM_SIZE ,EEPROM Size bound select" "0,1"
|
|
bitfld.long 0x00 2.--3. " TX1_SHIFT_CONFIG ,TX Shift configuration for Port1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TX0_SHIFT_CONFIG ,TX Shift configuration for Port0" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ESCSSRegs"
|
|
width 25.
|
|
rgroup.long (d:0x00057E00+0x00)++0x03
|
|
line.long 0x00 "ESCSS_IPREVNUM,IP Revision Number"
|
|
bitfld.long 0x00 4.--7. " IP_REV_MAJOR ,Major IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IP_REV_MINOR ,Minor IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x00057E00+0x02)++0x03
|
|
line.long 0x00 "ESCSS_INTR_RIS,EtherCATSS Interrupt Raw Status"
|
|
bitfld.long 0x00 5. " MASTER_RESET_RIS ,ECAT RESET RIS" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_RIS ,PDI bus Timeout Error RIS" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_RIS ,DMA Done RIS" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_RIS ,EtherCATSS IRQ RIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_RIS ,SYNC1 feature RIS" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_RIS ,SYNC0 feature RIS" "0,1"
|
|
group.long (d:0x00057E00+0x04)++0x03
|
|
line.long 0x00 "ESCSS_INTR_MASK,EtherCATSS Interrupt Mask"
|
|
bitfld.long 0x00 5. " MASTER_RESET_MASK ,EtherCAT Master Reset Mask" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_MASK ,PDI Access Timeout Error Mask" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_MASK ,DMA Done Mask" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_MASK ,EtherCATSS IRQ Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_MASK ,SYNC1 feature Mask" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_MASK ,SYNC0 feature Mask" "0,1"
|
|
rgroup.long (d:0x00057E00+0x06)++0x03
|
|
line.long 0x00 "ESCSS_INTR_MIS,EtherCATSS Masked Interrupt Status"
|
|
bitfld.long 0x00 5. " MASTER_RESET_MIS ,EtherCAT Master Reset MIS" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_MIS ,PDI bus Timeout Error MIS" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_MIS ,DMA Done MIS" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_MIS ,EtherCATSS IRQ MIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_MIS ,SYNC1 feature MIS" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_MIS ,SYNC0 feature MIS" "0,1"
|
|
group.long (d:0x00057E00+0x08)++0x03
|
|
line.long 0x00 "ESCSS_INTR_CLR,EtherCATSS Interrupt Clear"
|
|
bitfld.long 0x00 5. " MASTER_RESET_CLR ,EtherCAT Master Reset Clear" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_CLR ,PDI Access Timeout Error Clear" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_CLR ,DMA Done Clear" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_CLR ,EtherCATSS IRQ Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_CLR ,SYNC1 feature Clear" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_CLR ,SYNC0 feature Clear" "0,1"
|
|
group.long (d:0x00057E00+0x0A)++0x03
|
|
line.long 0x00 "ESCSS_INTR_SET,EtherCATSS Interrupt Set to emulate"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 5. " MASTER_RESET_SET ,EtherCAT Master Reset Emulate" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_SET ,PDI Access Timeout Error Set Emulate" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_SET ,DMA Done Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " IRQ_SET ,EtherCATSS IRQ Set Emulate" "0,1"
|
|
bitfld.long 0x00 1. " SYNC1_SET ,SYNC1 Set Emulate" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_SET ,SYNC0 Set Emulate" "0,1"
|
|
group.long (d:0x00057E00+0x0C)++0x03
|
|
line.long 0x00 "ESCSS_LATCH_SEL,Select for Latch0/1 inputs and LATCHIN input"
|
|
bitfld.long 0x00 8.--12. " LATCH1_SELECT ,LATCH1 Inputs mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LATCH0_SELECT ,LATCH0 Inputs mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x00057E00+0x0E)++0x03
|
|
line.long 0x00 "ESCSS_ACCESS_CTRL,PDI interface access control config."
|
|
hexmask.long 0x00 16.--27. 1. "TIMEOUT_COUNT,Max timecount programmed and count while enabled."
|
|
bitfld.long 0x00 10. " ENABLE_PARALLEL_PORT_ACCESS ,Parallel port access enable" "0,1"
|
|
bitfld.long 0x00 9. " ENABLE_DEBUG_ACCESS ,Debug access enable" "0,1"
|
|
bitfld.long 0x00 7. " EN_TIMEOUT ,PDI Timeout enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--6. " WAIT_STATES ,Minimum Wait States for VBUS Bridge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x00057E00+0x10)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_DAT,GPIN data capture for debug and override"
|
|
group.long (d:0x00057E00+0x12)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_PIPE,GPIN pipeline select"
|
|
group.long (d:0x00057E00+0x14)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_GRP_CAP_SEL,GPIN pipe group capture trigger"
|
|
bitfld.long 0x00 12.--14. " GPI_GRP_CAP_SEL3 ,GPI31-24 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " GPI_GRP_CAP_SEL2 ,GPI23-16 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " GPI_GRP_CAP_SEL1 ,GPI15-8 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " GPI_GRP_CAP_SEL0 ,GPI7-0 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x00057E00+0x16)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_DAT,GPOUT data capture for debug and override"
|
|
group.long (d:0x00057E00+0x18)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_PIPE,GPOUT pipeline select"
|
|
group.long (d:0x00057E00+0x1A)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_GRP_CAP_SEL,GPOUT pipe group capture trigger"
|
|
bitfld.long 0x00 12.--13. " GPO_GRP_CAP_SEL3 ,GPO31-24 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPO_GRP_CAP_SEL2 ,GPO23-16 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPO_GRP_CAP_SEL1 ,GPO15-8 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPO_GRP_CAP_SEL0 ,GPO7-0 capture trigger select" "0,1,2,3"
|
|
group.long (d:0x00057E00+0x1C)++0x03
|
|
line.long 0x00 "ESCSS_MEM_TEST,Memory Test Control"
|
|
rbitfld.long 0x00 1. " MEM_INIT_DONE ,Memory Init done status" "0,1"
|
|
bitfld.long 0x00 0. " INITIATE_MEM_INIT ,Initialize memory init" "0,1"
|
|
group.long (d:0x00057E00+0x1E)++0x03
|
|
line.long 0x00 "ESCSS_RESET_DEST_CONFIG,ResetOut impact or destination config"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " DEVICE_RESET_EN ,Enables RESET_OUT to impact the device reset" "0,1"
|
|
bitfld.long 0x00 2. " CPU_INT_EN ,CPU Interrupt enable for ResetOut" "0,1"
|
|
bitfld.long 0x00 1. " CPU_NMI_EN ,CPU NMI enable for ResetOut" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " CPU_RESET_EN ,CPU reset enable for ResetOut" "0,1"
|
|
group.long (d:0x00057E00+0x20)++0x03
|
|
line.long 0x00 "ESCSS_SYNC0_CONFIG,SYNC0 Configuration for various triggers"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " uDMA_TRIG_EN ,Connects the SYNC0 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x00 3. " CM4_NVIC_EN ,Connects the SYNC0 to CM4 NVIC Interrupt" "0,1"
|
|
bitfld.long 0x00 2. " C28x_DMA_EN ,Connects the SYNC0 to C28x DMA Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CLA_INT_EN ,Connects the SYNC0 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x00 0. " C28x_PIE_EN ,Connects the SYNC0 to C28x PIE Interrupt" "0,1"
|
|
group.long (d:0x00057E00+0x22)++0x03
|
|
line.long 0x00 "ESCSS_SYNC1_CONFIG,SYNC1 Configuration for various triggers"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " uDMA_TRIG_EN ,Connects the SYNC1 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x00 3. " CM4_NVIC_EN ,Connects the SYNC1 to CM4 NVIC Interrupt" "0,1"
|
|
bitfld.long 0x00 2. " C28x_DMA_EN ,Connects the SYNC1 to C28x DMA Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CLA_INT_EN ,Connects the SYNC1 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x00 0. " C28x_PIE_EN ,Connects the SYNC1 to C28x PIE Interrupt" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "Enhanced Quadrature Encoder Pulse (eQEP)"
|
|
tree "eQEP 1"
|
|
width 14.
|
|
group.long (d:0x00005100+0x00)++0x03
|
|
line.long 0x00 "QPOSCNT,Position Counter"
|
|
group.long (d:0x00005100+0x02)++0x03
|
|
line.long 0x00 "QPOSINIT,Position Counter Init"
|
|
group.long (d:0x00005100+0x04)++0x03
|
|
line.long 0x00 "QPOSMAX,Maximum Position Count"
|
|
group.long (d:0x00005100+0x06)++0x03
|
|
line.long 0x00 "QPOSCMP,Position Compare"
|
|
rgroup.long (d:0x00005100+0x08)++0x03
|
|
line.long 0x00 "QPOSILAT,Index Position Latch"
|
|
rgroup.long (d:0x00005100+0x0A)++0x03
|
|
line.long 0x00 "QPOSSLAT,Strobe Position Latch"
|
|
rgroup.long (d:0x00005100+0x0C)++0x03
|
|
line.long 0x00 "QPOSLAT,Position Latch"
|
|
group.long (d:0x00005100+0x0E)++0x03
|
|
line.long 0x00 "QUTMR,QEP Unit Timer"
|
|
group.long (d:0x00005100+0x10)++0x03
|
|
line.long 0x00 "QUPRD,QEP Unit Period"
|
|
group.word (d:0x00005100+0x12)++0x01
|
|
line.word 0x00 "QWDTMR,QEP Watchdog Timer"
|
|
group.word (d:0x00005100+0x13)++0x01
|
|
line.word 0x00 "QWDPRD,QEP Watchdog Period"
|
|
group.word (d:0x00005100+0x14)++0x01
|
|
line.word 0x00 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "0,1"
|
|
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "0,1"
|
|
bitfld.word 0x00 11. " XCR ,External Clock Rate" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SWAP ,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "0,1"
|
|
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "0,1"
|
|
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "0,1"
|
|
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "0,1"
|
|
bitfld.word 0x00 0. " QIDIRE ,Qep Index Direction Enhancement enable" "0,1"
|
|
group.word (d:0x00005100+0x15)++0x01
|
|
line.word 0x00 "QEPCTL,QEP Control"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " PCRM ,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SEI ,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " IEI ,Index event init of position count" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 7. " SWI ,Software init position counter" "0,1"
|
|
bitfld.word 0x00 6. " SEL ,Strobe event latch" "0,1"
|
|
bitfld.word 0x00 4.--5. " IEL ,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x00 3. " QPEN ,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " QCLM ,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x00 1. " UTE ,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x00 0. " WDE ,QEP watchdog enable" "0,1"
|
|
group.word (d:0x00005100+0x16)++0x01
|
|
line.word 0x00 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x00 4.--6. " CCPS ,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00005100+0x17)++0x01
|
|
line.word 0x00 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x00 15. " PCSHDW ,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x00 14. " PCLOAD ,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "0,1"
|
|
bitfld.word 0x00 12. " PCE ,Position compare enable/disable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
group.word (d:0x00005100+0x18)++0x01
|
|
line.word 0x00 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "0,1"
|
|
rgroup.word (d:0x00005100+0x19)++0x01
|
|
line.word 0x00 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "0,1"
|
|
group.word (d:0x00005100+0x1A)++0x01
|
|
line.word 0x00 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x00 12. " QMAE ,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "0,1"
|
|
group.word (d:0x00005100+0x1B)++0x01
|
|
line.word 0x00 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x00 12. " QMAE ,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "0,1"
|
|
group.word (d:0x00005100+0x1C)++0x01
|
|
line.word 0x00 "QEPSTS,QEP Status"
|
|
bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "0,1"
|
|
rbitfld.word 0x00 6. " FIDF ,The first index marker" "0,1"
|
|
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " COEF ,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x00 2. " CDEF ,Capture direction error flag" "0,1"
|
|
bitfld.word 0x00 1. " FIMF ,First index marker flag" "0,1"
|
|
rbitfld.word 0x00 0. " PCEF ,Position counter error flag." "0,1"
|
|
group.word (d:0x00005100+0x1D)++0x01
|
|
line.word 0x00 "QCTMR,QEP Capture Timer"
|
|
group.word (d:0x00005100+0x1E)++0x01
|
|
line.word 0x00 "QCPRD,QEP Capture Period"
|
|
rgroup.word (d:0x00005100+0x1F)++0x01
|
|
line.word 0x00 "QCTMRLAT,QEP Capture Latch"
|
|
rgroup.word (d:0x00005100+0x20)++0x01
|
|
line.word 0x00 "QCPRDLAT,QEP Capture Period Latch"
|
|
rgroup.long (d:0x00005100+0x30)++0x03
|
|
line.long 0x00 "REV,QEP Revision Number"
|
|
bitfld.long 0x00 3.--5. " MINOR ,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " MAJOR ,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005100+0x32)++0x03
|
|
line.long 0x00 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x00 0.--1. " STROBESEL ,QMA Mode Select" "0,1,2,3"
|
|
group.long (d:0x00005100+0x34)++0x03
|
|
line.long 0x00 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x00 0.--2. " MODE ,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005100+0x36)++0x03
|
|
line.long 0x00 "QEPSRCSEL,QEP Source Select Register"
|
|
bitfld.long 0x00 12.--15. " QEPSSEL ,QEPS Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " QEPISEL ,QEPI Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QEPBSEL ,QEPB Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " QEPASEL ,QEPA Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eQEP 2"
|
|
width 14.
|
|
group.long (d:0x00005140+0x00)++0x03
|
|
line.long 0x00 "QPOSCNT,Position Counter"
|
|
group.long (d:0x00005140+0x02)++0x03
|
|
line.long 0x00 "QPOSINIT,Position Counter Init"
|
|
group.long (d:0x00005140+0x04)++0x03
|
|
line.long 0x00 "QPOSMAX,Maximum Position Count"
|
|
group.long (d:0x00005140+0x06)++0x03
|
|
line.long 0x00 "QPOSCMP,Position Compare"
|
|
rgroup.long (d:0x00005140+0x08)++0x03
|
|
line.long 0x00 "QPOSILAT,Index Position Latch"
|
|
rgroup.long (d:0x00005140+0x0A)++0x03
|
|
line.long 0x00 "QPOSSLAT,Strobe Position Latch"
|
|
rgroup.long (d:0x00005140+0x0C)++0x03
|
|
line.long 0x00 "QPOSLAT,Position Latch"
|
|
group.long (d:0x00005140+0x0E)++0x03
|
|
line.long 0x00 "QUTMR,QEP Unit Timer"
|
|
group.long (d:0x00005140+0x10)++0x03
|
|
line.long 0x00 "QUPRD,QEP Unit Period"
|
|
group.word (d:0x00005140+0x12)++0x01
|
|
line.word 0x00 "QWDTMR,QEP Watchdog Timer"
|
|
group.word (d:0x00005140+0x13)++0x01
|
|
line.word 0x00 "QWDPRD,QEP Watchdog Period"
|
|
group.word (d:0x00005140+0x14)++0x01
|
|
line.word 0x00 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "0,1"
|
|
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "0,1"
|
|
bitfld.word 0x00 11. " XCR ,External Clock Rate" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SWAP ,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "0,1"
|
|
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "0,1"
|
|
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "0,1"
|
|
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "0,1"
|
|
bitfld.word 0x00 0. " QIDIRE ,Qep Index Direction Enhancement enable" "0,1"
|
|
group.word (d:0x00005140+0x15)++0x01
|
|
line.word 0x00 "QEPCTL,QEP Control"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " PCRM ,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SEI ,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " IEI ,Index event init of position count" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 7. " SWI ,Software init position counter" "0,1"
|
|
bitfld.word 0x00 6. " SEL ,Strobe event latch" "0,1"
|
|
bitfld.word 0x00 4.--5. " IEL ,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x00 3. " QPEN ,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " QCLM ,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x00 1. " UTE ,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x00 0. " WDE ,QEP watchdog enable" "0,1"
|
|
group.word (d:0x00005140+0x16)++0x01
|
|
line.word 0x00 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x00 4.--6. " CCPS ,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00005140+0x17)++0x01
|
|
line.word 0x00 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x00 15. " PCSHDW ,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x00 14. " PCLOAD ,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "0,1"
|
|
bitfld.word 0x00 12. " PCE ,Position compare enable/disable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
group.word (d:0x00005140+0x18)++0x01
|
|
line.word 0x00 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "0,1"
|
|
rgroup.word (d:0x00005140+0x19)++0x01
|
|
line.word 0x00 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "0,1"
|
|
group.word (d:0x00005140+0x1A)++0x01
|
|
line.word 0x00 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x00 12. " QMAE ,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "0,1"
|
|
group.word (d:0x00005140+0x1B)++0x01
|
|
line.word 0x00 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x00 12. " QMAE ,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "0,1"
|
|
group.word (d:0x00005140+0x1C)++0x01
|
|
line.word 0x00 "QEPSTS,QEP Status"
|
|
bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "0,1"
|
|
rbitfld.word 0x00 6. " FIDF ,The first index marker" "0,1"
|
|
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " COEF ,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x00 2. " CDEF ,Capture direction error flag" "0,1"
|
|
bitfld.word 0x00 1. " FIMF ,First index marker flag" "0,1"
|
|
rbitfld.word 0x00 0. " PCEF ,Position counter error flag." "0,1"
|
|
group.word (d:0x00005140+0x1D)++0x01
|
|
line.word 0x00 "QCTMR,QEP Capture Timer"
|
|
group.word (d:0x00005140+0x1E)++0x01
|
|
line.word 0x00 "QCPRD,QEP Capture Period"
|
|
rgroup.word (d:0x00005140+0x1F)++0x01
|
|
line.word 0x00 "QCTMRLAT,QEP Capture Latch"
|
|
rgroup.word (d:0x00005140+0x20)++0x01
|
|
line.word 0x00 "QCPRDLAT,QEP Capture Period Latch"
|
|
rgroup.long (d:0x00005140+0x30)++0x03
|
|
line.long 0x00 "REV,QEP Revision Number"
|
|
bitfld.long 0x00 3.--5. " MINOR ,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " MAJOR ,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005140+0x32)++0x03
|
|
line.long 0x00 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x00 0.--1. " STROBESEL ,QMA Mode Select" "0,1,2,3"
|
|
group.long (d:0x00005140+0x34)++0x03
|
|
line.long 0x00 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x00 0.--2. " MODE ,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005140+0x36)++0x03
|
|
line.long 0x00 "QEPSRCSEL,QEP Source Select Register"
|
|
bitfld.long 0x00 12.--15. " QEPSSEL ,QEPS Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " QEPISEL ,QEPI Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QEPBSEL ,QEPB Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " QEPASEL ,QEPA Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eQEP 3"
|
|
width 14.
|
|
group.long (d:0x00005180+0x00)++0x03
|
|
line.long 0x00 "QPOSCNT,Position Counter"
|
|
group.long (d:0x00005180+0x02)++0x03
|
|
line.long 0x00 "QPOSINIT,Position Counter Init"
|
|
group.long (d:0x00005180+0x04)++0x03
|
|
line.long 0x00 "QPOSMAX,Maximum Position Count"
|
|
group.long (d:0x00005180+0x06)++0x03
|
|
line.long 0x00 "QPOSCMP,Position Compare"
|
|
rgroup.long (d:0x00005180+0x08)++0x03
|
|
line.long 0x00 "QPOSILAT,Index Position Latch"
|
|
rgroup.long (d:0x00005180+0x0A)++0x03
|
|
line.long 0x00 "QPOSSLAT,Strobe Position Latch"
|
|
rgroup.long (d:0x00005180+0x0C)++0x03
|
|
line.long 0x00 "QPOSLAT,Position Latch"
|
|
group.long (d:0x00005180+0x0E)++0x03
|
|
line.long 0x00 "QUTMR,QEP Unit Timer"
|
|
group.long (d:0x00005180+0x10)++0x03
|
|
line.long 0x00 "QUPRD,QEP Unit Period"
|
|
group.word (d:0x00005180+0x12)++0x01
|
|
line.word 0x00 "QWDTMR,QEP Watchdog Timer"
|
|
group.word (d:0x00005180+0x13)++0x01
|
|
line.word 0x00 "QWDPRD,QEP Watchdog Period"
|
|
group.word (d:0x00005180+0x14)++0x01
|
|
line.word 0x00 "QDECCTL,Quadrature Decoder Control"
|
|
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "0,1,2,3"
|
|
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "0,1"
|
|
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "0,1"
|
|
bitfld.word 0x00 11. " XCR ,External Clock Rate" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " SWAP ,CLK/DIR Signal Source for Position Counter" "0,1"
|
|
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "0,1"
|
|
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "0,1"
|
|
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "0,1"
|
|
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "0,1"
|
|
bitfld.word 0x00 0. " QIDIRE ,Qep Index Direction Enhancement enable" "0,1"
|
|
group.word (d:0x00005180+0x15)++0x01
|
|
line.word 0x00 "QEPCTL,QEP Control"
|
|
bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation mode" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. " PCRM ,Postion counter reset" "0,1,2,3"
|
|
bitfld.word 0x00 10.--11. " SEI ,Strobe event init" "0,1,2,3"
|
|
bitfld.word 0x00 8.--9. " IEI ,Index event init of position count" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 7. " SWI ,Software init position counter" "0,1"
|
|
bitfld.word 0x00 6. " SEL ,Strobe event latch" "0,1"
|
|
bitfld.word 0x00 4.--5. " IEL ,Index event latch" "0,1,2,3"
|
|
bitfld.word 0x00 3. " QPEN ,Quadrature postotion counter enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " QCLM ,QEP capture latch mode" "0,1"
|
|
bitfld.word 0x00 1. " UTE ,QEP unit timer enable" "0,1"
|
|
bitfld.word 0x00 0. " WDE ,QEP watchdog enable" "0,1"
|
|
group.word (d:0x00005180+0x16)++0x01
|
|
line.word 0x00 "QCAPCTL,Qaudrature Capture Control"
|
|
bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "0,1"
|
|
bitfld.word 0x00 4.--6. " CCPS ,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00005180+0x17)++0x01
|
|
line.word 0x00 "QPOSCTL,Position Compare Control"
|
|
bitfld.word 0x00 15. " PCSHDW ,Position compare of shadow enable" "0,1"
|
|
bitfld.word 0x00 14. " PCLOAD ,Position compare of shadow load" "0,1"
|
|
bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "0,1"
|
|
bitfld.word 0x00 12. " PCE ,Position compare enable/disable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--11. 1. "PCSPW,Position compare sync pulse width"
|
|
group.word (d:0x00005180+0x18)++0x01
|
|
line.word 0x00 "QEINT,QEP Interrupt Control"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt enable" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "0,1"
|
|
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "0,1"
|
|
rgroup.word (d:0x00005180+0x19)++0x01
|
|
line.word 0x00 "QFLG,QEP Interrupt Flag"
|
|
bitfld.word 0x00 12. " QMAE ,QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "0,1"
|
|
group.word (d:0x00005180+0x1A)++0x01
|
|
line.word 0x00 "QCLR,QEP Interrupt Clear"
|
|
bitfld.word 0x00 12. " QMAE ,Clear QMA error interrupt flag" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "0,1"
|
|
group.word (d:0x00005180+0x1B)++0x01
|
|
line.word 0x00 "QFRC,QEP Interrupt Force"
|
|
bitfld.word 0x00 12. " QMAE ,Force QMA error interrupt" "0,1"
|
|
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "0,1"
|
|
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "0,1"
|
|
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "0,1"
|
|
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "0,1"
|
|
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "0,1"
|
|
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "0,1"
|
|
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "0,1"
|
|
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "0,1"
|
|
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "0,1"
|
|
group.word (d:0x00005180+0x1C)++0x01
|
|
line.word 0x00 "QEPSTS,QEP Status"
|
|
bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "0,1"
|
|
rbitfld.word 0x00 6. " FIDF ,The first index marker" "0,1"
|
|
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "0,1"
|
|
rbitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " COEF ,Capture overflow error flag" "0,1"
|
|
bitfld.word 0x00 2. " CDEF ,Capture direction error flag" "0,1"
|
|
bitfld.word 0x00 1. " FIMF ,First index marker flag" "0,1"
|
|
rbitfld.word 0x00 0. " PCEF ,Position counter error flag." "0,1"
|
|
group.word (d:0x00005180+0x1D)++0x01
|
|
line.word 0x00 "QCTMR,QEP Capture Timer"
|
|
group.word (d:0x00005180+0x1E)++0x01
|
|
line.word 0x00 "QCPRD,QEP Capture Period"
|
|
rgroup.word (d:0x00005180+0x1F)++0x01
|
|
line.word 0x00 "QCTMRLAT,QEP Capture Latch"
|
|
rgroup.word (d:0x00005180+0x20)++0x01
|
|
line.word 0x00 "QCPRDLAT,QEP Capture Period Latch"
|
|
rgroup.long (d:0x00005180+0x30)++0x03
|
|
line.long 0x00 "REV,QEP Revision Number"
|
|
bitfld.long 0x00 3.--5. " MINOR ,Minor Revision Number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " MAJOR ,Major Revision Number" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005180+0x32)++0x03
|
|
line.long 0x00 "QEPSTROBESEL,QEP Strobe select register"
|
|
bitfld.long 0x00 0.--1. " STROBESEL ,QMA Mode Select" "0,1,2,3"
|
|
group.long (d:0x00005180+0x34)++0x03
|
|
line.long 0x00 "QMACTRL,QMA Control register"
|
|
bitfld.long 0x00 0.--2. " MODE ,QMA Mode Select" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00005180+0x36)++0x03
|
|
line.long 0x00 "QEPSRCSEL,QEP Source Select Register"
|
|
bitfld.long 0x00 12.--15. " QEPSSEL ,QEPS Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " QEPISEL ,QEPI Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " QEPBSEL ,QEPB Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " QEPASEL ,QEPA Source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Embedded Real-time Analysis and Diagnostic (ERAD)"
|
|
tree "EradGlobalRegs"
|
|
width 25.
|
|
rgroup.word (d:0x0005E800+0x00)++0x01
|
|
line.word 0x00 "GLBL_EVENT_STAT,Global Event Status Register"
|
|
bitfld.word 0x00 11. " CTM4 ,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x00 10. " CTM3 ,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x00 9. " CTM2 ,Counter Module Event Status" "0,1"
|
|
bitfld.word 0x00 8. " CTM1 ,Counter Module Event Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " HWBP8 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 6. " HWBP7 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 5. " HWBP6 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 4. " HWBP5 ,Bus Comparator Module Event Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HWBP4 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 2. " HWBP3 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 1. " HWBP2 ,Bus Comparator Module Event Status" "0,1"
|
|
bitfld.word 0x00 0. " HWBP1 ,Bus Comparator Module Event Status" "0,1"
|
|
rgroup.word (d:0x0005E800+0x02)++0x01
|
|
line.word 0x00 "GLBL_HALT_STAT,Global Halt Status Register"
|
|
bitfld.word 0x00 11. " CTM4 ,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x00 10. " CTM3 ,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x00 9. " CTM2 ,Counter Module Halt Status" "0,1"
|
|
bitfld.word 0x00 8. " CTM1 ,Counter Module Halt Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " HWBP8 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 6. " HWBP7 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 5. " HWBP6 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 4. " HWBP5 ,Bus Comparator Module Halt Status" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HWBP4 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 2. " HWBP3 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 1. " HWBP2 ,Bus Comparator Module Halt Status" "0,1"
|
|
bitfld.word 0x00 0. " HWBP1 ,Bus Comparator Module Halt Status" "0,1"
|
|
group.word (d:0x0005E800+0x04)++0x01
|
|
line.word 0x00 "GLBL_ENABLE,Global Enable Register"
|
|
bitfld.word 0x00 11. " CTM4 ,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x00 10. " CTM3 ,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x00 9. " CTM2 ,Counter Module Global Enable" "0,1"
|
|
bitfld.word 0x00 8. " CTM1 ,Counter Module Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " HWBP8 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 6. " HWBP7 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 5. " HWBP6 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 4. " HWBP5 ,Bus Comparator Module Global Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HWBP4 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 2. " HWBP3 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 1. " HWBP2 ,Bus Comparator Module Global Enable" "0,1"
|
|
bitfld.word 0x00 0. " HWBP1 ,Bus Comparator Module Global Enable" "0,1"
|
|
group.word (d:0x0005E800+0x06)++0x01
|
|
line.word 0x00 "GLBL_CTM_RESET,Global Counter Reset"
|
|
bitfld.word 0x00 3. " CTM4 ,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x00 2. " CTM3 ,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x00 1. " CTM2 ,Global Reset for the counters" "0,1"
|
|
bitfld.word 0x00 0. " CTM1 ,Global Reset for the counters" "0,1"
|
|
group.word (d:0x0005E800+0x08)++0x01
|
|
line.word 0x00 "GLBL_NMI_CTL,Global Debug NMI control"
|
|
bitfld.word 0x00 11. " CTM4 ,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 10. " CTM3 ,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 9. " CTM2 ,Counter non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 8. " CTM1 ,Counter non-maskable interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " HWBP8 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 6. " HWBP7 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " HWBP6 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 4. " HWBP5 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HWBP4 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 2. " HWBP3 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " HWBP2 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
bitfld.word 0x00 0. " HWBP1 ,Bus Comparator non-maskable interrupt enable" "0,1"
|
|
group.word (d:0x0005E800+0x0A)++0x01
|
|
line.word 0x00 "GLBL_OWNER,Global Ownership"
|
|
bitfld.word 0x00 0.--1. " OWNER ,Global Ownership Bits" "0,1,2,3"
|
|
group.long (d:0x0005E800+0x0C)++0x03
|
|
line.long 0x00 "GLBL_EVENT_AND_MASK,Global Bus Comparator Event AND Mask Register"
|
|
bitfld.long 0x00 31. " MASK4_HWBP8 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 30. " MASK4_HWBP7 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 29. " MASK4_HWBP6 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 28. " MASK4_HWBP5 ,Bus Comparator AND Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MASK4_HWBP4 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 26. " MASK4_HWBP3 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 25. " MASK4_HWBP2 ,Bus Comparator AND Event Mask4" "0,1"
|
|
bitfld.long 0x00 24. " MASK4_HWBP1 ,Bus Comparator AND Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MASK3_HWBP8 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 22. " MASK3_HWBP7 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 21. " MASK3_HWBP6 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 20. " MASK3_HWBP5 ,Bus Comparator AND Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MASK3_HWBP4 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 18. " MASK3_HWBP3 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 17. " MASK3_HWBP2 ,Bus Comparator AND Event Mask3" "0,1"
|
|
bitfld.long 0x00 16. " MASK3_HWBP1 ,Bus Comparator AND Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MASK2_HWBP8 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 14. " MASK2_HWBP7 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 13. " MASK2_HWBP6 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 12. " MASK2_HWBP5 ,Bus Comparator AND Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MASK2_HWBP4 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 10. " MASK2_HWBP3 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 9. " MASK2_HWBP2 ,Bus Comparator AND Event Mask2" "0,1"
|
|
bitfld.long 0x00 8. " MASK2_HWBP1 ,Bus Comparator AND Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MASK1_HWBP8 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 6. " MASK1_HWBP7 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 5. " MASK1_HWBP6 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 4. " MASK1_HWBP5 ,Bus Comparator AND Event Mask1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MASK1_HWBP4 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 2. " MASK1_HWBP3 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 1. " MASK1_HWBP2 ,Bus Comparator AND Event Mask1" "0,1"
|
|
bitfld.long 0x00 0. " MASK1_HWBP1 ,Bus Comparator AND Event Mask1" "0,1"
|
|
group.long (d:0x0005E800+0x0E)++0x03
|
|
line.long 0x00 "GLBL_EVENT_OR_MASK,Global Bus Comparator Event OR Mask Register"
|
|
bitfld.long 0x00 31. " MASK4_HWBP8 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 30. " MASK4_HWBP7 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 29. " MASK4_HWBP6 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 28. " MASK4_HWBP5 ,Bus Comparator OR Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MASK4_HWBP4 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 26. " MASK4_HWBP3 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 25. " MASK4_HWBP2 ,Bus Comparator OR Event Mask4" "0,1"
|
|
bitfld.long 0x00 24. " MASK4_HWBP1 ,Bus Comparator OR Event Mask4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MASK3_HWBP8 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 22. " MASK3_HWBP7 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 21. " MASK3_HWBP6 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 20. " MASK3_HWBP5 ,Bus Comparator OR Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MASK3_HWBP4 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 18. " MASK3_HWBP3 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 17. " MASK3_HWBP2 ,Bus Comparator OR Event Mask3" "0,1"
|
|
bitfld.long 0x00 16. " MASK3_HWBP1 ,Bus Comparator OR Event Mask3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MASK2_HWBP8 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 14. " MASK2_HWBP7 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 13. " MASK2_HWBP6 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 12. " MASK2_HWBP5 ,Bus Comparator OR Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MASK2_HWBP4 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 10. " MASK2_HWBP3 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 9. " MASK2_HWBP2 ,Bus Comparator OR Event Mask2" "0,1"
|
|
bitfld.long 0x00 8. " MASK2_HWBP1 ,Bus Comparator OR Event Mask2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MASK1_HWBP8 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 6. " MASK1_HWBP7 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 5. " MASK1_HWBP6 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 4. " MASK1_HWBP5 ,Bus Comparator OR Event Mask1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MASK1_HWBP4 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 2. " MASK1_HWBP3 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 1. " MASK1_HWBP2 ,Bus Comparator OR Event Mask1" "0,1"
|
|
bitfld.long 0x00 0. " MASK1_HWBP1 ,Bus Comparator OR Event Mask1" "0,1"
|
|
group.word (d:0x0005E800+0x10)++0x01
|
|
line.word 0x00 "GLBL_AND_EVENT_INT_MASK,Global AND Event Interrupt Mask Register"
|
|
bitfld.word 0x00 3. " RTOSINT_MASK4 ,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x00 2. " RTOSINT_MASK3 ,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x00 1. " RTOSINT_MASK2 ,RTOSINT generation mask for global AND events" "0,1"
|
|
bitfld.word 0x00 0. " RTOSINT_MASK1 ,RTOSINT generation mask for global AND events" "0,1"
|
|
group.word (d:0x0005E800+0x12)++0x01
|
|
line.word 0x00 "GLBL_OR_EVENT_INT_MASK,Global OR Event Interrupt Mask Register"
|
|
bitfld.word 0x00 3. " RTOSINT_MASK4 ,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x00 2. " RTOSINT_MASK3 ,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x00 1. " RTOSINT_MASK2 ,RTOSINT generation mask for global OR events" "0,1"
|
|
bitfld.word 0x00 0. " RTOSINT_MASK1 ,RTOSINT generation mask for global OR events" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp1Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x0+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x0+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x0+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x0+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x0+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp2Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x8+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x8+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x8+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x8+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x8+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp3Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x10+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x10+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x10+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x10+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x10+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp4Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x18+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x18+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x18+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x18+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x18+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp5Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x20+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x20+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x20+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x20+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x20+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp6Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x28+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x28+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x28+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x28+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x28+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp7Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x30+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x30+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x30+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x30+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x30+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradHWbp8Regs"
|
|
width 13.
|
|
group.long (d:0x0005E900+0x38+0x00)++0x03
|
|
line.long 0x00 "HWBP_MASK,HWBP Mask Register"
|
|
group.long (d:0x0005E900+0x38+0x02)++0x03
|
|
line.long 0x00 "HWBP_REF,HWBP Reference Register"
|
|
group.word (d:0x0005E900+0x38+0x04)++0x01
|
|
line.word 0x00 "HWBP_CLEAR,HWBP Clear Register"
|
|
bitfld.word 0x00 0. " EVENT_CLR ,Event Clear register" "0,1"
|
|
group.word (d:0x0005E900+0x38+0x06)++0x01
|
|
line.word 0x00 "HWBP_CNTL,HWBP Control Register"
|
|
bitfld.word 0x00 7.--9. " COMP_MODE ,Compare mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 6. " RTOSINT ,RTOSINT bit" "0,1"
|
|
bitfld.word 0x00 5. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 1.--4. " BUS_SEL ,Bus select bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x0005E900+0x38+0x07)++0x01
|
|
line.word 0x00 "HWBP_STATUS,HWBP Status Register"
|
|
bitfld.word 0x00 14.--15. " STATUS ,Status bits" "0,1,2,3"
|
|
bitfld.word 0x00 8.--13. " MODULE_ID ,Identification bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,HWBP Event Fired bits" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCounter1Regs"
|
|
width 17.
|
|
group.word (d:0x0005E980+0x0+0x00)++0x01
|
|
line.word 0x00 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x00 11. " CNT_INP_SEL_EN ,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x00 10. " RST_EN ,Enable Reset" "0,1"
|
|
bitfld.word 0x00 8. " START_STOP_CUMULATIVE ,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x00 7. " RTOSINT ,RTOSINT bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 4. " RST_ON_MATCH ,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x00 3. " EVENT_MODE ,Event mode bit" "0,1"
|
|
bitfld.word 0x00 2. " START_STOP_MODE ,Start_stop mode bit" "0,1"
|
|
rgroup.word (d:0x0005E980+0x0+0x01)++0x01
|
|
line.word 0x00 "CTM_STATUS,Counter Status Register"
|
|
bitfld.word 0x00 12.--15. " STATUS ,Status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x00 1. " OVERFLOW ,Counter Overflowed" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,Counter Event Fired bits" "0,1"
|
|
group.long (d:0x0005E980+0x0+0x02)++0x03
|
|
line.long 0x00 "CTM_REF,Counter Reference Register"
|
|
group.long (d:0x0005E980+0x0+0x04)++0x03
|
|
line.long 0x00 "CTM_COUNT,Counter Current Value Register"
|
|
group.long (d:0x0005E980+0x0+0x06)++0x03
|
|
line.long 0x00 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
group.word (d:0x0005E980+0x0+0x08)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
bitfld.word 0x00 8.--14. " STA_INP_SEL ,Counter Sart Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " CNT_INP_SEL ,Counter Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x0+0x09)++0x01
|
|
line.word 0x00 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x00 1. " OVERFLOW_CLEAR ,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_CLEAR ,Clear EVENT_FIRED" "0,1"
|
|
group.word (d:0x0005E980+0x0+0x0A)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
bitfld.word 0x00 8.--14. " RST_INP_SEL ,Counter Reset input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " STO_INP_SEL ,Counter Stop Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x0+0x0B)++0x01
|
|
line.word 0x00 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x00 13. " RST_INP_SYNCH ,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 12. " RST_INP_INV ,Reset input Invert" "0,1"
|
|
bitfld.word 0x00 9. " STO_INP_SYNCH ,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 8. " STO_INP_INV ,Stop input Invert" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " STA_INP_SYNCH ,Start input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 4. " STA_INP_INV ,Start input Invert" "0,1"
|
|
bitfld.word 0x00 1. " CTM_INP_SYNCH ,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 0. " CTM_INP_INV ,Counter Input Invert" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCounter2Regs"
|
|
width 17.
|
|
group.word (d:0x0005E980+0x10+0x00)++0x01
|
|
line.word 0x00 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x00 11. " CNT_INP_SEL_EN ,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x00 10. " RST_EN ,Enable Reset" "0,1"
|
|
bitfld.word 0x00 8. " START_STOP_CUMULATIVE ,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x00 7. " RTOSINT ,RTOSINT bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 4. " RST_ON_MATCH ,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x00 3. " EVENT_MODE ,Event mode bit" "0,1"
|
|
bitfld.word 0x00 2. " START_STOP_MODE ,Start_stop mode bit" "0,1"
|
|
rgroup.word (d:0x0005E980+0x10+0x01)++0x01
|
|
line.word 0x00 "CTM_STATUS,Counter Status Register"
|
|
bitfld.word 0x00 12.--15. " STATUS ,Status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x00 1. " OVERFLOW ,Counter Overflowed" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,Counter Event Fired bits" "0,1"
|
|
group.long (d:0x0005E980+0x10+0x02)++0x03
|
|
line.long 0x00 "CTM_REF,Counter Reference Register"
|
|
group.long (d:0x0005E980+0x10+0x04)++0x03
|
|
line.long 0x00 "CTM_COUNT,Counter Current Value Register"
|
|
group.long (d:0x0005E980+0x10+0x06)++0x03
|
|
line.long 0x00 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
group.word (d:0x0005E980+0x10+0x08)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
bitfld.word 0x00 8.--14. " STA_INP_SEL ,Counter Sart Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " CNT_INP_SEL ,Counter Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x10+0x09)++0x01
|
|
line.word 0x00 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x00 1. " OVERFLOW_CLEAR ,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_CLEAR ,Clear EVENT_FIRED" "0,1"
|
|
group.word (d:0x0005E980+0x10+0x0A)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
bitfld.word 0x00 8.--14. " RST_INP_SEL ,Counter Reset input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " STO_INP_SEL ,Counter Stop Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x10+0x0B)++0x01
|
|
line.word 0x00 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x00 13. " RST_INP_SYNCH ,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 12. " RST_INP_INV ,Reset input Invert" "0,1"
|
|
bitfld.word 0x00 9. " STO_INP_SYNCH ,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 8. " STO_INP_INV ,Stop input Invert" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " STA_INP_SYNCH ,Start input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 4. " STA_INP_INV ,Start input Invert" "0,1"
|
|
bitfld.word 0x00 1. " CTM_INP_SYNCH ,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 0. " CTM_INP_INV ,Counter Input Invert" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCounter3Regs"
|
|
width 17.
|
|
group.word (d:0x0005E980+0x20+0x00)++0x01
|
|
line.word 0x00 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x00 11. " CNT_INP_SEL_EN ,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x00 10. " RST_EN ,Enable Reset" "0,1"
|
|
bitfld.word 0x00 8. " START_STOP_CUMULATIVE ,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x00 7. " RTOSINT ,RTOSINT bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 4. " RST_ON_MATCH ,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x00 3. " EVENT_MODE ,Event mode bit" "0,1"
|
|
bitfld.word 0x00 2. " START_STOP_MODE ,Start_stop mode bit" "0,1"
|
|
rgroup.word (d:0x0005E980+0x20+0x01)++0x01
|
|
line.word 0x00 "CTM_STATUS,Counter Status Register"
|
|
bitfld.word 0x00 12.--15. " STATUS ,Status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x00 1. " OVERFLOW ,Counter Overflowed" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,Counter Event Fired bits" "0,1"
|
|
group.long (d:0x0005E980+0x20+0x02)++0x03
|
|
line.long 0x00 "CTM_REF,Counter Reference Register"
|
|
group.long (d:0x0005E980+0x20+0x04)++0x03
|
|
line.long 0x00 "CTM_COUNT,Counter Current Value Register"
|
|
group.long (d:0x0005E980+0x20+0x06)++0x03
|
|
line.long 0x00 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
group.word (d:0x0005E980+0x20+0x08)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
bitfld.word 0x00 8.--14. " STA_INP_SEL ,Counter Sart Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " CNT_INP_SEL ,Counter Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x20+0x09)++0x01
|
|
line.word 0x00 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x00 1. " OVERFLOW_CLEAR ,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_CLEAR ,Clear EVENT_FIRED" "0,1"
|
|
group.word (d:0x0005E980+0x20+0x0A)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
bitfld.word 0x00 8.--14. " RST_INP_SEL ,Counter Reset input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " STO_INP_SEL ,Counter Stop Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x20+0x0B)++0x01
|
|
line.word 0x00 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x00 13. " RST_INP_SYNCH ,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 12. " RST_INP_INV ,Reset input Invert" "0,1"
|
|
bitfld.word 0x00 9. " STO_INP_SYNCH ,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 8. " STO_INP_INV ,Stop input Invert" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " STA_INP_SYNCH ,Start input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 4. " STA_INP_INV ,Start input Invert" "0,1"
|
|
bitfld.word 0x00 1. " CTM_INP_SYNCH ,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 0. " CTM_INP_INV ,Counter Input Invert" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCounter4Regs"
|
|
width 17.
|
|
group.word (d:0x0005E980+0x30+0x00)++0x01
|
|
line.word 0x00 "CTM_CNTL,Counter Control Register"
|
|
bitfld.word 0x00 11. " CNT_INP_SEL_EN ,Counter Input Select Enable" "0,1"
|
|
bitfld.word 0x00 10. " RST_EN ,Enable Reset" "0,1"
|
|
bitfld.word 0x00 8. " START_STOP_CUMULATIVE ,Start stop cumulative bit" "0,1"
|
|
bitfld.word 0x00 7. " RTOSINT ,RTOSINT bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " STOP ,Stop bit (Halt/No Halt of CPU)" "0,1"
|
|
bitfld.word 0x00 4. " RST_ON_MATCH ,Reset_on_match bit" "0,1"
|
|
bitfld.word 0x00 3. " EVENT_MODE ,Event mode bit" "0,1"
|
|
bitfld.word 0x00 2. " START_STOP_MODE ,Start_stop mode bit" "0,1"
|
|
rgroup.word (d:0x0005E980+0x30+0x01)++0x01
|
|
line.word 0x00 "CTM_STATUS,Counter Status Register"
|
|
bitfld.word 0x00 12.--15. " STATUS ,Status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word 0x00 2.--11. 1. "MODULE_ID,Identification bits"
|
|
bitfld.word 0x00 1. " OVERFLOW ,Counter Overflowed" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_FIRED ,Counter Event Fired bits" "0,1"
|
|
group.long (d:0x0005E980+0x30+0x02)++0x03
|
|
line.long 0x00 "CTM_REF,Counter Reference Register"
|
|
group.long (d:0x0005E980+0x30+0x04)++0x03
|
|
line.long 0x00 "CTM_COUNT,Counter Current Value Register"
|
|
group.long (d:0x0005E980+0x30+0x06)++0x03
|
|
line.long 0x00 "CTM_MAX_COUNT,Counter Max Count Value Register"
|
|
group.word (d:0x0005E980+0x30+0x08)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL,Counter Input Select Register"
|
|
bitfld.word 0x00 8.--14. " STA_INP_SEL ,Counter Sart Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " CNT_INP_SEL ,Counter Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x30+0x09)++0x01
|
|
line.word 0x00 "CTM_CLEAR,Counter Clear Register"
|
|
bitfld.word 0x00 1. " OVERFLOW_CLEAR ,Clear OVERFLOW" "0,1"
|
|
bitfld.word 0x00 0. " EVENT_CLEAR ,Clear EVENT_FIRED" "0,1"
|
|
group.word (d:0x0005E980+0x30+0x0A)++0x01
|
|
line.word 0x00 "CTM_INPUT_SEL_2,Counter Input Select Extension Register"
|
|
bitfld.word 0x00 8.--14. " RST_INP_SEL ,Counter Reset input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 0.--6. " STO_INP_SEL ,Counter Stop Input Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x0005E980+0x30+0x0B)++0x01
|
|
line.word 0x00 "CTM_INPUT_COND,Counter Input Conditioning Register"
|
|
bitfld.word 0x00 13. " RST_INP_SYNCH ,Reset input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 12. " RST_INP_INV ,Reset input Invert" "0,1"
|
|
bitfld.word 0x00 9. " STO_INP_SYNCH ,Stop input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 8. " STO_INP_INV ,Stop input Invert" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " STA_INP_SYNCH ,Start input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 4. " STA_INP_INV ,Start input Invert" "0,1"
|
|
bitfld.word 0x00 1. " CTM_INP_SYNCH ,Counter input synchronizer enable" "0,1"
|
|
bitfld.word 0x00 0. " CTM_INP_INV ,Counter Input Invert" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRCGlobalRegs"
|
|
width 17.
|
|
group.word (d:0x0005EA00+0x00)++0x01
|
|
line.word 0x00 "CRC_GLOBAL_CTRL,CRC_GLOBAL_CRTL"
|
|
bitfld.word 0x00 15. " CRC8_EN ,Enable CRC Module 8" "0,1"
|
|
bitfld.word 0x00 14. " CRC7_EN ,Enable CRC Module 7" "0,1"
|
|
bitfld.word 0x00 13. " CRC6_EN ,Enable CRC Module 6" "0,1"
|
|
bitfld.word 0x00 12. " CRC5_EN ,Enable CRC Module 5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " CRC4_EN ,Enable CRC Module 4" "0,1"
|
|
bitfld.word 0x00 10. " CRC3_EN ,Enable CRC Module 3" "0,1"
|
|
bitfld.word 0x00 9. " CRC2_EN ,Enable CRC Module 2" "0,1"
|
|
bitfld.word 0x00 8. " CRC1_EN ,Enable CRC Module 1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " CRC8_INIT ,Initialize CRC Module 8" "0,1"
|
|
bitfld.word 0x00 6. " CRC7_INIT ,Initialize CRC Module 7" "0,1"
|
|
bitfld.word 0x00 5. " CRC6_INIT ,Initialize CRC Module 6" "0,1"
|
|
bitfld.word 0x00 4. " CRC5_INIT ,Initialize CRC Module 5" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " CRC4_INIT ,Initialize CRC Module 4" "0,1"
|
|
bitfld.word 0x00 2. " CRC3_INIT ,Initialize CRC Module 3" "0,1"
|
|
bitfld.word 0x00 1. " CRC2_INIT ,Initialize CRC Module 2" "0,1"
|
|
bitfld.word 0x00 0. " CRC1_INIT ,Initialize CRC Module 1" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC1Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x0+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x0+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x0+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC2Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x10+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x10+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x10+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC3Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x20+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x20+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x20+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC4Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x30+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x30+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x30+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC5Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x40+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x40+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x40+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC6Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x50+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x50+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x50+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC7Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x60+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x60+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x60+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EradCRC8Regs"
|
|
width 15.
|
|
rgroup.long (d:0x0005EA10+0x70+0x00)++0x03
|
|
line.long 0x00 "CRC_CURRENT,CRC_CURRENT"
|
|
group.long (d:0x0005EA10+0x70+0x02)++0x03
|
|
line.long 0x00 "CRC_SEED,CRC_SEED"
|
|
group.word (d:0x0005EA10+0x70+0x04)++0x01
|
|
line.word 0x00 "CRC_QUALIFIER,CRC_QUALIFIER"
|
|
bitfld.word 0x00 0.--4. " CRC_QUALIFIER ,CRC Qualifier Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Flash Module"
|
|
tree "FlashWrapperCtrlRegs"
|
|
width 15.
|
|
group.long (d:0x0005F800+0x00)++0x03
|
|
line.long 0x00 "FRDCNTL,Flash Read Control Register"
|
|
bitfld.long 0x00 8.--11. " RWAIT ,Random Read Waitstate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005F800+0x1E)++0x03
|
|
line.long 0x00 "FBAC,Flash Bank Access Control Register"
|
|
hexmask.long 0x00 0.--7. 1. "VREADST,VREAD Setup Time Count"
|
|
group.long (d:0x0005F800+0x20)++0x03
|
|
line.long 0x00 "FBFALLBACK,Flash Bank Fallback Power Register"
|
|
bitfld.long 0x00 0.--1. " BNKPWR0 ,Bank Power Mode" "0,1,2,3"
|
|
rgroup.long (d:0x0005F800+0x22)++0x03
|
|
line.long 0x00 "FBPRDY,Flash Bank Pump Ready Register"
|
|
bitfld.long 0x00 15. " PUMPRDY ,Flash Pump Active Power Mode" "0,1"
|
|
bitfld.long 0x00 0. " BANKRDY ,Flash Bank Active Power State" "0,1"
|
|
group.long (d:0x0005F800+0x24)++0x03
|
|
line.long 0x00 "FPAC1,Flash Pump Access Control Register 1"
|
|
hexmask.long 0x00 16.--27. 1. "PSLEEP,Pump Sleep Down Count"
|
|
bitfld.long 0x00 0. " PMPPWR ,Charge Pump Fallback Power Mode" "0,1"
|
|
rgroup.long (d:0x0005F800+0x2A)++0x03
|
|
line.long 0x00 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x00 12. " PGV ,Program verify" "0,1"
|
|
bitfld.long 0x00 10. " EV ,Erase verify" "0,1"
|
|
bitfld.long 0x00 8. " Busy ,Busy Bit." "0,1"
|
|
bitfld.long 0x00 7. " ERS ,Erase Active." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " PGM ,Program Active." "0,1"
|
|
bitfld.long 0x00 5. " INVDAT ,Invalid Data." "0,1"
|
|
bitfld.long 0x00 4. " CSTAT ,Command Status." "0,1"
|
|
bitfld.long 0x00 3. " VOLTSTAT ,Core Voltage Status." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ESUSP ,Erase Suspend." "0,1"
|
|
bitfld.long 0x00 1. " PSUSP ,Program Suspend." "0,1"
|
|
group.long (d:0x0005F800+0x180)++0x03
|
|
line.long 0x00 "FRD_INTF_CTRL,Flash Read Interface Control Register"
|
|
bitfld.long 0x00 1. " DATA_CACHE_EN ,Data Cache Enable" "0,1"
|
|
bitfld.long 0x00 0. " PREFETCH_EN ,Prefetch Enable" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FlashWrapperEccLogRegs"
|
|
width 22.
|
|
group.long (d:0x0005FB00+0x00)++0x03
|
|
line.long 0x00 "ECC_ENABLE,ECC Enable"
|
|
bitfld.long 0x00 0.--3. " ENABLE ,Enable ECC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005FB00+0x02)++0x03
|
|
line.long 0x00 "SINGLE_ERR_ADDR_LOW,Single Error Address Low"
|
|
group.long (d:0x0005FB00+0x04)++0x03
|
|
line.long 0x00 "SINGLE_ERR_ADDR_HIGH,Single Error Address High"
|
|
group.long (d:0x0005FB00+0x06)++0x03
|
|
line.long 0x00 "UNC_ERR_ADDR_LOW,Uncorrectable Error Address Low"
|
|
group.long (d:0x0005FB00+0x08)++0x03
|
|
line.long 0x00 "UNC_ERR_ADDR_HIGH,Uncorrectable Error Address High"
|
|
rgroup.long (d:0x0005FB00+0x0A)++0x03
|
|
line.long 0x00 "ERR_STATUS,Error Status"
|
|
bitfld.long 0x00 18. " UNC_ERR_H ,Upper 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x00 17. " FAIL_1_H ,Upper 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x00 16. " FAIL_0_H ,Upper 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
bitfld.long 0x00 2. " UNC_ERR_L ,Lower 64 bits Uncorrectable error occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FAIL_1_L ,Lower 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x00 0. " FAIL_0_L ,Lower 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
rgroup.long (d:0x0005FB00+0x0C)++0x03
|
|
line.long 0x00 "ERR_POS,Error Position"
|
|
bitfld.long 0x00 24. " ERR_TYPE_H ,Error Type in upper 64 bits" "0,1"
|
|
bitfld.long 0x00 16.--21. " ERR_POS_H ,Bit Position of Single bit Error in upper 64 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " ERR_TYPE_L ,Error Type in lower 64 bits" "0,1"
|
|
bitfld.long 0x00 0.--5. " ERR_POS_L ,Bit Position of Single bit Error in lower 64 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005FB00+0x0E)++0x03
|
|
line.long 0x00 "ERR_STATUS_CLR,Error Status Clear"
|
|
bitfld.long 0x00 18. " UNC_ERR_H_CLR ,Upper 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x00 17. " FAIL_1_H_CLR ,Upper 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x00 16. " FAIL_0_H_CLR ,Upper 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
bitfld.long 0x00 2. " UNC_ERR_L_CLR ,Lower 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FAIL_1_L_CLR ,Lower 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x00 0. " FAIL_0_L_CLR ,Lower 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
group.long (d:0x0005FB00+0x10)++0x03
|
|
line.long 0x00 "ERR_CNT,Error Control"
|
|
hexmask.long 0x00 0.--15. 1. "ERR_CNT,Error counter"
|
|
group.long (d:0x0005FB00+0x12)++0x03
|
|
line.long 0x00 "ERR_THRESHOLD,Error Threshold"
|
|
hexmask.long 0x00 0.--15. 1. "ERR_THRESHOLD,Error Threshold"
|
|
rgroup.long (d:0x0005FB00+0x14)++0x03
|
|
line.long 0x00 "ERR_INTFLG,Error Interrupt Flag"
|
|
bitfld.long 0x00 1. " UNC_ERR_INTFLG ,Uncorrectable Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR_INTFLG ,Single Error Interrupt Flag" "0,1"
|
|
group.long (d:0x0005FB00+0x16)++0x03
|
|
line.long 0x00 "ERR_INTCLR,Error Interrupt Flag Clear"
|
|
bitfld.long 0x00 1. " UNC_ERR_INTCLR ,Uncorrectable Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR_INTCLR ,Single Error Interrupt Flag Clear" "0,1"
|
|
group.long (d:0x0005FB00+0x18)++0x03
|
|
line.long 0x00 "FDATAH_TEST,Data High Test"
|
|
group.long (d:0x0005FB00+0x1A)++0x03
|
|
line.long 0x00 "FDATAL_TEST,Data Low Test"
|
|
group.long (d:0x0005FB00+0x1C)++0x03
|
|
line.long 0x00 "FADDR_TEST,ECC Test Address"
|
|
bitfld.long 0x00 16.--21. " ADDRH ,ECC Address High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 3.--15. 1. "ADDRL,ECC Address Low"
|
|
group.long (d:0x0005FB00+0x1E)++0x03
|
|
line.long 0x00 "FECC_TEST,ECC Test Address"
|
|
hexmask.long 0x00 0.--7. 1. "ECC,ECC Control Bits"
|
|
group.long (d:0x0005FB00+0x20)++0x03
|
|
line.long 0x00 "FECC_CTRL,ECC Control"
|
|
bitfld.long 0x00 2. " DO_ECC_CALC ,Enable ECC Calculation" "0,1"
|
|
bitfld.long 0x00 1. " ECC_SELECT ,ECC Bit Select" "0,1"
|
|
bitfld.long 0x00 0. " ECC_TEST_EN ,Enable ECC Test Logic" "0,1"
|
|
rgroup.long (d:0x0005FB00+0x22)++0x03
|
|
line.long 0x00 "FOUTH_TEST,Test Data Out High"
|
|
rgroup.long (d:0x0005FB00+0x24)++0x03
|
|
line.long 0x00 "FOUTL_TEST,Test Data Out Low"
|
|
rgroup.long (d:0x0005FB00+0x26)++0x03
|
|
line.long 0x00 "FECC_STATUS,ECC Status"
|
|
bitfld.long 0x00 8. " ERR_TYPE ,Holds Bit Position of 8 Check Bits of Error" "0,1"
|
|
bitfld.long 0x00 2.--7. " DATA_ERR_POS ,Holds Bit Position of Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. " UNC_ERR ,Test Result is Uncorrectable Error" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR ,Test Result is Single Bit Error" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Fast Serial Interface (FSI)"
|
|
tree "FsiTxARegs"
|
|
width 20.
|
|
group.word (d:0x00006600+0x0+0x00)++0x01
|
|
line.word 0x00 "TX_MASTER_CTRL,Transmit master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 1. " FLUSH ,Flush Operation Start" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Transmitter Master Core Reset" "0,1"
|
|
group.word (d:0x00006600+0x0+0x02)++0x01
|
|
line.word 0x00 "TX_CLK_CTRL,Transmit clock control register"
|
|
hexmask.word 0x00 2.--9. 1. "PRESCALE_VAL,Prescale value"
|
|
bitfld.word 0x00 1. " CLK_EN ,Clock Divider Enable" "0,1"
|
|
bitfld.word 0x00 0. " CLK_RST ,Soft Reset for the Clock Divider" "0,1"
|
|
group.word (d:0x00006600+0x0+0x04)++0x01
|
|
line.word 0x00 "TX_OPER_CTRL_LO,Transmit operation control register low"
|
|
bitfld.word 0x00 9. " TDM_ENABLE ,Transmit TDM Mode Enable" "0,1"
|
|
bitfld.word 0x00 8. " SEL_PLLCLK ,Input Clock Select" "0,1"
|
|
bitfld.word 0x00 7. " PING_TO_MODE ,Ping Counter Reset Mode Select" "0,1"
|
|
bitfld.word 0x00 6. " SW_CRC ,CRC Source Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " START_MODE ,Transmission Start Mode Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Transmit Data width" "0,1,2,3"
|
|
group.word (d:0x00006600+0x0+0x05)++0x01
|
|
line.word 0x00 "TX_OPER_CTRL_HI,Transmit operation control register high"
|
|
bitfld.word 0x00 7.--12. " EXT_TRIG_SEL ,External Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 6. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 5. " FORCE_ERR ,Error Frame Force" "0,1"
|
|
group.word (d:0x00006600+0x0+0x06)++0x01
|
|
line.word 0x00 "TX_FRAME_CTRL,Transmit frame control register"
|
|
bitfld.word 0x00 15. " START ,Start Transmission" "0,1"
|
|
bitfld.word 0x00 4.--7. " N_WORDS ,Number of Words to be Transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Transmit Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x0+0x07)++0x01
|
|
line.word 0x00 "TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,User Data"
|
|
bitfld.word 0x00 0.--3. " FRAME_TAG ,Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x0+0x08)++0x01
|
|
line.word 0x00 "TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Buffer Pointer Force Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006600+0x0+0x09)++0x01
|
|
line.word 0x00 "TX_BUF_PTR_STS,Transmit buffer pointer control status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Remaining Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x0+0x0A)++0x01
|
|
line.word 0x00 "TX_PING_CTRL,Transmit ping control register"
|
|
bitfld.word 0x00 3.--8. " EXT_TRIG_SEL ,External Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 2. " EXT_TRIG_EN ,External Trigger Enable" "0,1"
|
|
bitfld.word 0x00 1. " TIMER_EN ,Ping Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " CNT_RST ,Ping Counter Reset" "0,1"
|
|
group.word (d:0x00006600+0x0+0x0B)++0x01
|
|
line.word 0x00 "TX_PING_TAG,Transmit ping tag register"
|
|
bitfld.word 0x00 0.--3. " TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006600+0x0+0x0C)++0x03
|
|
line.long 0x00 "TX_PING_TO_REF,Transmit ping timeout counter reference"
|
|
rgroup.long (d:0x00006600+0x0+0x0E)++0x03
|
|
line.long 0x00 "TX_PING_TO_CNT,Transmit ping timeout current count"
|
|
group.word (d:0x00006600+0x0+0x10)++0x01
|
|
line.word 0x00 "TX_INT_CTRL,Transmit interrupt event control register"
|
|
bitfld.word 0x00 11. " INT2_EN_PING_TO ,Enable Ping Timer Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 10. " INT2_EN_BUF_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_BUF_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT1_EN_PING_TO ,Enable Ping Timer Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 2. " INT1_EN_BUF_OVERRUN ,Enable Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_BUF_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006600+0x0+0x11)++0x01
|
|
line.word 0x00 "TX_DMA_CTRL,Transmit DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
group.word (d:0x00006600+0x0+0x12)++0x01
|
|
line.word 0x00 "TX_LOCK_CTRL,Transmit lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
rgroup.word (d:0x00006600+0x0+0x14)++0x01
|
|
line.word 0x00 "TX_EVT_STS,Transmit event and error status flag register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
group.word (d:0x00006600+0x0+0x16)++0x01
|
|
line.word 0x00 "TX_EVT_CLR,Transmit event and error clear register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
group.word (d:0x00006600+0x0+0x17)++0x01
|
|
line.word 0x00 "TX_EVT_FRC,Transmit event and error flag force register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag Force" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
group.word (d:0x00006600+0x0+0x18)++0x01
|
|
line.word 0x00 "TX_USER_CRC,Transmit user-defined CRC register"
|
|
hexmask.word 0x00 0.--7. 1. "USER_CRC,User-defined CRC"
|
|
group.long (d:0x00006600+0x0+0x20)++0x03
|
|
line.long 0x00 "TX_ECC_DATA,Transmit ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
rgroup.word (d:0x00006600+0x0+0x22)++0x01
|
|
line.word 0x00 "TX_ECC_VAL,Transmit ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00006600+0x0+0x40)++0x01
|
|
line.word 0x00 "TX_BUF_BASE,Base address for transmit buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiTxBRegs"
|
|
width 20.
|
|
group.word (d:0x00006600+0x100+0x00)++0x01
|
|
line.word 0x00 "TX_MASTER_CTRL,Transmit master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 1. " FLUSH ,Flush Operation Start" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Transmitter Master Core Reset" "0,1"
|
|
group.word (d:0x00006600+0x100+0x02)++0x01
|
|
line.word 0x00 "TX_CLK_CTRL,Transmit clock control register"
|
|
hexmask.word 0x00 2.--9. 1. "PRESCALE_VAL,Prescale value"
|
|
bitfld.word 0x00 1. " CLK_EN ,Clock Divider Enable" "0,1"
|
|
bitfld.word 0x00 0. " CLK_RST ,Soft Reset for the Clock Divider" "0,1"
|
|
group.word (d:0x00006600+0x100+0x04)++0x01
|
|
line.word 0x00 "TX_OPER_CTRL_LO,Transmit operation control register low"
|
|
bitfld.word 0x00 9. " TDM_ENABLE ,Transmit TDM Mode Enable" "0,1"
|
|
bitfld.word 0x00 8. " SEL_PLLCLK ,Input Clock Select" "0,1"
|
|
bitfld.word 0x00 7. " PING_TO_MODE ,Ping Counter Reset Mode Select" "0,1"
|
|
bitfld.word 0x00 6. " SW_CRC ,CRC Source Select" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " START_MODE ,Transmission Start Mode Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Select" "0,1"
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Transmit Data width" "0,1,2,3"
|
|
group.word (d:0x00006600+0x100+0x05)++0x01
|
|
line.word 0x00 "TX_OPER_CTRL_HI,Transmit operation control register high"
|
|
bitfld.word 0x00 7.--12. " EXT_TRIG_SEL ,External Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 6. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 5. " FORCE_ERR ,Error Frame Force" "0,1"
|
|
group.word (d:0x00006600+0x100+0x06)++0x01
|
|
line.word 0x00 "TX_FRAME_CTRL,Transmit frame control register"
|
|
bitfld.word 0x00 15. " START ,Start Transmission" "0,1"
|
|
bitfld.word 0x00 4.--7. " N_WORDS ,Number of Words to be Transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Transmit Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x100+0x07)++0x01
|
|
line.word 0x00 "TX_FRAME_TAG_UDATA,Transmit frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,User Data"
|
|
bitfld.word 0x00 0.--3. " FRAME_TAG ,Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x100+0x08)++0x01
|
|
line.word 0x00 "TX_BUF_PTR_LOAD,Transmit buffer pointer control load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Buffer Pointer Force Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006600+0x100+0x09)++0x01
|
|
line.word 0x00 "TX_BUF_PTR_STS,Transmit buffer pointer control status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Remaining Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006600+0x100+0x0A)++0x01
|
|
line.word 0x00 "TX_PING_CTRL,Transmit ping control register"
|
|
bitfld.word 0x00 3.--8. " EXT_TRIG_SEL ,External Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 2. " EXT_TRIG_EN ,External Trigger Enable" "0,1"
|
|
bitfld.word 0x00 1. " TIMER_EN ,Ping Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " CNT_RST ,Ping Counter Reset" "0,1"
|
|
group.word (d:0x00006600+0x100+0x0B)++0x01
|
|
line.word 0x00 "TX_PING_TAG,Transmit ping tag register"
|
|
bitfld.word 0x00 0.--3. " TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006600+0x100+0x0C)++0x03
|
|
line.long 0x00 "TX_PING_TO_REF,Transmit ping timeout counter reference"
|
|
rgroup.long (d:0x00006600+0x100+0x0E)++0x03
|
|
line.long 0x00 "TX_PING_TO_CNT,Transmit ping timeout current count"
|
|
group.word (d:0x00006600+0x100+0x10)++0x01
|
|
line.word 0x00 "TX_INT_CTRL,Transmit interrupt event control register"
|
|
bitfld.word 0x00 11. " INT2_EN_PING_TO ,Enable Ping Timer Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 10. " INT2_EN_BUF_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_BUF_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " INT1_EN_PING_TO ,Enable Ping Timer Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 2. " INT1_EN_BUF_OVERRUN ,Enable Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_BUF_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006600+0x100+0x11)++0x01
|
|
line.word 0x00 "TX_DMA_CTRL,Transmit DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
group.word (d:0x00006600+0x100+0x12)++0x01
|
|
line.word 0x00 "TX_LOCK_CTRL,Transmit lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
rgroup.word (d:0x00006600+0x100+0x14)++0x01
|
|
line.word 0x00 "TX_EVT_STS,Transmit event and error status flag register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
group.word (d:0x00006600+0x100+0x16)++0x01
|
|
line.word 0x00 "TX_EVT_CLR,Transmit event and error clear register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag Clear" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
group.word (d:0x00006600+0x100+0x17)++0x01
|
|
line.word 0x00 "TX_EVT_FRC,Transmit event and error flag force register"
|
|
bitfld.word 0x00 3. " PING_TRIGGERED ,Ping Frame Triggered Flag Force" "0,1"
|
|
bitfld.word 0x00 2. " BUF_OVERRUN ,Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " BUF_UNDERRUN ,Buffer Underrun Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
group.word (d:0x00006600+0x100+0x18)++0x01
|
|
line.word 0x00 "TX_USER_CRC,Transmit user-defined CRC register"
|
|
hexmask.word 0x00 0.--7. 1. "USER_CRC,User-defined CRC"
|
|
group.long (d:0x00006600+0x100+0x20)++0x03
|
|
line.long 0x00 "TX_ECC_DATA,Transmit ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
rgroup.word (d:0x00006600+0x100+0x22)++0x01
|
|
line.word 0x00 "TX_ECC_VAL,Transmit ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.word (d:0x00006600+0x100+0x40)++0x01
|
|
line.word 0x00 "TX_BUF_BASE,Base address for transmit buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxARegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x0+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x0+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x0+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x0+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x0+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x0+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x0+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x0+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x0+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x0+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x0+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x0+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x0+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x0+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x0+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x0+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x0+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x0+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x0+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x0+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x0+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x0+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x0+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x0+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x0+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x0+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x0+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x0+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x0+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x0+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxBRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x100+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x100+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x100+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x100+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x100+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x100+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x100+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x100+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x100+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x100+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x100+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x100+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x100+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x100+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x100+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x100+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x100+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x100+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x100+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x100+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x100+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x100+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x100+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x100+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x100+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x100+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x100+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x100+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x100+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x100+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxCRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x200+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x200+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x200+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x200+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x200+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x200+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x200+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x200+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x200+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x200+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x200+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x200+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x200+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x200+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x200+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x200+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x200+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x200+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x200+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x200+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x200+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x200+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x200+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x200+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x200+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x200+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x200+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x200+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x200+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x200+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxDRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x300+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x300+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x300+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x300+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x300+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x300+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x300+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x300+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x300+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x300+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x300+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x300+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x300+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x300+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x300+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x300+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x300+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x300+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x300+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x300+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x300+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x300+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x300+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x300+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x300+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x300+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x300+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x300+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x300+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x300+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxERegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x400+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x400+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x400+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x400+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x400+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x400+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x400+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x400+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x400+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x400+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x400+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x400+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x400+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x400+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x400+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x400+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x400+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x400+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x400+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x400+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x400+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x400+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x400+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x400+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x400+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x400+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x400+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x400+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x400+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x400+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxFRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x500+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x500+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x500+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x500+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x500+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x500+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x500+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x500+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x500+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x500+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x500+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x500+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x500+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x500+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x500+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x500+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x500+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x500+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x500+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x500+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x500+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x500+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x500+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x500+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x500+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x500+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x500+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x500+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x500+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x500+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxGRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x600+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x600+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x600+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x600+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x600+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x600+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x600+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x600+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x600+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x600+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x600+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x600+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x600+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x600+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x600+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x600+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x600+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x600+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x600+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x600+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x600+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x600+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x600+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x600+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x600+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x600+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x600+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x600+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x600+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x600+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FsiRxHRegs"
|
|
width 20.
|
|
group.word (d:0x00006680+0x700+0x00)++0x01
|
|
line.word 0x00 "RX_MASTER_CTRL,Receive master control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 2. " SPI_PAIRING ,Clock Pairing for SPI-like Behaviour" "0,1"
|
|
bitfld.word 0x00 1. " INT_LOOPBACK ,Internal Loopback Enable" "0,1"
|
|
bitfld.word 0x00 0. " CORE_RST ,Receiver Master Core Reset" "0,1"
|
|
group.word (d:0x00006680+0x700+0x04)++0x01
|
|
line.word 0x00 "RX_OPER_CTRL,Receive operation control register"
|
|
bitfld.word 0x00 8. " PING_WD_RST_MODE ,Ping Watchdog Timeout Mode Select" "0,1"
|
|
bitfld.word 0x00 7. " ECC_SEL ,ECC Data Width Select" "0,1"
|
|
bitfld.word 0x00 3.--6. " N_WORDS ,Number of Words to be Received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 2. " SPI_MODE ,SPI Mode Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " DATA_WIDTH ,Receive Data Width Select" "0,1,2,3"
|
|
rgroup.word (d:0x00006680+0x700+0x06)++0x01
|
|
line.word 0x00 "RX_FRAME_INFO,Receive frame control register"
|
|
bitfld.word 0x00 0.--3. " FRAME_TYPE ,Received Frame Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x700+0x07)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_UDATA,Receive frame tag and user data register"
|
|
hexmask.word 0x00 8.--15. 1. "USER_DATA,Received User Data"
|
|
bitfld.word 0x00 1.--4. " FRAME_TAG ,Received Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x700+0x08)++0x01
|
|
line.word 0x00 "RX_DMA_CTRL,Receive DMA event control register"
|
|
bitfld.word 0x00 0. " DMA_EVT_EN ,DMA Event Enable" "0,1"
|
|
rgroup.word (d:0x00006680+0x700+0x0A)++0x01
|
|
line.word 0x00 "RX_EVT_STS,Receive event and error status flag register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag." "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag" "0,1"
|
|
rgroup.word (d:0x00006680+0x700+0x0B)++0x01
|
|
line.word 0x00 "RX_CRC_INFO,Receive CRC info of received and computed CRC"
|
|
hexmask.word 0x00 8.--15. 1. "CALC_CRC,Hardware Calculated CRC"
|
|
hexmask.word 0x00 0.--7. 1. "RX_CRC,Received CRC Value"
|
|
group.word (d:0x00006680+0x700+0x0C)++0x01
|
|
line.word 0x00 "RX_EVT_CLR,Receive event and error clear register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Clear" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,PING Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Clear" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Clear" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Clear" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Clear" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Clear" "0,1"
|
|
group.word (d:0x00006680+0x700+0x0D)++0x01
|
|
line.word 0x00 "RX_EVT_FRC,Receive event and error flag force register"
|
|
bitfld.word 0x00 14. " ERROR_TAG_MATCH ,Error Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 13. " DATA_TAG_MATCH ,Data Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 12. " PING_TAG_MATCH ,Ping Tag Match Flag Force" "0,1"
|
|
bitfld.word 0x00 11. " DATA_FRAME ,Data Frame Received Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " FRAME_OVERRUN ,Frame Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 9. " PING_FRAME ,Ping Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 8. " ERR_FRAME ,Error Frame Received Flag Force" "0,1"
|
|
bitfld.word 0x00 7. " BUF_UNDERRUN ,Receive Buffer Underrun Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " FRAME_DONE ,Frame Done Flag Force" "0,1"
|
|
bitfld.word 0x00 5. " BUF_OVERRUN ,Receive Buffer Overrun Flag Force" "0,1"
|
|
bitfld.word 0x00 4. " EOF_ERR ,End-of-Frame Error Flag Force" "0,1"
|
|
bitfld.word 0x00 3. " TYPE_ERR ,Frame Type Error Flag Force" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " CRC_ERR ,CRC Error Flag Force" "0,1"
|
|
bitfld.word 0x00 1. " FRAME_WD_TO ,Frame Watchdog Timeout Flag Force" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_TO ,Ping Watchdog Timeout Flag Force" "0,1"
|
|
group.word (d:0x00006680+0x700+0x0E)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_LOAD,Receive buffer pointer load register"
|
|
bitfld.word 0x00 0.--3. " BUF_PTR_LOAD ,Load value for receive buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (d:0x00006680+0x700+0x0F)++0x01
|
|
line.word 0x00 "RX_BUF_PTR_STS,Receive buffer pointer status register"
|
|
bitfld.word 0x00 8.--12. " CURR_WORD_CNT ,Available Words in Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--3. " CURR_BUF_PTR ,Current Buffer Pointer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x700+0x10)++0x01
|
|
line.word 0x00 "RX_FRAME_WD_CTRL,Receive frame watchdog control register"
|
|
bitfld.word 0x00 1. " FRAME_WD_EN ,Frame Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " FRAME_WD_CNT_RST ,Frame Watchdog Counter Reset" "0,1"
|
|
group.long (d:0x00006680+0x700+0x12)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_REF,Receive frame watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x700+0x14)++0x03
|
|
line.long 0x00 "RX_FRAME_WD_CNT,Receive frame watchdog current count"
|
|
group.word (d:0x00006680+0x700+0x16)++0x01
|
|
line.word 0x00 "RX_PING_WD_CTRL,Receive ping watchdog control register"
|
|
bitfld.word 0x00 1. " PING_WD_EN ,Ping Watchdog Counter Enable" "0,1"
|
|
bitfld.word 0x00 0. " PING_WD_RST ,Ping Watchdog Counter Reset" "0,1"
|
|
rgroup.word (d:0x00006680+0x700+0x17)++0x01
|
|
line.word 0x00 "RX_PING_TAG,Receive ping tag register"
|
|
bitfld.word 0x00 1.--4. " PING_TAG ,Ping Frame Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00006680+0x700+0x18)++0x03
|
|
line.long 0x00 "RX_PING_WD_REF,Receive ping watchdog counter reference"
|
|
rgroup.long (d:0x00006680+0x700+0x1A)++0x03
|
|
line.long 0x00 "RX_PING_WD_CNT,Receive pingwatchdog current count"
|
|
group.word (d:0x00006680+0x700+0x1C)++0x01
|
|
line.word 0x00 "RX_INT1_CTRL,Receive interrupt control register for RX_INT1"
|
|
bitfld.word 0x00 14. " INT1_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 13. " INT1_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 12. " INT1_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 11. " INT1_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT1_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 9. " INT1_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 8. " INT1_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 7. " INT1_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT1_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 5. " INT1_EN_OVERRUN ,Enable Receive Buffer Overrun Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 4. " INT1_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 3. " INT1_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT1" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT1_EN_CRC_ERR ,Enable CRC Error Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 1. " INT1_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT1" "0,1"
|
|
bitfld.word 0x00 0. " INT1_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT1" "0,1"
|
|
group.word (d:0x00006680+0x700+0x1D)++0x01
|
|
line.word 0x00 "RX_INT2_CTRL,Receive interrupt control register for RX_INT2"
|
|
bitfld.word 0x00 14. " INT2_EN_ERROR_TAG_MATCH ,Enable Error Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 13. " INT2_EN_DATA_TAG_MATCH ,Enable Data Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 12. " INT2_EN_PING_TAG_MATCH ,Enable Ping Frame Tag Matched Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 11. " INT2_EN_DATA_FRAME ,Enable Data Frame Received Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " INT2_EN_FRAME_OVERRUN ,Enable Frame Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 9. " INT2_EN_PING_FRAME ,Enable Ping Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 8. " INT2_EN_ERR_FRAME ,Enable Error Frame Received Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 7. " INT2_EN_UNDERRUN ,Enable Buffer Underrun Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " INT2_EN_FRAME_DONE ,Enable Frame Done Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 5. " INT2_EN_OVERRUN ,Enable Buffer Overrun Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 4. " INT2_EN_EOF_ERR ,Enable End-of-Frame Error Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 3. " INT2_EN_TYPE_ERR ,Enable Frame Type Error Interrupt to INT2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " INT2_EN_CRC_ERR ,Enable CRC Errror Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 1. " INT2_EN_FRAME_WD_TO ,Enable Frame Watchdog Timeout Interrupt to INT2" "0,1"
|
|
bitfld.word 0x00 0. " INT2_EN_PING_WD_TO ,Enable Ping Watchdog Timeout Interrupt to INT2" "0,1"
|
|
group.word (d:0x00006680+0x700+0x1E)++0x01
|
|
line.word 0x00 "RX_LOCK_CTRL,Receive lock control register"
|
|
hexmask.word 0x00 8.--15. 1. "KEY,Write Key"
|
|
bitfld.word 0x00 0. " LOCK ,Control Register Lock Enable" "0,1"
|
|
group.long (d:0x00006680+0x700+0x20)++0x03
|
|
line.long 0x00 "RX_ECC_DATA,Receive ECC data register"
|
|
hexmask.long 0x00 16.--31. 1. "DATA_HIGH,ECC Data Upper 16 Bits"
|
|
hexmask.long 0x00 0.--15. 1. "DATA_LOW,ECC Data Lower 16 Bits"
|
|
group.word (d:0x00006680+0x700+0x22)++0x01
|
|
line.word 0x00 "RX_ECC_VAL,Receive ECC value register"
|
|
bitfld.word 0x00 0.--6. " ECC_VAL ,Computed ECC Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006680+0x700+0x24)++0x03
|
|
line.long 0x00 "RX_ECC_SEC_DATA,Receive ECC corrected data register"
|
|
rgroup.word (d:0x00006680+0x700+0x26)++0x01
|
|
line.word 0x00 "RX_ECC_LOG,Receive ECC log and status register"
|
|
bitfld.word 0x00 1. " MBE ,Multiple Bit Errors Detected" "0,1"
|
|
bitfld.word 0x00 0. " SBE ,Single Bit Error Detected" "0,1"
|
|
group.word (d:0x00006680+0x700+0x28)++0x01
|
|
line.word 0x00 "RX_FRAME_TAG_CMP,Receive frame tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Frame Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Frame Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Frame Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x700+0x29)++0x01
|
|
line.word 0x00 "RX_PING_TAG_CMP,Receive ping tag compare register"
|
|
bitfld.word 0x00 9. " BROADCAST_EN ,Broadcast Enable" "0,1"
|
|
bitfld.word 0x00 8. " CMP_EN ,Ping Tag Compare Enable" "0,1"
|
|
bitfld.word 0x00 4.--7. " TAG_MASK ,Ping Tag Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " TAG_REF ,Ping Tag Reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006680+0x700+0x30)++0x01
|
|
line.word 0x00 "RX_DLYLINE_CTRL,Receive delay line control register"
|
|
bitfld.word 0x00 10.--14. " RXD1_DLY ,Delay Line Tap Select for RXD1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 5.--9. " RXD0_DLY ,Delay Line Tap Select for RXD0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " RXCLK_DLY ,Delay Line Tap Select for RXCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00006680+0x700+0x38)++0x03
|
|
line.long 0x00 "RX_VIS_1,Receive debug visibility register 1"
|
|
bitfld.long 0x00 3. " RX_CORE_STS ,Receiver Core Status" "0,1"
|
|
rgroup.word (d:0x00006680+0x700+0x40)++0x01
|
|
line.word 0x00 "RX_BUF_BASE,Base address for receive data buffer"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "General-Purpose Input/Output (GPIO)"
|
|
tree "GpioCtrlRegs"
|
|
width 10.
|
|
group.long (d:0x00007C00+0x00)++0x03
|
|
line.long 0x00 "GPACTRL,GPIO A Qualification Sampling Period Control (GPIO0 to 31)"
|
|
hexmask.long 0x00 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO24 to GPIO31"
|
|
hexmask.long 0x00 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO16 to GPIO23"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO8 to GPIO15"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO0 to GPIO7"
|
|
group.long (d:0x00007C00+0x02)++0x03
|
|
line.long 0x00 "GPAQSEL1,GPIO A Qualifier Select 1 Register (GPIO0 to 15)"
|
|
bitfld.long 0x00 30.--31. " GPIO15 ,Select input qualification type for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO14 ,Select input qualification type for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO13 ,Select input qualification type for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO12 ,Select input qualification type for GPIO12" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO11 ,Select input qualification type for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO10 ,Select input qualification type for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO9 ,Select input qualification type for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO8 ,Select input qualification type for GPIO8" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO7 ,Select input qualification type for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO6 ,Select input qualification type for GPIO6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO5 ,Select input qualification type for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO4 ,Select input qualification type for GPIO4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO3 ,Select input qualification type for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO2 ,Select input qualification type for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO1 ,Select input qualification type for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO0 ,Select input qualification type for GPIO0" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x04)++0x03
|
|
line.long 0x00 "GPAQSEL2,GPIO A Qualifier Select 2 Register (GPIO16 to 31)"
|
|
bitfld.long 0x00 30.--31. " GPIO31 ,Select input qualification type for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO30 ,Select input qualification type for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO29 ,Select input qualification type for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO28 ,Select input qualification type for GPIO28" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO27 ,Select input qualification type for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO26 ,Select input qualification type for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO25 ,Select input qualification type for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO24 ,Select input qualification type for GPIO24" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO23 ,Select input qualification type for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO22 ,Select input qualification type for GPIO22" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO21 ,Select input qualification type for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO20 ,Select input qualification type for GPIO20" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO19 ,Select input qualification type for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO18 ,Select input qualification type for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO17 ,Select input qualification type for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO16 ,Select input qualification type for GPIO16" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x06)++0x03
|
|
line.long 0x00 "GPAMUX1,GPIO A Mux 1 Register (GPIO0 to 15)"
|
|
bitfld.long 0x00 30.--31. " GPIO15 ,Defines pin-muxing selection for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO14 ,Defines pin-muxing selection for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO13 ,Defines pin-muxing selection for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO12 ,Defines pin-muxing selection for GPIO12" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO11 ,Defines pin-muxing selection for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO10 ,Defines pin-muxing selection for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO9 ,Defines pin-muxing selection for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO8 ,Defines pin-muxing selection for GPIO8" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO7 ,Defines pin-muxing selection for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO6 ,Defines pin-muxing selection for GPIO6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO5 ,Defines pin-muxing selection for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO4 ,Defines pin-muxing selection for GPIO4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO3 ,Defines pin-muxing selection for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO2 ,Defines pin-muxing selection for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO1 ,Defines pin-muxing selection for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO0 ,Defines pin-muxing selection for GPIO0" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x08)++0x03
|
|
line.long 0x00 "GPAMUX2,GPIO A Mux 2 Register (GPIO16 to 31)"
|
|
bitfld.long 0x00 30.--31. " GPIO31 ,Defines pin-muxing selection for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO30 ,Defines pin-muxing selection for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO29 ,Defines pin-muxing selection for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO28 ,Defines pin-muxing selection for GPIO28" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO27 ,Defines pin-muxing selection for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO26 ,Defines pin-muxing selection for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO25 ,Defines pin-muxing selection for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO24 ,Defines pin-muxing selection for GPIO24" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO23 ,Defines pin-muxing selection for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO22 ,Defines pin-muxing selection for GPIO22" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO21 ,Defines pin-muxing selection for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO20 ,Defines pin-muxing selection for GPIO20" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO19 ,Defines pin-muxing selection for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO18 ,Defines pin-muxing selection for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO17 ,Defines pin-muxing selection for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO16 ,Defines pin-muxing selection for GPIO16" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x0A)++0x03
|
|
line.long 0x00 "GPADIR,GPIO A Direction Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0x0C)++0x03
|
|
line.long 0x00 "GPAPUD,GPIO A Pull Up Disable Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x10)++0x03
|
|
line.long 0x00 "GPAINV,GPIO A Input Polarity Invert Registers (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x12)++0x03
|
|
line.long 0x00 "GPAODR,GPIO A Open Drain Output Register (GPIO0 to GPIO31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x20)++0x03
|
|
line.long 0x00 "GPAGMUX1,GPIO A Peripheral Group Mux (GPIO0 to 15)"
|
|
bitfld.long 0x00 30.--31. " GPIO15 ,Defines pin-muxing selection for GPIO15" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO14 ,Defines pin-muxing selection for GPIO14" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO13 ,Defines pin-muxing selection for GPIO13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO12 ,Defines pin-muxing selection for GPIO12" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO11 ,Defines pin-muxing selection for GPIO11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO10 ,Defines pin-muxing selection for GPIO10" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO9 ,Defines pin-muxing selection for GPIO9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO8 ,Defines pin-muxing selection for GPIO8" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO7 ,Defines pin-muxing selection for GPIO7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO6 ,Defines pin-muxing selection for GPIO6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO5 ,Defines pin-muxing selection for GPIO5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO4 ,Defines pin-muxing selection for GPIO4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO3 ,Defines pin-muxing selection for GPIO3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO2 ,Defines pin-muxing selection for GPIO2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO1 ,Defines pin-muxing selection for GPIO1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO0 ,Defines pin-muxing selection for GPIO0" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x22)++0x03
|
|
line.long 0x00 "GPAGMUX2,GPIO A Peripheral Group Mux (GPIO16 to 31)"
|
|
bitfld.long 0x00 30.--31. " GPIO31 ,Defines pin-muxing selection for GPIO31" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO30 ,Defines pin-muxing selection for GPIO30" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO29 ,Defines pin-muxing selection for GPIO29" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO28 ,Defines pin-muxing selection for GPIO28" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO27 ,Defines pin-muxing selection for GPIO27" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO26 ,Defines pin-muxing selection for GPIO26" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO25 ,Defines pin-muxing selection for GPIO25" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO24 ,Defines pin-muxing selection for GPIO24" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO23 ,Defines pin-muxing selection for GPIO23" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO22 ,Defines pin-muxing selection for GPIO22" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO21 ,Defines pin-muxing selection for GPIO21" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO20 ,Defines pin-muxing selection for GPIO20" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO19 ,Defines pin-muxing selection for GPIO19" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO18 ,Defines pin-muxing selection for GPIO18" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO17 ,Defines pin-muxing selection for GPIO17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO16 ,Defines pin-muxing selection for GPIO16" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x28)++0x03
|
|
line.long 0x00 "GPACSEL1,GPIO A Core Select Register (GPIO0 to 7)"
|
|
bitfld.long 0x00 28.--31. " GPIO7 ,GPIO7 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO6 ,GPIO6 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO5 ,GPIO5 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO4 ,GPIO4 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO3 ,GPIO3 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO2 ,GPIO2 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO1 ,GPIO1 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO0 ,GPIO0 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x2A)++0x03
|
|
line.long 0x00 "GPACSEL2,GPIO A Core Select Register (GPIO8 to 15)"
|
|
bitfld.long 0x00 28.--31. " GPIO15 ,GPIO15 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO14 ,GPIO14 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO13 ,GPIO13 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO12 ,GPIO12 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO11 ,GPIO11 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO10 ,GPIO10 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO9 ,GPIO9 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO8 ,GPIO8 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x2C)++0x03
|
|
line.long 0x00 "GPACSEL3,GPIO A Core Select Register (GPIO16 to 23)"
|
|
bitfld.long 0x00 28.--31. " GPIO23 ,GPIO23 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO22 ,GPIO22 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO21 ,GPIO21 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO20 ,GPIO20 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO19 ,GPIO19 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO18 ,GPIO18 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO17 ,GPIO17 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO16 ,GPIO16 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x2E)++0x03
|
|
line.long 0x00 "GPACSEL4,GPIO A Core Select Register (GPIO24 to 31)"
|
|
bitfld.long 0x00 28.--31. " GPIO31 ,GPIO31 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO30 ,GPIO30 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO29 ,GPIO29 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO28 ,GPIO28 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO27 ,GPIO27 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO26 ,GPIO26 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO25 ,GPIO25 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO24 ,GPIO24 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x3C)++0x03
|
|
line.long 0x00 "GPALOCK,GPIO A Lock Configuration Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x3E)++0x03
|
|
line.long 0x00 "GPACR,GPIO A Lock Commit Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Configuration lock commit bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x40)++0x03
|
|
line.long 0x00 "GPBCTRL,GPIO B Qualification Sampling Period Control (GPIO32 to 63)"
|
|
hexmask.long 0x00 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO56 to GPIO63"
|
|
hexmask.long 0x00 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO48 to GPIO55"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO40 to GPIO47"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO32 to GPIO39"
|
|
group.long (d:0x00007C00+0x42)++0x03
|
|
line.long 0x00 "GPBQSEL1,GPIO B Qualifier Select 1 Register (GPIO32 to 47)"
|
|
bitfld.long 0x00 30.--31. " GPIO47 ,Select input qualification type for GPIO47" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO46 ,Select input qualification type for GPIO46" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO45 ,Select input qualification type for GPIO45" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO44 ,Select input qualification type for GPIO44" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO43 ,Select input qualification type for GPIO43" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO42 ,Select input qualification type for GPIO42" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO41 ,Select input qualification type for GPIO41" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO40 ,Select input qualification type for GPIO40" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO39 ,Select input qualification type for GPIO39" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO38 ,Select input qualification type for GPIO38" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO37 ,Select input qualification type for GPIO37" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO36 ,Select input qualification type for GPIO36" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO35 ,Select input qualification type for GPIO35" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO34 ,Select input qualification type for GPIO34" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO33 ,Select input qualification type for GPIO33" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO32 ,Select input qualification type for GPIO32" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x44)++0x03
|
|
line.long 0x00 "GPBQSEL2,GPIO B Qualifier Select 2 Register (GPIO48 to 63)"
|
|
bitfld.long 0x00 30.--31. " GPIO63 ,Select input qualification type for GPIO63" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO62 ,Select input qualification type for GPIO62" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO61 ,Select input qualification type for GPIO61" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO60 ,Select input qualification type for GPIO60" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO59 ,Select input qualification type for GPIO59" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO58 ,Select input qualification type for GPIO58" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO57 ,Select input qualification type for GPIO57" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO56 ,Select input qualification type for GPIO56" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO55 ,Select input qualification type for GPIO55" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO54 ,Select input qualification type for GPIO54" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO53 ,Select input qualification type for GPIO53" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO52 ,Select input qualification type for GPIO52" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO51 ,Select input qualification type for GPIO51" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO50 ,Select input qualification type for GPIO50" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO49 ,Select input qualification type for GPIO49" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO48 ,Select input qualification type for GPIO48" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x46)++0x03
|
|
line.long 0x00 "GPBMUX1,GPIO B Mux 1 Register (GPIO32 to 47)"
|
|
bitfld.long 0x00 30.--31. " GPIO47 ,Defines pin-muxing selection for GPIO47" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO46 ,Defines pin-muxing selection for GPIO46" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO45 ,Defines pin-muxing selection for GPIO45" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO44 ,Defines pin-muxing selection for GPIO44" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO43 ,Defines pin-muxing selection for GPIO43" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO42 ,Defines pin-muxing selection for GPIO42" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO41 ,Defines pin-muxing selection for GPIO41" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO40 ,Defines pin-muxing selection for GPIO40" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO39 ,Defines pin-muxing selection for GPIO39" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO38 ,Defines pin-muxing selection for GPIO38" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO37 ,Defines pin-muxing selection for GPIO37" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO36 ,Defines pin-muxing selection for GPIO36" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO35 ,Defines pin-muxing selection for GPIO35" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO34 ,Defines pin-muxing selection for GPIO34" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO33 ,Defines pin-muxing selection for GPIO33" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO32 ,Defines pin-muxing selection for GPIO32" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x48)++0x03
|
|
line.long 0x00 "GPBMUX2,GPIO B Mux 2 Register (GPIO48 to 63)"
|
|
bitfld.long 0x00 30.--31. " GPIO63 ,Defines pin-muxing selection for GPIO63" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO62 ,Defines pin-muxing selection for GPIO62" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO61 ,Defines pin-muxing selection for GPIO61" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO60 ,Defines pin-muxing selection for GPIO60" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO59 ,Defines pin-muxing selection for GPIO59" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO58 ,Defines pin-muxing selection for GPIO58" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO57 ,Defines pin-muxing selection for GPIO57" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO56 ,Defines pin-muxing selection for GPIO56" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO55 ,Defines pin-muxing selection for GPIO55" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO54 ,Defines pin-muxing selection for GPIO54" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO53 ,Defines pin-muxing selection for GPIO53" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO52 ,Defines pin-muxing selection for GPIO52" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO51 ,Defines pin-muxing selection for GPIO51" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO50 ,Defines pin-muxing selection for GPIO50" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO49 ,Defines pin-muxing selection for GPIO49" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO48 ,Defines pin-muxing selection for GPIO48" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x4A)++0x03
|
|
line.long 0x00 "GPBDIR,GPIO B Direction Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0x4C)++0x03
|
|
line.long 0x00 "GPBPUD,GPIO B Pull Up Disable Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x50)++0x03
|
|
line.long 0x00 "GPBINV,GPIO B Input Polarity Invert Registers (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x52)++0x03
|
|
line.long 0x00 "GPBODR,GPIO B Open Drain Output Register (GPIO32 to GPIO63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x54)++0x03
|
|
line.long 0x00 "GPBAMSEL,GPIO B Analog Mode Select register (GPIO32 to GPIO63)"
|
|
bitfld.long 0x00 11. " GPIO43 ,Analog Mode select for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Analog Mode select for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x60)++0x03
|
|
line.long 0x00 "GPBGMUX1,GPIO B Peripheral Group Mux (GPIO32 to 47)"
|
|
bitfld.long 0x00 30.--31. " GPIO47 ,Defines pin-muxing selection for GPIO47" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO46 ,Defines pin-muxing selection for GPIO46" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO45 ,Defines pin-muxing selection for GPIO45" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO44 ,Defines pin-muxing selection for GPIO44" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO43 ,Defines pin-muxing selection for GPIO43" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO42 ,Defines pin-muxing selection for GPIO42" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO41 ,Defines pin-muxing selection for GPIO41" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO40 ,Defines pin-muxing selection for GPIO40" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO39 ,Defines pin-muxing selection for GPIO39" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO38 ,Defines pin-muxing selection for GPIO38" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO37 ,Defines pin-muxing selection for GPIO37" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO36 ,Defines pin-muxing selection for GPIO36" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO35 ,Defines pin-muxing selection for GPIO35" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO34 ,Defines pin-muxing selection for GPIO34" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO33 ,Defines pin-muxing selection for GPIO33" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO32 ,Defines pin-muxing selection for GPIO32" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x62)++0x03
|
|
line.long 0x00 "GPBGMUX2,GPIO B Peripheral Group Mux (GPIO48 to 63)"
|
|
bitfld.long 0x00 30.--31. " GPIO63 ,Defines pin-muxing selection for GPIO63" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO62 ,Defines pin-muxing selection for GPIO62" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO61 ,Defines pin-muxing selection for GPIO61" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO60 ,Defines pin-muxing selection for GPIO60" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO59 ,Defines pin-muxing selection for GPIO59" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO58 ,Defines pin-muxing selection for GPIO58" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO57 ,Defines pin-muxing selection for GPIO57" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO56 ,Defines pin-muxing selection for GPIO56" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO55 ,Defines pin-muxing selection for GPIO55" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO54 ,Defines pin-muxing selection for GPIO54" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO53 ,Defines pin-muxing selection for GPIO53" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO52 ,Defines pin-muxing selection for GPIO52" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO51 ,Defines pin-muxing selection for GPIO51" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO50 ,Defines pin-muxing selection for GPIO50" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO49 ,Defines pin-muxing selection for GPIO49" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO48 ,Defines pin-muxing selection for GPIO48" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x68)++0x03
|
|
line.long 0x00 "GPBCSEL1,GPIO B Core Select Register (GPIO32 to 39)"
|
|
bitfld.long 0x00 28.--31. " GPIO39 ,GPIO39 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO38 ,GPIO38 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO37 ,GPIO37 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO36 ,GPIO36 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO35 ,GPIO35 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO34 ,GPIO34 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO33 ,GPIO33 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO32 ,GPIO32 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x6A)++0x03
|
|
line.long 0x00 "GPBCSEL2,GPIO B Core Select Register (GPIO40 to 47)"
|
|
bitfld.long 0x00 28.--31. " GPIO47 ,GPIO47 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO46 ,GPIO46 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO45 ,GPIO45 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO44 ,GPIO44 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO43 ,GPIO43 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO42 ,GPIO42 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO41 ,GPIO41 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO40 ,GPIO40 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x6C)++0x03
|
|
line.long 0x00 "GPBCSEL3,GPIO B Core Select Register (GPIO48 to 55)"
|
|
bitfld.long 0x00 28.--31. " GPIO55 ,GPIO55 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO54 ,GPIO54 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO53 ,GPIO53 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO52 ,GPIO52 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO51 ,GPIO51 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO50 ,GPIO50 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO49 ,GPIO49 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO48 ,GPIO48 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x6E)++0x03
|
|
line.long 0x00 "GPBCSEL4,GPIO B Core Select Register (GPIO56 to 63)"
|
|
bitfld.long 0x00 28.--31. " GPIO63 ,GPIO63 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO62 ,GPIO62 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO61 ,GPIO61 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO60 ,GPIO60 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO59 ,GPIO59 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO58 ,GPIO58 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO57 ,GPIO57 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO56 ,GPIO56 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x7C)++0x03
|
|
line.long 0x00 "GPBLOCK,GPIO B Lock Configuration Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x7E)++0x03
|
|
line.long 0x00 "GPBCR,GPIO B Lock Commit Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Configuration lock commit bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x80)++0x03
|
|
line.long 0x00 "GPCCTRL,GPIO C Qualification Sampling Period Control (GPIO64 to 95)"
|
|
hexmask.long 0x00 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO88 to GPIO95"
|
|
hexmask.long 0x00 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO80 to GPIO87"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO72 to GPIO79"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO64 to GPIO71"
|
|
group.long (d:0x00007C00+0x82)++0x03
|
|
line.long 0x00 "GPCQSEL1,GPIO C Qualifier Select 1 Register (GPIO64 to 79)"
|
|
bitfld.long 0x00 30.--31. " GPIO79 ,Select input qualification type for GPIO79" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO78 ,Select input qualification type for GPIO78" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO77 ,Select input qualification type for GPIO77" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO76 ,Select input qualification type for GPIO76" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO75 ,Select input qualification type for GPIO75" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO74 ,Select input qualification type for GPIO74" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO73 ,Select input qualification type for GPIO73" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO72 ,Select input qualification type for GPIO72" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO71 ,Select input qualification type for GPIO71" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO70 ,Select input qualification type for GPIO70" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO69 ,Select input qualification type for GPIO69" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO68 ,Select input qualification type for GPIO68" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO67 ,Select input qualification type for GPIO67" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO66 ,Select input qualification type for GPIO66" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO65 ,Select input qualification type for GPIO65" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO64 ,Select input qualification type for GPIO64" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x84)++0x03
|
|
line.long 0x00 "GPCQSEL2,GPIO C Qualifier Select 2 Register (GPIO80 to 95)"
|
|
bitfld.long 0x00 30.--31. " GPIO95 ,Select input qualification type for GPIO95" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO94 ,Select input qualification type for GPIO94" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO93 ,Select input qualification type for GPIO93" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO92 ,Select input qualification type for GPIO92" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO91 ,Select input qualification type for GPIO91" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO90 ,Select input qualification type for GPIO90" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO89 ,Select input qualification type for GPIO89" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO88 ,Select input qualification type for GPIO88" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO87 ,Select input qualification type for GPIO87" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO86 ,Select input qualification type for GPIO86" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO85 ,Select input qualification type for GPIO85" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO84 ,Select input qualification type for GPIO84" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO83 ,Select input qualification type for GPIO83" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO82 ,Select input qualification type for GPIO82" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO81 ,Select input qualification type for GPIO81" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO80 ,Select input qualification type for GPIO80" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x86)++0x03
|
|
line.long 0x00 "GPCMUX1,GPIO C Mux 1 Register (GPIO64 to 79)"
|
|
bitfld.long 0x00 30.--31. " GPIO79 ,Defines pin-muxing selection for GPIO79" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO78 ,Defines pin-muxing selection for GPIO78" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO77 ,Defines pin-muxing selection for GPIO77" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO76 ,Defines pin-muxing selection for GPIO76" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO75 ,Defines pin-muxing selection for GPIO75" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO74 ,Defines pin-muxing selection for GPIO74" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO73 ,Defines pin-muxing selection for GPIO73" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO72 ,Defines pin-muxing selection for GPIO72" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO71 ,Defines pin-muxing selection for GPIO71" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO70 ,Defines pin-muxing selection for GPIO70" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO69 ,Defines pin-muxing selection for GPIO69" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO68 ,Defines pin-muxing selection for GPIO68" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO67 ,Defines pin-muxing selection for GPIO67" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO66 ,Defines pin-muxing selection for GPIO66" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO65 ,Defines pin-muxing selection for GPIO65" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO64 ,Defines pin-muxing selection for GPIO64" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x88)++0x03
|
|
line.long 0x00 "GPCMUX2,GPIO C Mux 2 Register (GPIO80 to 95)"
|
|
bitfld.long 0x00 30.--31. " GPIO95 ,Defines pin-muxing selection for GPIO95" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO94 ,Defines pin-muxing selection for GPIO94" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO93 ,Defines pin-muxing selection for GPIO93" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO92 ,Defines pin-muxing selection for GPIO92" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO91 ,Defines pin-muxing selection for GPIO91" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO90 ,Defines pin-muxing selection for GPIO90" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO89 ,Defines pin-muxing selection for GPIO89" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO88 ,Defines pin-muxing selection for GPIO88" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO87 ,Defines pin-muxing selection for GPIO87" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO86 ,Defines pin-muxing selection for GPIO86" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO85 ,Defines pin-muxing selection for GPIO85" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO84 ,Defines pin-muxing selection for GPIO84" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO83 ,Defines pin-muxing selection for GPIO83" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO82 ,Defines pin-muxing selection for GPIO82" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO81 ,Defines pin-muxing selection for GPIO81" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO80 ,Defines pin-muxing selection for GPIO80" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x8A)++0x03
|
|
line.long 0x00 "GPCDIR,GPIO C Direction Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0x8C)++0x03
|
|
line.long 0x00 "GPCPUD,GPIO C Pull Up Disable Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x90)++0x03
|
|
line.long 0x00 "GPCINV,GPIO C Input Polarity Invert Registers (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x92)++0x03
|
|
line.long 0x00 "GPCODR,GPIO C Open Drain Output Register (GPIO64 to GPIO95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xA0)++0x03
|
|
line.long 0x00 "GPCGMUX1,GPIO C Peripheral Group Mux (GPIO64 to 79)"
|
|
bitfld.long 0x00 30.--31. " GPIO79 ,Defines pin-muxing selection for GPIO79" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO78 ,Defines pin-muxing selection for GPIO78" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO77 ,Defines pin-muxing selection for GPIO77" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO76 ,Defines pin-muxing selection for GPIO76" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO75 ,Defines pin-muxing selection for GPIO75" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO74 ,Defines pin-muxing selection for GPIO74" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO73 ,Defines pin-muxing selection for GPIO73" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO72 ,Defines pin-muxing selection for GPIO72" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO71 ,Defines pin-muxing selection for GPIO71" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO70 ,Defines pin-muxing selection for GPIO70" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO69 ,Defines pin-muxing selection for GPIO69" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO68 ,Defines pin-muxing selection for GPIO68" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO67 ,Defines pin-muxing selection for GPIO67" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO66 ,Defines pin-muxing selection for GPIO66" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO65 ,Defines pin-muxing selection for GPIO65" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO64 ,Defines pin-muxing selection for GPIO64" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xA2)++0x03
|
|
line.long 0x00 "GPCGMUX2,GPIO C Peripheral Group Mux (GPIO80 to 95)"
|
|
bitfld.long 0x00 30.--31. " GPIO95 ,Defines pin-muxing selection for GPIO95" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO94 ,Defines pin-muxing selection for GPIO94" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO93 ,Defines pin-muxing selection for GPIO93" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO92 ,Defines pin-muxing selection for GPIO92" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO91 ,Defines pin-muxing selection for GPIO91" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO90 ,Defines pin-muxing selection for GPIO90" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO89 ,Defines pin-muxing selection for GPIO89" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO88 ,Defines pin-muxing selection for GPIO88" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO87 ,Defines pin-muxing selection for GPIO87" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO86 ,Defines pin-muxing selection for GPIO86" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO85 ,Defines pin-muxing selection for GPIO85" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO84 ,Defines pin-muxing selection for GPIO84" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO83 ,Defines pin-muxing selection for GPIO83" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO82 ,Defines pin-muxing selection for GPIO82" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO81 ,Defines pin-muxing selection for GPIO81" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO80 ,Defines pin-muxing selection for GPIO80" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xA8)++0x03
|
|
line.long 0x00 "GPCCSEL1,GPIO C Core Select Register (GPIO64 to 71)"
|
|
bitfld.long 0x00 28.--31. " GPIO71 ,GPIO71 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO70 ,GPIO70 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO69 ,GPIO69 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO68 ,GPIO68 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO67 ,GPIO67 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO66 ,GPIO66 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO65 ,GPIO65 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO64 ,GPIO64 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xAA)++0x03
|
|
line.long 0x00 "GPCCSEL2,GPIO C Core Select Register (GPIO72 to 79)"
|
|
bitfld.long 0x00 28.--31. " GPIO79 ,GPIO79 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO78 ,GPIO78 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO77 ,GPIO77 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO76 ,GPIO76 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO75 ,GPIO75 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO74 ,GPIO74 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO73 ,GPIO73 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO72 ,GPIO72 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xAC)++0x03
|
|
line.long 0x00 "GPCCSEL3,GPIO C Core Select Register (GPIO80 to 87)"
|
|
bitfld.long 0x00 28.--31. " GPIO87 ,GPIO87 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO86 ,GPIO86 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO85 ,GPIO85 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO84 ,GPIO84 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO83 ,GPIO83 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO82 ,GPIO82 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO81 ,GPIO81 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO80 ,GPIO80 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xAE)++0x03
|
|
line.long 0x00 "GPCCSEL4,GPIO C Core Select Register (GPIO88 to 95)"
|
|
bitfld.long 0x00 28.--31. " GPIO95 ,GPIO95 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO94 ,GPIO94 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO93 ,GPIO93 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO92 ,GPIO92 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO91 ,GPIO91 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO90 ,GPIO90 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO89 ,GPIO89 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO88 ,GPIO88 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xBC)++0x03
|
|
line.long 0x00 "GPCLOCK,GPIO C Lock Configuration Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xBE)++0x03
|
|
line.long 0x00 "GPCCR,GPIO C Lock Commit Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Configuration lock commit bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xC0)++0x03
|
|
line.long 0x00 "GPDCTRL,GPIO D Qualification Sampling Period Control (GPIO96 to 127)"
|
|
hexmask.long 0x00 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO120 to GPIO127"
|
|
hexmask.long 0x00 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO112 to GPIO119"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO104 to GPIO111"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO96 to GPIO103"
|
|
group.long (d:0x00007C00+0xC2)++0x03
|
|
line.long 0x00 "GPDQSEL1,GPIO D Qualifier Select 1 Register (GPIO96 to 111)"
|
|
bitfld.long 0x00 30.--31. " GPIO111 ,Select input qualification type for GPIO111" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO110 ,Select input qualification type for GPIO110" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO109 ,Select input qualification type for GPIO109" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO108 ,Select input qualification type for GPIO108" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO107 ,Select input qualification type for GPIO107" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO106 ,Select input qualification type for GPIO106" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO105 ,Select input qualification type for GPIO105" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO104 ,Select input qualification type for GPIO104" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO103 ,Select input qualification type for GPIO103" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO102 ,Select input qualification type for GPIO102" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO101 ,Select input qualification type for GPIO101" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO100 ,Select input qualification type for GPIO100" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO99 ,Select input qualification type for GPIO99" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO98 ,Select input qualification type for GPIO98" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO97 ,Select input qualification type for GPIO97" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO96 ,Select input qualification type for GPIO96" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xC4)++0x03
|
|
line.long 0x00 "GPDQSEL2,GPIO D Qualifier Select 2 Register (GPIO112 to 127)"
|
|
bitfld.long 0x00 30.--31. " GPIO127 ,Select input qualification type for GPIO127" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO126 ,Select input qualification type for GPIO126" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO125 ,Select input qualification type for GPIO125" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO124 ,Select input qualification type for GPIO124" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO123 ,Select input qualification type for GPIO123" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO122 ,Select input qualification type for GPIO122" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO121 ,Select input qualification type for GPIO121" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO120 ,Select input qualification type for GPIO120" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO119 ,Select input qualification type for GPIO119" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO118 ,Select input qualification type for GPIO118" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO117 ,Select input qualification type for GPIO117" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO116 ,Select input qualification type for GPIO116" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO115 ,Select input qualification type for GPIO115" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO114 ,Select input qualification type for GPIO114" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO113 ,Select input qualification type for GPIO113" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO112 ,Select input qualification type for GPIO112" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xC6)++0x03
|
|
line.long 0x00 "GPDMUX1,GPIO D Mux 1 Register (GPIO96 to 111)"
|
|
bitfld.long 0x00 30.--31. " GPIO111 ,Defines pin-muxing selection for GPIO111" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO110 ,Defines pin-muxing selection for GPIO110" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO109 ,Defines pin-muxing selection for GPIO109" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO108 ,Defines pin-muxing selection for GPIO108" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO107 ,Defines pin-muxing selection for GPIO107" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO106 ,Defines pin-muxing selection for GPIO106" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO105 ,Defines pin-muxing selection for GPIO105" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO104 ,Defines pin-muxing selection for GPIO104" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO103 ,Defines pin-muxing selection for GPIO103" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO102 ,Defines pin-muxing selection for GPIO102" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO101 ,Defines pin-muxing selection for GPIO101" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO100 ,Defines pin-muxing selection for GPIO100" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO99 ,Defines pin-muxing selection for GPIO99" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO98 ,Defines pin-muxing selection for GPIO98" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO97 ,Defines pin-muxing selection for GPIO97" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO96 ,Defines pin-muxing selection for GPIO96" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xC8)++0x03
|
|
line.long 0x00 "GPDMUX2,GPIO D Mux 2 Register (GPIO112 to 127)"
|
|
bitfld.long 0x00 30.--31. " GPIO127 ,Defines pin-muxing selection for GPIO127" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO126 ,Defines pin-muxing selection for GPIO126" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO125 ,Defines pin-muxing selection for GPIO125" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO124 ,Defines pin-muxing selection for GPIO124" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO123 ,Defines pin-muxing selection for GPIO123" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO122 ,Defines pin-muxing selection for GPIO122" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO121 ,Defines pin-muxing selection for GPIO121" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO120 ,Defines pin-muxing selection for GPIO120" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO119 ,Defines pin-muxing selection for GPIO119" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO118 ,Defines pin-muxing selection for GPIO118" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO117 ,Defines pin-muxing selection for GPIO117" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO116 ,Defines pin-muxing selection for GPIO116" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO115 ,Defines pin-muxing selection for GPIO115" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO114 ,Defines pin-muxing selection for GPIO114" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO113 ,Defines pin-muxing selection for GPIO113" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO112 ,Defines pin-muxing selection for GPIO112" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xCA)++0x03
|
|
line.long 0x00 "GPDDIR,GPIO D Direction Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0xCC)++0x03
|
|
line.long 0x00 "GPDPUD,GPIO D Pull Up Disable Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xD0)++0x03
|
|
line.long 0x00 "GPDINV,GPIO D Input Polarity Invert Registers (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xD2)++0x03
|
|
line.long 0x00 "GPDODR,GPIO D Open Drain Output Register (GPIO96 to GPIO127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xE0)++0x03
|
|
line.long 0x00 "GPDGMUX1,GPIO D Peripheral Group Mux (GPIO96 to 111)"
|
|
bitfld.long 0x00 30.--31. " GPIO111 ,Defines pin-muxing selection for GPIO111" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO110 ,Defines pin-muxing selection for GPIO110" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO109 ,Defines pin-muxing selection for GPIO109" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO108 ,Defines pin-muxing selection for GPIO108" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO107 ,Defines pin-muxing selection for GPIO107" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO106 ,Defines pin-muxing selection for GPIO106" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO105 ,Defines pin-muxing selection for GPIO105" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO104 ,Defines pin-muxing selection for GPIO104" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO103 ,Defines pin-muxing selection for GPIO103" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO102 ,Defines pin-muxing selection for GPIO102" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO101 ,Defines pin-muxing selection for GPIO101" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO100 ,Defines pin-muxing selection for GPIO100" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO99 ,Defines pin-muxing selection for GPIO99" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO98 ,Defines pin-muxing selection for GPIO98" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO97 ,Defines pin-muxing selection for GPIO97" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO96 ,Defines pin-muxing selection for GPIO96" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xE2)++0x03
|
|
line.long 0x00 "GPDGMUX2,GPIO D Peripheral Group Mux (GPIO112 to 127)"
|
|
bitfld.long 0x00 30.--31. " GPIO127 ,Defines pin-muxing selection for GPIO127" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO126 ,Defines pin-muxing selection for GPIO126" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO125 ,Defines pin-muxing selection for GPIO125" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO124 ,Defines pin-muxing selection for GPIO124" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO123 ,Defines pin-muxing selection for GPIO123" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO122 ,Defines pin-muxing selection for GPIO122" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO121 ,Defines pin-muxing selection for GPIO121" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO120 ,Defines pin-muxing selection for GPIO120" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO119 ,Defines pin-muxing selection for GPIO119" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO118 ,Defines pin-muxing selection for GPIO118" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO117 ,Defines pin-muxing selection for GPIO117" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO116 ,Defines pin-muxing selection for GPIO116" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO115 ,Defines pin-muxing selection for GPIO115" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO114 ,Defines pin-muxing selection for GPIO114" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO113 ,Defines pin-muxing selection for GPIO113" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO112 ,Defines pin-muxing selection for GPIO112" "0,1,2,3"
|
|
group.long (d:0x00007C00+0xE8)++0x03
|
|
line.long 0x00 "GPDCSEL1,GPIO D Core Select Register (GPIO96 to 103)"
|
|
bitfld.long 0x00 28.--31. " GPIO103 ,GPIO103 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO102 ,GPIO102 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO101 ,GPIO101 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO100 ,GPIO100 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO99 ,GPIO99 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO98 ,GPIO98 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO97 ,GPIO97 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO96 ,GPIO96 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xEA)++0x03
|
|
line.long 0x00 "GPDCSEL2,GPIO D Core Select Register (GPIO104 to 111)"
|
|
bitfld.long 0x00 28.--31. " GPIO111 ,GPIO111 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO110 ,GPIO110 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO109 ,GPIO109 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO108 ,GPIO108 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO107 ,GPIO107 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO106 ,GPIO106 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO105 ,GPIO105 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO104 ,GPIO104 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xEC)++0x03
|
|
line.long 0x00 "GPDCSEL3,GPIO D Core Select Register (GPIO112 to 119)"
|
|
bitfld.long 0x00 28.--31. " GPIO119 ,GPIO119 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO118 ,GPIO118 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO117 ,GPIO117 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO116 ,GPIO116 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO115 ,GPIO115 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO114 ,GPIO114 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO113 ,GPIO113 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO112 ,GPIO112 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xEE)++0x03
|
|
line.long 0x00 "GPDCSEL4,GPIO D Core Select Register (GPIO120 to 127)"
|
|
bitfld.long 0x00 28.--31. " GPIO127 ,GPIO127 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO126 ,GPIO126 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO125 ,GPIO125 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO124 ,GPIO124 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO123 ,GPIO123 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO122 ,GPIO122 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO121 ,GPIO121 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO120 ,GPIO120 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0xFC)++0x03
|
|
line.long 0x00 "GPDLOCK,GPIO D Lock Configuration Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0xFE)++0x03
|
|
line.long 0x00 "GPDCR,GPIO D Lock Commit Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Configuration lock commit bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x100)++0x03
|
|
line.long 0x00 "GPECTRL,GPIO E Qualification Sampling Period Control (GPIO128 to 159)"
|
|
hexmask.long 0x00 24.--31. 1. "QUALPRD3,Qualification sampling period for GPIO152 to GPIO159"
|
|
hexmask.long 0x00 16.--23. 1. "QUALPRD2,Qualification sampling period for GPIO144 to GPIO151"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO136 to GPIO143"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO128 to GPIO135"
|
|
group.long (d:0x00007C00+0x102)++0x03
|
|
line.long 0x00 "GPEQSEL1,GPIO E Qualifier Select 1 Register (GPIO128 to 143)"
|
|
bitfld.long 0x00 30.--31. " GPIO143 ,Select input qualification type for GPIO143" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO142 ,Select input qualification type for GPIO142" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO141 ,Select input qualification type for GPIO141" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO140 ,Select input qualification type for GPIO140" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO139 ,Select input qualification type for GPIO139" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO138 ,Select input qualification type for GPIO138" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO137 ,Select input qualification type for GPIO137" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO136 ,Select input qualification type for GPIO136" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO135 ,Select input qualification type for GPIO135" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO134 ,Select input qualification type for GPIO134" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO133 ,Select input qualification type for GPIO133" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO132 ,Select input qualification type for GPIO132" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO131 ,Select input qualification type for GPIO131" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO130 ,Select input qualification type for GPIO130" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO129 ,Select input qualification type for GPIO129" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO128 ,Select input qualification type for GPIO128" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x104)++0x03
|
|
line.long 0x00 "GPEQSEL2,GPIO E Qualifier Select 2 Register (GPIO144 to 159)"
|
|
bitfld.long 0x00 30.--31. " GPIO159 ,Select input qualification type for GPIO159" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO158 ,Select input qualification type for GPIO158" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO157 ,Select input qualification type for GPIO157" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO156 ,Select input qualification type for GPIO156" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO155 ,Select input qualification type for GPIO155" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO154 ,Select input qualification type for GPIO154" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO153 ,Select input qualification type for GPIO153" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO152 ,Select input qualification type for GPIO152" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO151 ,Select input qualification type for GPIO151" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO150 ,Select input qualification type for GPIO150" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO149 ,Select input qualification type for GPIO149" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO148 ,Select input qualification type for GPIO148" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO147 ,Select input qualification type for GPIO147" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO146 ,Select input qualification type for GPIO146" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO145 ,Select input qualification type for GPIO145" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO144 ,Select input qualification type for GPIO144" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x106)++0x03
|
|
line.long 0x00 "GPEMUX1,GPIO E Mux 1 Register (GPIO128 to 143)"
|
|
bitfld.long 0x00 30.--31. " GPIO143 ,Defines pin-muxing selection for GPIO143" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO142 ,Defines pin-muxing selection for GPIO142" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO141 ,Defines pin-muxing selection for GPIO141" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO140 ,Defines pin-muxing selection for GPIO140" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO139 ,Defines pin-muxing selection for GPIO139" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO138 ,Defines pin-muxing selection for GPIO138" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO137 ,Defines pin-muxing selection for GPIO137" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO136 ,Defines pin-muxing selection for GPIO136" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO135 ,Defines pin-muxing selection for GPIO135" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO134 ,Defines pin-muxing selection for GPIO134" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO133 ,Defines pin-muxing selection for GPIO133" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO132 ,Defines pin-muxing selection for GPIO132" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO131 ,Defines pin-muxing selection for GPIO131" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO130 ,Defines pin-muxing selection for GPIO130" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO129 ,Defines pin-muxing selection for GPIO129" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO128 ,Defines pin-muxing selection for GPIO128" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x108)++0x03
|
|
line.long 0x00 "GPEMUX2,GPIO E Mux 2 Register (GPIO144 to 159)"
|
|
bitfld.long 0x00 30.--31. " GPIO159 ,Defines pin-muxing selection for GPIO159" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO158 ,Defines pin-muxing selection for GPIO158" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO157 ,Defines pin-muxing selection for GPIO157" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO156 ,Defines pin-muxing selection for GPIO156" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO155 ,Defines pin-muxing selection for GPIO155" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO154 ,Defines pin-muxing selection for GPIO154" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO153 ,Defines pin-muxing selection for GPIO153" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO152 ,Defines pin-muxing selection for GPIO152" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO151 ,Defines pin-muxing selection for GPIO151" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO150 ,Defines pin-muxing selection for GPIO150" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO149 ,Defines pin-muxing selection for GPIO149" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO148 ,Defines pin-muxing selection for GPIO148" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO147 ,Defines pin-muxing selection for GPIO147" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO146 ,Defines pin-muxing selection for GPIO146" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO145 ,Defines pin-muxing selection for GPIO145" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO144 ,Defines pin-muxing selection for GPIO144" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x10A)++0x03
|
|
line.long 0x00 "GPEDIR,GPIO E Direction Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0x10C)++0x03
|
|
line.long 0x00 "GPEPUD,GPIO E Pull Up Disable Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x110)++0x03
|
|
line.long 0x00 "GPEINV,GPIO E Input Polarity Invert Registers (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x112)++0x03
|
|
line.long 0x00 "GPEODR,GPIO E Open Drain Output Register (GPIO128 to GPIO159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x120)++0x03
|
|
line.long 0x00 "GPEGMUX1,GPIO E Peripheral Group Mux (GPIO128 to 143)"
|
|
bitfld.long 0x00 30.--31. " GPIO143 ,Defines pin-muxing selection for GPIO143" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO142 ,Defines pin-muxing selection for GPIO142" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO141 ,Defines pin-muxing selection for GPIO141" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO140 ,Defines pin-muxing selection for GPIO140" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO139 ,Defines pin-muxing selection for GPIO139" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO138 ,Defines pin-muxing selection for GPIO138" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO137 ,Defines pin-muxing selection for GPIO137" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO136 ,Defines pin-muxing selection for GPIO136" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO135 ,Defines pin-muxing selection for GPIO135" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO134 ,Defines pin-muxing selection for GPIO134" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO133 ,Defines pin-muxing selection for GPIO133" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO132 ,Defines pin-muxing selection for GPIO132" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO131 ,Defines pin-muxing selection for GPIO131" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO130 ,Defines pin-muxing selection for GPIO130" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO129 ,Defines pin-muxing selection for GPIO129" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO128 ,Defines pin-muxing selection for GPIO128" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x122)++0x03
|
|
line.long 0x00 "GPEGMUX2,GPIO E Peripheral Group Mux (GPIO144 to 159)"
|
|
bitfld.long 0x00 30.--31. " GPIO159 ,Defines pin-muxing selection for GPIO159" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GPIO158 ,Defines pin-muxing selection for GPIO158" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GPIO157 ,Defines pin-muxing selection for GPIO157" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GPIO156 ,Defines pin-muxing selection for GPIO156" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GPIO155 ,Defines pin-muxing selection for GPIO155" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GPIO154 ,Defines pin-muxing selection for GPIO154" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GPIO153 ,Defines pin-muxing selection for GPIO153" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GPIO152 ,Defines pin-muxing selection for GPIO152" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GPIO151 ,Defines pin-muxing selection for GPIO151" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO150 ,Defines pin-muxing selection for GPIO150" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO149 ,Defines pin-muxing selection for GPIO149" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPIO148 ,Defines pin-muxing selection for GPIO148" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " GPIO147 ,Defines pin-muxing selection for GPIO147" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO146 ,Defines pin-muxing selection for GPIO146" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO145 ,Defines pin-muxing selection for GPIO145" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPIO144 ,Defines pin-muxing selection for GPIO144" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x128)++0x03
|
|
line.long 0x00 "GPECSEL1,GPIO E Core Select Register (GPIO128 to 135)"
|
|
bitfld.long 0x00 28.--31. " GPIO135 ,GPIO135 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO134 ,GPIO134 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO133 ,GPIO133 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO132 ,GPIO132 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO131 ,GPIO131 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO130 ,GPIO130 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO129 ,GPIO129 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO128 ,GPIO128 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x12A)++0x03
|
|
line.long 0x00 "GPECSEL2,GPIO E Core Select Register (GPIO136 to 143)"
|
|
bitfld.long 0x00 28.--31. " GPIO143 ,GPIO143 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO142 ,GPIO142 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO141 ,GPIO141 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO140 ,GPIO140 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO139 ,GPIO139 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO138 ,GPIO138 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO137 ,GPIO137 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO136 ,GPIO136 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x12C)++0x03
|
|
line.long 0x00 "GPECSEL3,GPIO E Core Select Register (GPIO144 to 151)"
|
|
bitfld.long 0x00 28.--31. " GPIO151 ,GPIO151 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO150 ,GPIO150 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO149 ,GPIO149 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO148 ,GPIO148 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO147 ,GPIO147 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO146 ,GPIO146 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO145 ,GPIO145 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO144 ,GPIO144 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x12E)++0x03
|
|
line.long 0x00 "GPECSEL4,GPIO E Core Select Register (GPIO152 to 159)"
|
|
bitfld.long 0x00 28.--31. " GPIO159 ,GPIO159 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO158 ,GPIO158 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO157 ,GPIO157 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO156 ,GPIO156 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO155 ,GPIO155 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO154 ,GPIO154 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO153 ,GPIO153 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO152 ,GPIO152 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x13C)++0x03
|
|
line.long 0x00 "GPELOCK,GPIO E Lock Configuration Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x13E)++0x03
|
|
line.long 0x00 "GPECR,GPIO E Lock Commit Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Configuration lock commit bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x140)++0x03
|
|
line.long 0x00 "GPFCTRL,GPIO F Qualification Sampling Period Control (GPIO160 to 168)"
|
|
hexmask.long 0x00 8.--15. 1. "QUALPRD1,Qualification sampling period for GPIO168"
|
|
hexmask.long 0x00 0.--7. 1. "QUALPRD0,Qualification sampling period for GPIO160 to GPIO167"
|
|
group.long (d:0x00007C00+0x142)++0x03
|
|
line.long 0x00 "GPFQSEL1,GPIO F Qualifier Select 1 Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 16.--17. " GPIO168 ,Select input qualification type for GPIO168" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GPIO167 ,Select input qualification type for GPIO167" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO166 ,Select input qualification type for GPIO166" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO165 ,Select input qualification type for GPIO165" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " GPIO164 ,Select input qualification type for GPIO164" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GPIO163 ,Select input qualification type for GPIO163" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO162 ,Select input qualification type for GPIO162" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO161 ,Select input qualification type for GPIO161" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " GPIO160 ,Select input qualification type for GPIO160" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x146)++0x03
|
|
line.long 0x00 "GPFMUX1,GPIO F Mux 1 Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 16.--17. " GPIO168 ,Defines pin-muxing selection for GPIO168" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GPIO167 ,Defines pin-muxing selection for GPIO167" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO166 ,Defines pin-muxing selection for GPIO166" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO165 ,Defines pin-muxing selection for GPIO165" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " GPIO164 ,Defines pin-muxing selection for GPIO164" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GPIO163 ,Defines pin-muxing selection for GPIO163" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO162 ,Defines pin-muxing selection for GPIO162" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO161 ,Defines pin-muxing selection for GPIO161" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " GPIO160 ,Defines pin-muxing selection for GPIO160" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x14A)++0x03
|
|
line.long 0x00 "GPFDIR,GPIO F Direction Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Defines direction for this pin in GPIO mode" "0,1"
|
|
group.long (d:0x00007C00+0x14C)++0x03
|
|
line.long 0x00 "GPFPUD,GPIO F Pull Up Disable Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Pull-Up Disable control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Pull-Up Disable control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Pull-Up Disable control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x150)++0x03
|
|
line.long 0x00 "GPFINV,GPIO F Input Polarity Invert Registers (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Input inversion control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Input inversion control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Input inversion control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x152)++0x03
|
|
line.long 0x00 "GPFODR,GPIO F Open Drain Output Register (GPIO160 to GPIO168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Outpout Open-Drain control for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Outpout Open-Drain control for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Outpout Open-Drain control for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x160)++0x03
|
|
line.long 0x00 "GPFGMUX1,GPIO F Peripheral Group Mux (GPIO160 to 168)"
|
|
bitfld.long 0x00 16.--17. " GPIO168 ,Defines pin-muxing selection for GPIO168" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GPIO167 ,Defines pin-muxing selection for GPIO167" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GPIO166 ,Defines pin-muxing selection for GPIO166" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GPIO165 ,Defines pin-muxing selection for GPIO165" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " GPIO164 ,Defines pin-muxing selection for GPIO164" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GPIO163 ,Defines pin-muxing selection for GPIO163" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPIO162 ,Defines pin-muxing selection for GPIO162" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " GPIO161 ,Defines pin-muxing selection for GPIO161" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " GPIO160 ,Defines pin-muxing selection for GPIO160" "0,1,2,3"
|
|
group.long (d:0x00007C00+0x168)++0x03
|
|
line.long 0x00 "GPFCSEL1,GPIO F Core Select Register (GPIO160 to 167)"
|
|
bitfld.long 0x00 28.--31. " GPIO167 ,GPIO167 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " GPIO166 ,GPIO166 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " GPIO165 ,GPIO165 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " GPIO164 ,GPIO164 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " GPIO163 ,GPIO163 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPIO162 ,GPIO162 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GPIO161 ,GPIO161 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " GPIO160 ,GPIO160 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x16A)++0x03
|
|
line.long 0x00 "GPFCSEL2,GPIO F Core Select Register (GPIO168)"
|
|
bitfld.long 0x00 0.--3. " GPIO168 ,GPIO168 Master CPU Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00007C00+0x17C)++0x03
|
|
line.long 0x00 "GPFLOCK,GPIO F Lock Configuration Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Configuration Lock bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Configuration Lock bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Configuration Lock bit for this pin" "0,1"
|
|
group.long (d:0x00007C00+0x17E)++0x03
|
|
line.long 0x00 "GPFCR,GPIO F Lock Commit Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Configuration lock commit bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Configuration lock commit bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Configuration lock commit bit for this pin" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GpioDataRegs"
|
|
width 11.
|
|
group.long (d:0x00007F00+0x00)++0x03
|
|
line.long 0x00 "GPADAT,GPIO A Data Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x02)++0x03
|
|
line.long 0x00 "GPASET,GPIO A Data Set Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x04)++0x03
|
|
line.long 0x00 "GPACLEAR,GPIO A Data Clear Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x06)++0x03
|
|
line.long 0x00 "GPATOGGLE,GPIO A Data Toggle Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x08)++0x03
|
|
line.long 0x00 "GPBDAT,GPIO B Data Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x0A)++0x03
|
|
line.long 0x00 "GPBSET,GPIO B Data Set Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x0C)++0x03
|
|
line.long 0x00 "GPBCLEAR,GPIO B Data Clear Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x0E)++0x03
|
|
line.long 0x00 "GPBTOGGLE,GPIO B Data Toggle Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x10)++0x03
|
|
line.long 0x00 "GPCDAT,GPIO C Data Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x12)++0x03
|
|
line.long 0x00 "GPCSET,GPIO C Data Set Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x14)++0x03
|
|
line.long 0x00 "GPCCLEAR,GPIO C Data Clear Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x16)++0x03
|
|
line.long 0x00 "GPCTOGGLE,GPIO C Data Toggle Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x18)++0x03
|
|
line.long 0x00 "GPDDAT,GPIO D Data Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x1A)++0x03
|
|
line.long 0x00 "GPDSET,GPIO D Data Set Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x1C)++0x03
|
|
line.long 0x00 "GPDCLEAR,GPIO D Data Clear Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x1E)++0x03
|
|
line.long 0x00 "GPDTOGGLE,GPIO D Data Toggle Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x20)++0x03
|
|
line.long 0x00 "GPEDAT,GPIO E Data Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x22)++0x03
|
|
line.long 0x00 "GPESET,GPIO E Data Set Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x24)++0x03
|
|
line.long 0x00 "GPECLEAR,GPIO E Data Clear Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x26)++0x03
|
|
line.long 0x00 "GPETOGGLE,GPIO E Data Toggle Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x28)++0x03
|
|
line.long 0x00 "GPFDAT,GPIO F Data Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x2A)++0x03
|
|
line.long 0x00 "GPFSET,GPIO F Data Set Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x2C)++0x03
|
|
line.long 0x00 "GPFCLEAR,GPIO F Data Clear Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x00007F00+0x2E)++0x03
|
|
line.long 0x00 "GPFTOGGLE,GPIO F Data Toggle Register (GPIO160 to 168)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Toggle bit for this pin" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GpioDataReadRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00007F80+0x00)++0x03
|
|
line.long 0x00 "GPADAT_R,GPIO A Data Read Register"
|
|
rgroup.long (d:0x00007F80+0x02)++0x03
|
|
line.long 0x00 "GPBDAT_R,GPIO B Data Read Register"
|
|
rgroup.long (d:0x00007F80+0x04)++0x03
|
|
line.long 0x00 "GPCDAT_R,GPIO C Data Read Register"
|
|
rgroup.long (d:0x00007F80+0x06)++0x03
|
|
line.long 0x00 "GPDDAT_R,GPIO D Data Read Register"
|
|
rgroup.long (d:0x00007F80+0x08)++0x03
|
|
line.long 0x00 "GPEDAT_R,GPIO E Data Read Register"
|
|
rgroup.long (d:0x00007F80+0x0A)++0x03
|
|
line.long 0x00 "GPFDAT_R,GPIO F Data Read Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HWBistRegs"
|
|
width 12.
|
|
group.long (d:0x0005E000+0x04)++0x03
|
|
line.long 0x00 "CSTCGCR1,STC Global Control Register1"
|
|
group.long (d:0x0005E000+0x0C)++0x03
|
|
line.long 0x00 "CSTCGCR3,STC Global Control Register3"
|
|
bitfld.long 0x00 0.--3. " ILS ,Interrupt Logging Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E000+0x10)++0x03
|
|
line.long 0x00 "CSTCGCR4,STC Global Control Register4"
|
|
bitfld.long 0x00 0.--3. " BISTGO ,BIST Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E000+0x14)++0x03
|
|
line.long 0x00 "CSTCGCR5,STC Global Control Register5"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Soft reset to BIST controller" "0,1"
|
|
bitfld.long 0x00 0.--3. " RESTART ,Restart Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E000+0x18)++0x03
|
|
line.long 0x00 "CSTCGCR6,STC Global Control Register6"
|
|
bitfld.long 0x00 0.--1. " COV ,COVERAGE" "0,1,2,3"
|
|
group.long (d:0x0005E000+0x1C)++0x03
|
|
line.long 0x00 "CSTCGCR7,STC Global Control Register7"
|
|
bitfld.long 0x00 18.--19. " SCD ,SHIFT_CLOCK_DIVISION" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " PST ,PATTERN SET TYPE" "0,1,2,3"
|
|
bitfld.long 0x00 12.--15. " NP ,NUM OF PIPELINE STAGES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DC ,DEAD CYCLES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long 0x00 0.--7. 1. "MCL,MAX CHAIN LENGTH"
|
|
group.long (d:0x0005E000+0x20)++0x03
|
|
line.long 0x00 "CSTCGCR8,STC Global Control Register8"
|
|
hexmask.long 0x00 0.--15. 1. "CPC,COMPARE PATTERN CNT"
|
|
group.long (d:0x0005E000+0x24)++0x03
|
|
line.long 0x00 "CSTCPCNT,STC Pattern Count Register"
|
|
hexmask.long 0x00 16.--31. 1. "PCNT_99,PATTERNS FOR 99% COVERAGE"
|
|
hexmask.long 0x00 0.--15. 1. "PCNT_95,PATTERNS FOR 95% COVERAGE"
|
|
group.long (d:0x0005E000+0x28)++0x03
|
|
line.long 0x00 "CSTCCONFIG,STC Registers Configuration Status"
|
|
bitfld.long 0x00 0.--3. " CFGDONE ,Configuration done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E000+0x2C)++0x03
|
|
line.long 0x00 "CSTCSADDR,STC ROM Start Address"
|
|
hexmask.long 0x00 16.--31. 1. "SAMISR,MISR ROM Start Address"
|
|
hexmask.long 0x00 0.--15. 1. "SAPAT,PATTERN ROM Start Address"
|
|
group.long (d:0x0005E000+0x30)++0x03
|
|
line.long 0x00 "CSTCTEST,C28 HW BIST Test Register"
|
|
hexmask.long 0x00 12.--31. 1. "TEST,TEST Bits"
|
|
bitfld.long 0x00 8.--11. " TEST_NMI ,Test_NMI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TEST_CMP_FAIL ,Test MISR compare fail" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " TEST_TO ,Test_ Time_Out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005E000+0x34)++0x03
|
|
line.long 0x00 "CSTCRET,C28 Return PC Address"
|
|
group.long (d:0x0005E000+0x38)++0x03
|
|
line.long 0x00 "CSTCCRD,C28 Context Restore Done Register"
|
|
bitfld.long 0x00 0.--3. " Restore_Done ,Context Restone Done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x0005E000+0x40)++0x03
|
|
line.long 0x00 "CSTCGSTAT,STC Global Status Register"
|
|
bitfld.long 0x00 5. " TOFAIL ,Time Out Failure" "0,1"
|
|
bitfld.long 0x00 4. " INTCMPF ,Intermediate Comparison Failure" "0,1"
|
|
bitfld.long 0x00 3. " BISTFAIL ,HW BIST Failure" "0,1"
|
|
bitfld.long 0x00 2. " NMI ,Exit due to NMI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " MACRODONE ,Macro test slot Complete" "0,1"
|
|
bitfld.long 0x00 0. " BISTDONE ,HW BIST Complete" "0,1"
|
|
rgroup.long (d:0x0005E000+0x48)++0x03
|
|
line.long 0x00 "CSTCCPCR,STC Current Pattern Count Register"
|
|
hexmask.long 0x00 0.--15. 1. "PATCNT,Current Pattern Count"
|
|
rgroup.long (d:0x0005E000+0x4C)++0x03
|
|
line.long 0x00 "CSTCCADDR,STC Current ROM Address Register"
|
|
hexmask.long 0x00 16.--31. 1. "MISRADDR,Current MISR ROM Address"
|
|
hexmask.long 0x00 0.--15. 1. "PATADDR,Current Pattern ROM Address"
|
|
rgroup.long (d:0x0005E000+0x50)++0x03
|
|
line.long 0x00 "CSTCMISR0,MISR Result Register 0"
|
|
rgroup.long (d:0x0005E000+0x54)++0x03
|
|
line.long 0x00 "CSTCMISR1,MISR Result Register 1"
|
|
rgroup.long (d:0x0005E000+0x58)++0x03
|
|
line.long 0x00 "CSTCMISR2,MISR Result Register 2"
|
|
rgroup.long (d:0x0005E000+0x5C)++0x03
|
|
line.long 0x00 "CSTCMISR3,MISR Result Register 3"
|
|
rgroup.long (d:0x0005E000+0x60)++0x03
|
|
line.long 0x00 "CSTCMISR4,MISR Result Register 4"
|
|
rgroup.long (d:0x0005E000+0x64)++0x03
|
|
line.long 0x00 "CSTCMISR5,MISR Result Register 5"
|
|
rgroup.long (d:0x0005E000+0x68)++0x03
|
|
line.long 0x00 "CSTCMISR6,MISR Result Register 6"
|
|
rgroup.long (d:0x0005E000+0x6C)++0x03
|
|
line.long 0x00 "CSTCMISR7,MISR Result Register 7"
|
|
rgroup.long (d:0x0005E000+0x70)++0x03
|
|
line.long 0x00 "CSTCMISR8,MISR Result Register 8"
|
|
rgroup.long (d:0x0005E000+0x74)++0x03
|
|
line.long 0x00 "CSTCMISR9,MISR Result Register 9"
|
|
rgroup.long (d:0x0005E000+0x78)++0x03
|
|
line.long 0x00 "CSTCMISR10,MISR Result Register 10"
|
|
rgroup.long (d:0x0005E000+0x7C)++0x03
|
|
line.long 0x00 "CSTCMISR11,MISR Result Register 11"
|
|
rgroup.long (d:0x0005E000+0x80)++0x03
|
|
line.long 0x00 "CSTCMISR12,MISR Result Register 12"
|
|
rgroup.long (d:0x0005E000+0x84)++0x03
|
|
line.long 0x00 "CSTCMISR13,MISR Result Register 13"
|
|
rgroup.long (d:0x0005E000+0x88)++0x03
|
|
line.long 0x00 "CSTCMISR14,MISR Result Register 14"
|
|
rgroup.long (d:0x0005E000+0x8C)++0x03
|
|
line.long 0x00 "CSTCMISR15,MISR Result Register 15"
|
|
group.long (d:0x0005E000+0xA0)++0x03
|
|
line.long 0x00 "CSTCSEM,STC Semaphore register"
|
|
bitfld.long 0x00 0.--1. " SEMAPHORE ,Semaphore" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Inter-Integrated Circuit Module (I2C)"
|
|
tree "I2C A"
|
|
width 9.
|
|
group.word (d:0x00007300+0x00)++0x01
|
|
line.word 0x00 "I2COAR,I2C Own address"
|
|
hexmask.word 0x00 0.--9. 1. "OAR,I2C Own address"
|
|
group.word (d:0x00007300+0x01)++0x01
|
|
line.word 0x00 "I2CIER,I2C Interrupt Enable"
|
|
bitfld.word 0x00 6. " AAS ,Addressed as slave interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SCD ,Stop condition detected interrupt enable" "0,1"
|
|
bitfld.word 0x00 4. " XRDY ,Transmit-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " RRDY ,Receive-data-ready interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " ARDY ,Register-access-ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " NACK ,No-acknowledgment interrupt enable" "0,1"
|
|
bitfld.word 0x00 0. " ARBL ,Arbitration-lost interrupt enable" "0,1"
|
|
group.word (d:0x00007300+0x02)++0x01
|
|
line.word 0x00 "I2CSTR,I2C Status"
|
|
bitfld.word 0x00 14. " SDIR ,Slave direction bit" "0,1"
|
|
bitfld.word 0x00 13. " NACKSNT ,NACK sent bit." "0,1"
|
|
rbitfld.word 0x00 12. " BB ,Bus busy bit." "0,1"
|
|
rbitfld.word 0x00 11. " RSFULL ,Receive shift register full bit." "0,1"
|
|
newline
|
|
rbitfld.word 0x00 10. " XSMT ,Transmit shift register empty bit." "0,1"
|
|
rbitfld.word 0x00 9. " AAS ,Addressed-as-slave bit" "0,1"
|
|
rbitfld.word 0x00 8. " AD0 ,Address 0 bits" "0,1"
|
|
bitfld.word 0x00 6. " BYTESENT ,Byte transmit over indication" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " SCD ,Stop condition detected bit." "0,1"
|
|
rbitfld.word 0x00 4. " XRDY ,Transmit-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 3. " RRDY ,Receive-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 2. " ARDY ,Register-access-ready interrupt flag bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " NACK ,No-acknowledgment interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 0. " ARBL ,Arbitration-lost interrupt flag bit" "0,1"
|
|
group.word (d:0x00007300+0x03)++0x01
|
|
line.word 0x00 "I2CCLKL,I2C Clock low-time divider"
|
|
group.word (d:0x00007300+0x04)++0x01
|
|
line.word 0x00 "I2CCLKH,I2C Clock high-time divider"
|
|
group.word (d:0x00007300+0x05)++0x01
|
|
line.word 0x00 "I2CCNT,I2C Data count"
|
|
rgroup.word (d:0x00007300+0x06)++0x01
|
|
line.word 0x00 "I2CDRR,I2C Data receive"
|
|
hexmask.word 0x00 0.--7. 1. "DATA,Receive data"
|
|
group.word (d:0x00007300+0x07)++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave address"
|
|
hexmask.word 0x00 0.--9. 1. "SAR,Slave Address"
|
|
group.word (d:0x00007300+0x08)++0x01
|
|
line.word 0x00 "I2CDXR,I2C Data Transmit"
|
|
hexmask.word 0x00 0.--7. 1. "DATA,Transmit data"
|
|
group.word (d:0x00007300+0x09)++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode"
|
|
bitfld.word 0x00 15. " NACKMOD ,NACK mode bit" "0,1"
|
|
bitfld.word 0x00 14. " FREE ,Debug Action" "0,1"
|
|
bitfld.word 0x00 13. " STT ,START condition bit" "0,1"
|
|
bitfld.word 0x00 11. " STP ,STOP Condition" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master Mode" "0,1"
|
|
bitfld.word 0x00 9. " TRX ,Transmitter Mode" "0,1"
|
|
bitfld.word 0x00 8. " XA ,Expanded Address Mode" "0,1"
|
|
bitfld.word 0x00 7. " RM ,Repeat Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital Loopback Mode" "0,1"
|
|
bitfld.word 0x00 5. " IRS ,I2C Module Reset" "0,1"
|
|
bitfld.word 0x00 4. " STB ,START Byte Mode" "0,1"
|
|
bitfld.word 0x00 3. " FDF ,Free Data Format" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC ,Bit count bits." "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007300+0x0A)++0x01
|
|
line.word 0x00 "I2CISRC,I2C Interrupt Source"
|
|
bitfld.word 0x00 8.--11. " WRITE_ZEROS ,Always write all 0s to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 0.--2. " INTCODE ,Interrupt code bits." "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007300+0x0B)++0x01
|
|
line.word 0x00 "I2CEMDR,I2C Extended Mode"
|
|
bitfld.word 0x00 1. " FCM ,Forward Compatibility for Tx behav in Type1" "0,1"
|
|
bitfld.word 0x00 0. " BC ,Backwards compatibility mode" "0,1"
|
|
group.word (d:0x00007300+0x0C)++0x01
|
|
line.word 0x00 "I2CPSC,I2C Prescaler"
|
|
hexmask.word 0x00 0.--7. 1. "IPSC,I2C Prescaler Divide Down"
|
|
group.word (d:0x00007300+0x20)++0x01
|
|
line.word 0x00 "I2CFFTX,I2C FIFO Transmit"
|
|
bitfld.word 0x00 14. " I2CFFEN ,Transmit FIFO Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFFRST ,Transmit FIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.word 0x00 7. " TXFFINT ,Transmit FIFO Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Transmit FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Transmit FIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Transmit FIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007300+0x21)++0x01
|
|
line.word 0x00 "I2CFFRX,I2C FIFO Receive"
|
|
bitfld.word 0x00 13. " RXFFRST ,Receive FIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.word 0x00 7. " RXFFINT ,Receive FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Receive FIFO Interrupt Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " RXFFIENA ,Receive FIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Receive FIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C B"
|
|
width 9.
|
|
group.word (d:0x00007340+0x00)++0x01
|
|
line.word 0x00 "I2COAR,I2C Own address"
|
|
hexmask.word 0x00 0.--9. 1. "OAR,I2C Own address"
|
|
group.word (d:0x00007340+0x01)++0x01
|
|
line.word 0x00 "I2CIER,I2C Interrupt Enable"
|
|
bitfld.word 0x00 6. " AAS ,Addressed as slave interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SCD ,Stop condition detected interrupt enable" "0,1"
|
|
bitfld.word 0x00 4. " XRDY ,Transmit-data-ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " RRDY ,Receive-data-ready interrupt enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " ARDY ,Register-access-ready interrupt enable" "0,1"
|
|
bitfld.word 0x00 1. " NACK ,No-acknowledgment interrupt enable" "0,1"
|
|
bitfld.word 0x00 0. " ARBL ,Arbitration-lost interrupt enable" "0,1"
|
|
group.word (d:0x00007340+0x02)++0x01
|
|
line.word 0x00 "I2CSTR,I2C Status"
|
|
bitfld.word 0x00 14. " SDIR ,Slave direction bit" "0,1"
|
|
bitfld.word 0x00 13. " NACKSNT ,NACK sent bit." "0,1"
|
|
rbitfld.word 0x00 12. " BB ,Bus busy bit." "0,1"
|
|
rbitfld.word 0x00 11. " RSFULL ,Receive shift register full bit." "0,1"
|
|
newline
|
|
rbitfld.word 0x00 10. " XSMT ,Transmit shift register empty bit." "0,1"
|
|
rbitfld.word 0x00 9. " AAS ,Addressed-as-slave bit" "0,1"
|
|
rbitfld.word 0x00 8. " AD0 ,Address 0 bits" "0,1"
|
|
bitfld.word 0x00 6. " BYTESENT ,Byte transmit over indication" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " SCD ,Stop condition detected bit." "0,1"
|
|
rbitfld.word 0x00 4. " XRDY ,Transmit-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 3. " RRDY ,Receive-data-ready interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 2. " ARDY ,Register-access-ready interrupt flag bit" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " NACK ,No-acknowledgment interrupt flag bit." "0,1"
|
|
bitfld.word 0x00 0. " ARBL ,Arbitration-lost interrupt flag bit" "0,1"
|
|
group.word (d:0x00007340+0x03)++0x01
|
|
line.word 0x00 "I2CCLKL,I2C Clock low-time divider"
|
|
group.word (d:0x00007340+0x04)++0x01
|
|
line.word 0x00 "I2CCLKH,I2C Clock high-time divider"
|
|
group.word (d:0x00007340+0x05)++0x01
|
|
line.word 0x00 "I2CCNT,I2C Data count"
|
|
rgroup.word (d:0x00007340+0x06)++0x01
|
|
line.word 0x00 "I2CDRR,I2C Data receive"
|
|
hexmask.word 0x00 0.--7. 1. "DATA,Receive data"
|
|
group.word (d:0x00007340+0x07)++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave address"
|
|
hexmask.word 0x00 0.--9. 1. "SAR,Slave Address"
|
|
group.word (d:0x00007340+0x08)++0x01
|
|
line.word 0x00 "I2CDXR,I2C Data Transmit"
|
|
hexmask.word 0x00 0.--7. 1. "DATA,Transmit data"
|
|
group.word (d:0x00007340+0x09)++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode"
|
|
bitfld.word 0x00 15. " NACKMOD ,NACK mode bit" "0,1"
|
|
bitfld.word 0x00 14. " FREE ,Debug Action" "0,1"
|
|
bitfld.word 0x00 13. " STT ,START condition bit" "0,1"
|
|
bitfld.word 0x00 11. " STP ,STOP Condition" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master Mode" "0,1"
|
|
bitfld.word 0x00 9. " TRX ,Transmitter Mode" "0,1"
|
|
bitfld.word 0x00 8. " XA ,Expanded Address Mode" "0,1"
|
|
bitfld.word 0x00 7. " RM ,Repeat Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " DLB ,Digital Loopback Mode" "0,1"
|
|
bitfld.word 0x00 5. " IRS ,I2C Module Reset" "0,1"
|
|
bitfld.word 0x00 4. " STB ,START Byte Mode" "0,1"
|
|
bitfld.word 0x00 3. " FDF ,Free Data Format" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--2. " BC ,Bit count bits." "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007340+0x0A)++0x01
|
|
line.word 0x00 "I2CISRC,I2C Interrupt Source"
|
|
bitfld.word 0x00 8.--11. " WRITE_ZEROS ,Always write all 0s to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 0.--2. " INTCODE ,Interrupt code bits." "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007340+0x0B)++0x01
|
|
line.word 0x00 "I2CEMDR,I2C Extended Mode"
|
|
bitfld.word 0x00 1. " FCM ,Forward Compatibility for Tx behav in Type1" "0,1"
|
|
bitfld.word 0x00 0. " BC ,Backwards compatibility mode" "0,1"
|
|
group.word (d:0x00007340+0x0C)++0x01
|
|
line.word 0x00 "I2CPSC,I2C Prescaler"
|
|
hexmask.word 0x00 0.--7. 1. "IPSC,I2C Prescaler Divide Down"
|
|
group.word (d:0x00007340+0x20)++0x01
|
|
line.word 0x00 "I2CFFTX,I2C FIFO Transmit"
|
|
bitfld.word 0x00 14. " I2CFFEN ,Transmit FIFO Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFFRST ,Transmit FIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.word 0x00 7. " TXFFINT ,Transmit FIFO Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Transmit FIFO Interrupt Flag Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Transmit FIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Transmit FIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007340+0x21)++0x01
|
|
line.word 0x00 "I2CFFRX,I2C FIFO Receive"
|
|
bitfld.word 0x00 13. " RXFFRST ,Receive FIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.word 0x00 7. " RXFFINT ,Receive FIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Receive FIFO Interrupt Flag Clear" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. " RXFFIENA ,Receive FIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Receive FIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Interprocessor Communication (IPC)"
|
|
width 21.
|
|
group.long (d:0x0005CE40+0x00)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCACK,CMTOCPU1IPCACK Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC28 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC24 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC20 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC16 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC8 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC4 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long (d:0x0005CE40+0x02)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCSTS,CPU1TOCMIPCSTS Register"
|
|
bitfld.long 0x00 31. " IPC31 ,IPC31 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,IPC30 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,IPC29 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,IPC28 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,IPC27 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,IPC26 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,IPC25 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,IPC24 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,IPC23 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,IPC22 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,IPC21 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,IPC20 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,IPC19 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,IPC18 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,IPC17 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,IPC16 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,IPC15 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,IPC14 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,IPC13 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,IPC12 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,IPC11 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,IPC10 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,IPC9 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,IPC8 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,IPC7 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,IPC6 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,IPC5 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,IPC4 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,IPC3 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,IPC2 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,IPC1 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,IPC0 Request from CPU1 to CM" "0,1"
|
|
group.long (d:0x0005CE40+0x04)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSET,CMTOCPU1IPCSET Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Set CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Set CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Set CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Set CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Set CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Set CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Set CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Set CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Set CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Set CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Set CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Set CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Set CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Set CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Set CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Set CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Set CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Set CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Set CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Set CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Set CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Set CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Set CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Set CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Set CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Set CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Set CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Set CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Set CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Set CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Set CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Set CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
group.long (d:0x0005CE40+0x06)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCCLR,CMTOCPU1IPCCLR Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Clear CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Clear CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Clear CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Clear CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Clear CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Clear CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Clear CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Clear CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Clear CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Clear CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Clear CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Clear CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Clear CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Clear CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Clear CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Clear CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Clear CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Clear CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Clear CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Clear CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Clear CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Clear CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Clear CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Clear CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Clear CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Clear CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Clear CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Clear CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Clear CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Clear CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Clear CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Clear CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long (d:0x0005CE40+0x08)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCFLG,CMTOCPU1IPCFLG Register"
|
|
bitfld.long 0x00 31. " IPC31 ,CM to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,CM to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,CM to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,CM to CPU1 IPC28 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,CM to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,CM to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,CM to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,CM to CPU1 IPC24 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,CM to CPU1 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,CM to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,CM to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,CM to CPU1 IPC20 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,CM to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,CM to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,CM to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,CM to CPU1 IPC16 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,CM to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,CM to CPU1 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,CM to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,CM to CPU1 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,CM to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,CM to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,CM to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,CM to CPU1 IPC8 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,CM to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,CM to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,CM to CPU1 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,CM to CPU1 IPC4 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,CM to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,CM to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,CM to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,CM to CPU1 IPC0 Flag Status" "0,1"
|
|
rgroup.long (d:0x0005CE40+0x0C)++0x03
|
|
line.long 0x00 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
rgroup.long (d:0x0005CE40+0x0E)++0x03
|
|
line.long 0x00 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
rgroup.long (d:0x0005CE40+0x10)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVCOM,CPU1TOCMIPCRECVCOM Register"
|
|
rgroup.long (d:0x0005CE40+0x12)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVADDR,CPU1TOCMIPCRECVADDR Register"
|
|
rgroup.long (d:0x0005CE40+0x14)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVDATA,CPU1TOCMIPCRECVDATA Register"
|
|
group.long (d:0x0005CE40+0x16)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCREPLY,CMTOCPU1IPCREPLY Register"
|
|
group.long (d:0x0005CE40+0x18)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDCOM,CMTOCPU1IPCSENDCOM Register"
|
|
group.long (d:0x0005CE40+0x1A)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDADDR,CMTOCPU1IPCSENDADDR Register"
|
|
group.long (d:0x0005CE40+0x1C)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDDATA,CMTOCPU1IPCSENDDATA Register"
|
|
group.long (d:0x0005CE40+0x1E)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCREPLY,CPU1TOCMIPCREPLY Register"
|
|
group.long (d:0x0005CE40+0x20)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCBOOTSTS,CMTOCPU1IPCBOOTSTS Register"
|
|
group.long (d:0x0005CE40+0x22)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCBOOTMODE,CPU1TOCMIPCBOOTMODE Register"
|
|
group.long (d:0x0005CE40+0x24)++0x03
|
|
line.long 0x00 "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x00 0.--1. " SEM ,Flash Pump Request Semaphore between CPU1, CPU2 and CM" "0,1,2,3"
|
|
width 0x0B
|
|
sif !cpuis("F28388S*")&&!cpuis("F28386S*")&&!cpuis("F28384S*")
|
|
tree "IpcCPU1toCPU2Regs"
|
|
width 23.
|
|
group.long (d:0x0005CE00+0x00)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCACK,CPU2TOCPU1IPCACK Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC28 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC24 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC20 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC16 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC8 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC4 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long (d:0x0005CE00+0x02)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCSTS,CPU1TOCPU2IPCSTS Register"
|
|
bitfld.long 0x00 31. " IPC31 ,IPC31 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,IPC30 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,IPC29 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,IPC28 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,IPC27 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,IPC26 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,IPC25 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,IPC24 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,IPC23 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,IPC22 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,IPC21 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,IPC20 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,IPC19 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,IPC18 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,IPC17 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,IPC16 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,IPC15 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,IPC14 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,IPC13 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,IPC12 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,IPC11 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,IPC10 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,IPC9 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,IPC8 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,IPC7 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,IPC6 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,IPC5 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,IPC4 Request from CPU1 to CPU2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,IPC3 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,IPC2 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,IPC1 Request from CPU1 to CPU2" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,IPC0 Request from CPU1 to CPU2" "0,1"
|
|
group.long (d:0x0005CE00+0x04)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCSET,CPU2TOCPU1IPCSET Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Set CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Set CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Set CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Set CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Set CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Set CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Set CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Set CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Set CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Set CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Set CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Set CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Set CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Set CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Set CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Set CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Set CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Set CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Set CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Set CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Set CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Set CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Set CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Set CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Set CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Set CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Set CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Set CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Set CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Set CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Set CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Set CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
group.long (d:0x0005CE00+0x06)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCCLR,CPU2TOCPU1IPCCLR Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Clear CPU2TOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Clear CPU2TOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Clear CPU2TOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Clear CPU2TOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Clear CPU2TOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Clear CPU2TOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Clear CPU2TOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Clear CPU2TOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Clear CPU2TOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Clear CPU2TOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Clear CPU2TOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Clear CPU2TOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Clear CPU2TOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Clear CPU2TOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Clear CPU2TOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Clear CPU2TOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Clear CPU2TOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Clear CPU2TOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Clear CPU2TOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Clear CPU2TOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Clear CPU2TOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Clear CPU2TOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Clear CPU2TOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Clear CPU2TOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Clear CPU2TOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Clear CPU2TOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Clear CPU2TOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Clear CPU2TOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Clear CPU2TOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Clear CPU2TOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Clear CPU2TOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Clear CPU2TOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long (d:0x0005CE00+0x08)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCFLG,CPU2TOCPU1IPCFLG Register"
|
|
bitfld.long 0x00 31. " IPC31 ,CPU2 to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,CPU2 to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,CPU2 to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,CPU2 to CPU1 IPC28 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,CPU2 to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,CPU2 to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,CPU2 to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,CPU2 to CPU1 IPC24 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,CPU2 to CPU1 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,CPU2 to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,CPU2 to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,CPU2 to CPU1 IPC20 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,CPU2 to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,CPU2 to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,CPU2 to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,CPU2 to CPU1 IPC16 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,CPU2 to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,CPU2 to CPU1 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,CPU2 to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,CPU2 to CPU1 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,CPU2 to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,CPU2 to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,CPU2 to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,CPU2 to CPU1 IPC8 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,CPU2 to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,CPU2 to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,CPU2 to CPU1 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,CPU2 to CPU1 IPC4 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,CPU2 to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,CPU2 to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,CPU2 to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,CPU2 to CPU1 IPC0 Flag Status" "0,1"
|
|
rgroup.long (d:0x0005CE00+0x0C)++0x03
|
|
line.long 0x00 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
rgroup.long (d:0x0005CE00+0x0E)++0x03
|
|
line.long 0x00 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
rgroup.long (d:0x0005CE00+0x10)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCRECVCOM,CPU1TOCPU2IPCRECVCOM Register"
|
|
rgroup.long (d:0x0005CE00+0x12)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCRECVADDR,CPU1TOCPU2IPCRECVADDR Register"
|
|
rgroup.long (d:0x0005CE00+0x14)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCRECVDATA,CPU1TOCPU2IPCRECVDATA Register"
|
|
group.long (d:0x0005CE00+0x16)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCREPLY,CPU2TOCPU1IPCREPLY Register"
|
|
group.long (d:0x0005CE00+0x18)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCSENDCOM,CPU2TOCPU1IPCSENDCOM Register"
|
|
group.long (d:0x0005CE00+0x1A)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCSENDADDR,CPU2TOCPU1IPCSENDADDR Register"
|
|
group.long (d:0x0005CE00+0x1C)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCSENDDATA,CPU2TOCPU1IPCSENDDATA Register"
|
|
group.long (d:0x0005CE00+0x1E)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCREPLY,CPU1TOCPU2IPCREPLY Register"
|
|
group.long (d:0x0005CE00+0x20)++0x03
|
|
line.long 0x00 "CPU2TOCPU1IPCBOOTSTS,CPU2TOCPU1IPCBOOTSTS Register"
|
|
group.long (d:0x0005CE00+0x22)++0x03
|
|
line.long 0x00 "CPU1TOCPU2IPCBOOTMODE,CPU1TOCPU2IPCBOOTMODE Register"
|
|
group.long (d:0x0005CE00+0x24)++0x03
|
|
line.long 0x00 "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x00 0.--1. " SEM ,Flash Pump Request Semaphore between CPU1, CPU2 and CM" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "Modular Controller Area Network (MCAN)"
|
|
tree "McanRegs"
|
|
width 13.
|
|
rgroup.long (d:0x0005C600+0x00)++0x03
|
|
line.long 0x00 "MCAN_CREL,MCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long 0x00 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long 0x00 0.--7. 1. "DAY,Time Stamp Day"
|
|
rgroup.long (d:0x0005C600+0x02)++0x03
|
|
line.long 0x00 "MCAN_ENDN,MCAN Endian Register"
|
|
group.long (d:0x0005C600+0x06)++0x03
|
|
line.long 0x00 "MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 23. " TDC ,Transmitter Delay Compensation" "0,1"
|
|
bitfld.long 0x00 16.--20. " DBRP ,Data Bit Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " DTSEG1 ,Data Time Segment Before Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " DTSEG2 ,Data Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DSJW ,Data Resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x0005C600+0x08)++0x03
|
|
line.long 0x00 "MCAN_TEST,MCAN Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Receive Pin" "0,1"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "0,1"
|
|
group.long (d:0x0005C600+0x0A)++0x03
|
|
line.long 0x00 "MCAN_RWD,MCAN RAM Watchdog"
|
|
hexmask.long 0x00 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long 0x00 0.--7. 1. "WDC,Watchdog Configuration"
|
|
group.long (d:0x0005C600+0x0C)++0x03
|
|
line.long 0x00 "MCAN_CCCR,MCAN CC Control Register"
|
|
bitfld.long 0x00 15. " NISO ,Non-ISO Operation" "0,1"
|
|
bitfld.long 0x00 14. " TXP ,Transmit Pause" "0,1"
|
|
bitfld.long 0x00 13. " EFBI ,Edge Filtering During Bus Integration" "0,1"
|
|
bitfld.long 0x00 12. " PXHD ,Protocol Exception Handling Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " BRSE ,Bit Rate Switch Enable" "0,1"
|
|
bitfld.long 0x00 8. " FDOE ,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "0,1"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "0,1"
|
|
bitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "0,1"
|
|
group.long (d:0x0005C600+0x0E)++0x03
|
|
line.long 0x00 "MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 25.--31. " NSJW ,Nominal (Re)Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
hexmask.long 0x00 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
bitfld.long 0x00 0.--6. " NTSEG2 ,Nominal Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x0005C600+0x10)++0x03
|
|
line.long 0x00 "MCAN_TSCC,MCAN Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,1,2,3"
|
|
group.long (d:0x0005C600+0x12)++0x03
|
|
line.long 0x00 "MCAN_TSCV,MCAN Timestamp Counter Value"
|
|
hexmask.long 0x00 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long (d:0x0005C600+0x14)++0x03
|
|
line.long 0x00 "MCAN_TOCC,MCAN Timeout Counter Configuration"
|
|
hexmask.long 0x00 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "0,1"
|
|
group.long (d:0x0005C600+0x16)++0x03
|
|
line.long 0x00 "MCAN_TOCV,MCAN Timeout Counter Value"
|
|
hexmask.long 0x00 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long (d:0x0005C600+0x20)++0x03
|
|
line.long 0x00 "MCAN_ECR,MCAN Error Counter Register"
|
|
hexmask.long 0x00 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "0,1"
|
|
bitfld.long 0x00 8.--14. " REC ,Receive Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
rgroup.long (d:0x0005C600+0x22)++0x03
|
|
line.long 0x00 "MCAN_PSR,MCAN Protocol Status Register"
|
|
bitfld.long 0x00 16.--22. " TDCV ,Transmitter Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14. " PXE ,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x00 13. " RFDF ,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x00 12. " RBRS ,BRS Flag of Last Received CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " RESI ,ESI Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x00 8.--10. " DLEC ,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " BO ,Bus_Off Status" "0,1"
|
|
bitfld.long 0x00 6. " EW ,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EP ,Error Passive" "0,1"
|
|
bitfld.long 0x00 3.--4. " ACT ,Node Activity" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x0005C600+0x24)++0x03
|
|
line.long 0x00 "MCAN_TDCR,MCAN Transmitter Delay Compensation Register"
|
|
bitfld.long 0x00 8.--14. " TDCO ,Transmitter Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " TDCF ,Transmitter Delay Compensation Filter Window Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x0005C600+0x28)++0x03
|
|
line.long 0x00 "MCAN_IR,MCAN Interrupt Register"
|
|
bitfld.long 0x00 29. " ARA ,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x00 28. " PED ,Protocol Error in Data Phase" "0,1"
|
|
bitfld.long 0x00 27. " PEA ,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x00 26. " WDI ,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BO ,Bus_Off Status" "0,1"
|
|
bitfld.long 0x00 24. " EW ,Warning Status" "0,1"
|
|
bitfld.long 0x00 23. " EP ,Error Passive" "0,1"
|
|
bitfld.long 0x00 22. " ELO ,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEU ,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x00 19. " DRX ,Message Stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x00 18. " TOO ,Timeout Occurred" "0,1"
|
|
bitfld.long 0x00 17. " MRAF ,Message RAM Access Failure" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " TSW ,Timestamp Wraparound" "0,1"
|
|
bitfld.long 0x00 15. " TEFL ,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 14. " TEFF ,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 13. " TEFW ,Tx Event FIFO Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " TEFN ,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x00 11. " TFE ,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x00 10. " TCF ,Transmission Cancellation Finished" "0,1"
|
|
bitfld.long 0x00 9. " TC ,Transmission Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " HPM ,High Priority Message" "0,1"
|
|
bitfld.long 0x00 7. " RF1L ,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x00 5. " RF1W ,Rx FIFO 1 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " RF1N ,Rx FIFO 1 New Message" "0,1"
|
|
bitfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 1. " RF0W ,Rx FIFO 0 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " RF0N ,Rx FIFO 0 New Message" "0,1"
|
|
group.long (d:0x0005C600+0x2A)++0x03
|
|
line.long 0x00 "MCAN_IE,MCAN Interrupt Enable"
|
|
bitfld.long 0x00 29. " ARAE ,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x00 28. " PEDE ,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x00 27. " PEAE ,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x00 26. " WDIE ,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BOE ,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x00 24. " EWE ,Warning Status Enable" "0,1"
|
|
bitfld.long 0x00 23. " EPE ,Error Passive Enable" "0,1"
|
|
bitfld.long 0x00 22. " ELOE ,Error Logging Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEUE ,Bit Error Uncorrected Enable" "0,1"
|
|
bitfld.long 0x00 20. " BECE ,Bit Error Corrected Enable" "0,1"
|
|
bitfld.long 0x00 19. " DRXE ,Message Stored to Dedicated Rx Buffer Enable" "0,1"
|
|
bitfld.long 0x00 18. " TOOE ,Timeout Occurred Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MRAFE ,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x00 16. " TSWE ,Timestamp Wraparound Enable" "0,1"
|
|
bitfld.long 0x00 15. " TEFLE ,Tx Event FIFO Element Lost Enable" "0,1"
|
|
bitfld.long 0x00 14. " TEFFE ,Tx Event FIFO Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " TEFWE ,Tx Event FIFO Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 12. " TEFNE ,Tx Event FIFO New Entry Enable" "0,1"
|
|
bitfld.long 0x00 11. " TFEE ,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x00 10. " TCFE ,Transmission Cancellation Finished Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " TCE ,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x00 8. " HPME ,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x00 7. " RF1LE ,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 6. " RF1FE ,Rx FIFO 1 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " RF1WE ,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 4. " RF1NE ,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x00 3. " RF0LE ,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 2. " RF0FE ,Rx FIFO 0 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " RF0WE ,Rx FIFO 0 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 0. " RF0NE ,Rx FIFO 0 New Message Enable" "0,1"
|
|
group.long (d:0x0005C600+0x2C)++0x03
|
|
line.long 0x00 "MCAN_ILS,MCAN Interrupt Line Select"
|
|
bitfld.long 0x00 29. " ARAL ,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x00 28. " PEDL ,Protocol Error in Data Phase Line" "0,1"
|
|
bitfld.long 0x00 27. " PEAL ,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x00 26. " WDIL ,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BOL ,Bus_Off Status Line" "0,1"
|
|
bitfld.long 0x00 24. " EWL ,Warning Status Line" "0,1"
|
|
bitfld.long 0x00 23. " EPL ,Error Passive Line" "0,1"
|
|
bitfld.long 0x00 22. " ELOL ,Error Logging Overflow Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEUL ,Bit Error Uncorrected Line" "0,1"
|
|
bitfld.long 0x00 20. " BECL ,Bit Error Corrected Line" "0,1"
|
|
bitfld.long 0x00 19. " DRXL ,Message Stored to Dedicated Rx Buffer Line" "0,1"
|
|
bitfld.long 0x00 18. " TOOL ,Timeout Occurred Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MRAFL ,Message RAM Access Failure Line" "0,1"
|
|
bitfld.long 0x00 16. " TSWL ,Timestamp Wraparound Line" "0,1"
|
|
bitfld.long 0x00 15. " TEFLL ,Tx Event FIFO Element Lost Line" "0,1"
|
|
bitfld.long 0x00 14. " TEFFL ,Tx Event FIFO Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " TEFWL ,Tx Event FIFO Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 12. " TEFNL ,Tx Event FIFO New Entry Line" "0,1"
|
|
bitfld.long 0x00 11. " TFEL ,Tx FIFO Empty Line" "0,1"
|
|
bitfld.long 0x00 10. " TCFL ,Transmission Cancellation Finished Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " TCL ,Transmission Completed Line" "0,1"
|
|
bitfld.long 0x00 8. " HPML ,High Priority Message Line" "0,1"
|
|
bitfld.long 0x00 7. " RF1LL ,Rx FIFO 1 Message Lost Line" "0,1"
|
|
bitfld.long 0x00 6. " RF1FL ,Rx FIFO 1 Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " RF1WL ,Rx FIFO 1 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 4. " RF1NL ,Rx FIFO 1 New Message Line" "0,1"
|
|
bitfld.long 0x00 3. " RF0LL ,Rx FIFO 0 Message Lost Line" "0,1"
|
|
bitfld.long 0x00 2. " RF0FL ,Rx FIFO 0 Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " RF0WL ,Rx FIFO 0 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 0. " RF0NL ,Rx FIFO 0 New Message Line" "0,1"
|
|
group.long (d:0x0005C600+0x2E)++0x03
|
|
line.long 0x00 "MCAN_ILE,MCAN Interrupt Line Enable"
|
|
bitfld.long 0x00 1. " EINT1 ,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0x00 0. " EINT0 ,Enable Interrupt Line 0" "0,1"
|
|
group.long (d:0x0005C600+0x40)++0x03
|
|
line.long 0x00 "MCAN_GFC,MCAN Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. " RRFS ,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x00 0. " RRFE ,Reject Remote Frames Extended" "0,1"
|
|
group.long (d:0x0005C600+0x42)++0x03
|
|
line.long 0x00 "MCAN_SIDFC,MCAN Standard ID Filter Configuration"
|
|
hexmask.long 0x00 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
group.long (d:0x0005C600+0x44)++0x03
|
|
line.long 0x00 "MCAN_XIDFC,MCAN Extended ID Filter Configuration"
|
|
bitfld.long 0x00 16.--22. " LSE ,List Size Extended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long (d:0x0005C600+0x48)++0x03
|
|
line.long 0x00 "MCAN_XIDAM,MCAN Extended ID and Mask"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long (d:0x0005C600+0x4A)++0x03
|
|
line.long 0x00 "MCAN_HPMS,MCAN High Priority Message Status"
|
|
bitfld.long 0x00 15. " FLST ,Filter List" "0,1"
|
|
bitfld.long 0x00 8.--14. " FIDX ,Filter Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 6.--7. " MSI ,Message Storage Indicator" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BIDX ,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C600+0x4C)++0x03
|
|
line.long 0x00 "MCAN_NDAT1,MCAN New Data 1"
|
|
bitfld.long 0x00 31. " ND31 ,New Data RX Buffer 31" "0,1"
|
|
bitfld.long 0x00 30. " ND30 ,New Data RX Buffer 30" "0,1"
|
|
bitfld.long 0x00 29. " ND29 ,New Data RX Buffer 29" "0,1"
|
|
bitfld.long 0x00 28. " ND28 ,New Data RX Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ND27 ,New Data RX Buffer 27" "0,1"
|
|
bitfld.long 0x00 26. " ND26 ,New Data RX Buffer 26" "0,1"
|
|
bitfld.long 0x00 25. " ND25 ,New Data RX Buffer 25" "0,1"
|
|
bitfld.long 0x00 24. " ND24 ,New Data RX Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ND23 ,New Data RX Buffer 23" "0,1"
|
|
bitfld.long 0x00 22. " ND22 ,New Data RX Buffer 22" "0,1"
|
|
bitfld.long 0x00 21. " ND21 ,New Data RX Buffer 21" "0,1"
|
|
bitfld.long 0x00 20. " ND20 ,New Data RX Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ND19 ,New Data RX Buffer 19" "0,1"
|
|
bitfld.long 0x00 18. " ND18 ,New Data RX Buffer 18" "0,1"
|
|
bitfld.long 0x00 17. " ND17 ,New Data RX Buffer 17" "0,1"
|
|
bitfld.long 0x00 16. " ND16 ,New Data RX Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ND15 ,New Data RX Buffer 15" "0,1"
|
|
bitfld.long 0x00 14. " ND14 ,New Data RX Buffer 14" "0,1"
|
|
bitfld.long 0x00 13. " ND13 ,New Data RX Buffer 13" "0,1"
|
|
bitfld.long 0x00 12. " ND12 ,New Data RX Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ND11 ,New Data RX Buffer 11" "0,1"
|
|
bitfld.long 0x00 10. " ND10 ,New Data RX Buffer 10" "0,1"
|
|
bitfld.long 0x00 9. " ND9 ,New Data RX Buffer 9" "0,1"
|
|
bitfld.long 0x00 8. " ND8 ,New Data RX Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ND7 ,New Data RX Buffer 7" "0,1"
|
|
bitfld.long 0x00 6. " ND6 ,New Data RX Buffer 6" "0,1"
|
|
bitfld.long 0x00 5. " ND5 ,New Data RX Buffer 5" "0,1"
|
|
bitfld.long 0x00 4. " ND4 ,New Data RX Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ND3 ,New Data RX Buffer 3" "0,1"
|
|
bitfld.long 0x00 2. " ND2 ,New Data RX Buffer 2" "0,1"
|
|
bitfld.long 0x00 1. " ND1 ,New Data RX Buffer 1" "0,1"
|
|
bitfld.long 0x00 0. " ND0 ,New Data RX Buffer 0" "0,1"
|
|
group.long (d:0x0005C600+0x4E)++0x03
|
|
line.long 0x00 "MCAN_NDAT2,MCAN New Data 2"
|
|
bitfld.long 0x00 31. " ND63 ,New Data RX Buffer 63" "0,1"
|
|
bitfld.long 0x00 30. " ND62 ,New Data RX Buffer 62" "0,1"
|
|
bitfld.long 0x00 29. " ND61 ,New Data RX Buffer 61" "0,1"
|
|
bitfld.long 0x00 28. " ND60 ,New Data RX Buffer 60" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ND59 ,New Data RX Buffer 59" "0,1"
|
|
bitfld.long 0x00 26. " ND58 ,New Data RX Buffer 58" "0,1"
|
|
bitfld.long 0x00 25. " ND57 ,New Data RX Buffer 57" "0,1"
|
|
bitfld.long 0x00 24. " ND56 ,New Data RX Buffer 56" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ND55 ,New Data RX Buffer 55" "0,1"
|
|
bitfld.long 0x00 22. " ND54 ,New Data RX Buffer 54" "0,1"
|
|
bitfld.long 0x00 21. " ND53 ,New Data RX Buffer 53" "0,1"
|
|
bitfld.long 0x00 20. " ND52 ,New Data RX Buffer 52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ND51 ,New Data RX Buffer 51" "0,1"
|
|
bitfld.long 0x00 18. " ND50 ,New Data RX Buffer 50" "0,1"
|
|
bitfld.long 0x00 17. " ND49 ,New Data RX Buffer 49" "0,1"
|
|
bitfld.long 0x00 16. " ND48 ,New Data RX Buffer 48" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ND47 ,New Data RX Buffer 47" "0,1"
|
|
bitfld.long 0x00 14. " ND46 ,New Data RX Buffer 46" "0,1"
|
|
bitfld.long 0x00 13. " ND45 ,New Data RX Buffer 45" "0,1"
|
|
bitfld.long 0x00 12. " ND44 ,New Data RX Buffer 44" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ND43 ,New Data RX Buffer 43" "0,1"
|
|
bitfld.long 0x00 10. " ND42 ,New Data RX Buffer 42" "0,1"
|
|
bitfld.long 0x00 9. " ND41 ,New Data RX Buffer 41" "0,1"
|
|
bitfld.long 0x00 8. " ND40 ,New Data RX Buffer 40" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ND39 ,New Data RX Buffer 39" "0,1"
|
|
bitfld.long 0x00 6. " ND38 ,New Data RX Buffer 38" "0,1"
|
|
bitfld.long 0x00 5. " ND37 ,New Data RX Buffer 37" "0,1"
|
|
bitfld.long 0x00 4. " ND36 ,New Data RX Buffer 36" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ND35 ,New Data RX Buffer 35" "0,1"
|
|
bitfld.long 0x00 2. " ND34 ,New Data RX Buffer 34" "0,1"
|
|
bitfld.long 0x00 1. " ND33 ,New Data RX Buffer 33" "0,1"
|
|
bitfld.long 0x00 0. " ND32 ,New Data RX Buffer 32" "0,1"
|
|
group.long (d:0x0005C600+0x50)++0x03
|
|
line.long 0x00 "MCAN_RXF0C,MCAN Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "0,1"
|
|
bitfld.long 0x00 24.--30. " F0WM ,Rx FIFO 0 Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 16.--22. " F0S ,Rx FIFO 0 Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long (d:0x0005C600+0x52)++0x03
|
|
line.long 0x00 "MCAN_RXF0S,MCAN Rx FIFO 0 Status"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--6. " F0FL ,Rx FIFO 0 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x0005C600+0x54)++0x03
|
|
line.long 0x00 "MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C600+0x56)++0x03
|
|
line.long 0x00 "MCAN_RXBC,MCAN Rx Buffer Configuration"
|
|
hexmask.long 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
group.long (d:0x0005C600+0x58)++0x03
|
|
line.long 0x00 "MCAN_RXF1C,MCAN Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 Operation Mode" "0,1"
|
|
bitfld.long 0x00 24.--30. " F1WM ,Rx FIFO 1 Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 16.--22. " F1S ,Rx FIFO 1 Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long (d:0x0005C600+0x5A)++0x03
|
|
line.long 0x00 "MCAN_RXF1S,MCAN Rx FIFO 1 Status"
|
|
bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "0,1,2,3"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--6. " F1FL ,Rx FIFO 1 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x0005C600+0x5C)++0x03
|
|
line.long 0x00 "MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long (d:0x0005C600+0x5E)++0x03
|
|
line.long 0x00 "MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
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|
group.long (d:0x0005C600+0x60)++0x03
|
|
line.long 0x00 "MCAN_TXBC,MCAN Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "0,1"
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|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long (d:0x0005C600+0x62)++0x03
|
|
line.long 0x00 "MCAN_TXFQS,MCAN Tx FIFO / Queue Status"
|
|
bitfld.long 0x00 21. " TFQF ,Tx FIFO/Queue Full" "0,1"
|
|
bitfld.long 0x00 16.--20. " TFQP ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--5. " TFFL ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long (d:0x0005C600+0x64)++0x03
|
|
line.long 0x00 "MCAN_TXESC,MCAN Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x0005C600+0x66)++0x03
|
|
line.long 0x00 "MCAN_TXBRP,MCAN Tx Buffer Request Pending"
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|
bitfld.long 0x00 31. " TRP31 ,Transmission Request Pending 31" "0,1"
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|
bitfld.long 0x00 30. " TRP30 ,Transmission Request Pending 30" "0,1"
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|
bitfld.long 0x00 29. " TRP29 ,Transmission Request Pending 29" "0,1"
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|
bitfld.long 0x00 28. " TRP28 ,Transmission Request Pending 28" "0,1"
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|
newline
|
|
bitfld.long 0x00 27. " TRP27 ,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x00 26. " TRP26 ,Transmission Request Pending 26" "0,1"
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|
bitfld.long 0x00 25. " TRP25 ,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x00 24. " TRP24 ,Transmission Request Pending 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TRP23 ,Transmission Request Pending 23" "0,1"
|
|
bitfld.long 0x00 22. " TRP22 ,Transmission Request Pending 22" "0,1"
|
|
bitfld.long 0x00 21. " TRP21 ,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x00 20. " TRP20 ,Transmission Request Pending 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TRP19 ,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x00 18. " TRP18 ,Transmission Request Pending 18" "0,1"
|
|
bitfld.long 0x00 17. " TRP17 ,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x00 16. " TRP16 ,Transmission Request Pending 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TRP15 ,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x00 14. " TRP14 ,Transmission Request Pending 14" "0,1"
|
|
bitfld.long 0x00 13. " TRP13 ,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x00 12. " TRP12 ,Transmission Request Pending 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TRP11 ,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x00 10. " TRP10 ,Transmission Request Pending 10" "0,1"
|
|
bitfld.long 0x00 9. " TRP9 ,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x00 8. " TRP8 ,Transmission Request Pending 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TRP7 ,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x00 6. " TRP6 ,Transmission Request Pending 6" "0,1"
|
|
bitfld.long 0x00 5. " TRP5 ,Transmission Request Pending 5" "0,1"
|
|
bitfld.long 0x00 4. " TRP4 ,Transmission Request Pending 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TRP3 ,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x00 2. " TRP2 ,Transmission Request Pending 2" "0,1"
|
|
bitfld.long 0x00 1. " TRP1 ,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x00 0. " TRP0 ,Transmission Request Pending 0" "0,1"
|
|
group.long (d:0x0005C600+0x68)++0x03
|
|
line.long 0x00 "MCAN_TXBAR,MCAN Tx Buffer Add Request"
|
|
bitfld.long 0x00 31. " AR31 ,Add Request 31" "0,1"
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|
bitfld.long 0x00 30. " AR30 ,Add Request 30" "0,1"
|
|
bitfld.long 0x00 29. " AR29 ,Add Request 29" "0,1"
|
|
bitfld.long 0x00 28. " AR28 ,Add Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " AR27 ,Add Request 27" "0,1"
|
|
bitfld.long 0x00 26. " AR26 ,Add Request 26" "0,1"
|
|
bitfld.long 0x00 25. " AR25 ,Add Request 25" "0,1"
|
|
bitfld.long 0x00 24. " AR24 ,Add Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " AR23 ,Add Request 23" "0,1"
|
|
bitfld.long 0x00 22. " AR22 ,Add Request 22" "0,1"
|
|
bitfld.long 0x00 21. " AR21 ,Add Request 21" "0,1"
|
|
bitfld.long 0x00 20. " AR20 ,Add Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " AR19 ,Add Request 19" "0,1"
|
|
bitfld.long 0x00 18. " AR18 ,Add Request 18" "0,1"
|
|
bitfld.long 0x00 17. " AR17 ,Add Request 17" "0,1"
|
|
bitfld.long 0x00 16. " AR16 ,Add Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " AR15 ,Add Request 15" "0,1"
|
|
bitfld.long 0x00 14. " AR14 ,Add Request 14" "0,1"
|
|
bitfld.long 0x00 13. " AR13 ,Add Request 13" "0,1"
|
|
bitfld.long 0x00 12. " AR12 ,Add Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " AR11 ,Add Request 11" "0,1"
|
|
bitfld.long 0x00 10. " AR10 ,Add Request 10" "0,1"
|
|
bitfld.long 0x00 9. " AR9 ,Add Request 9" "0,1"
|
|
bitfld.long 0x00 8. " AR8 ,Add Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " AR7 ,Add Request 7" "0,1"
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|
bitfld.long 0x00 6. " AR6 ,Add Request 6" "0,1"
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|
bitfld.long 0x00 5. " AR5 ,Add Request 5" "0,1"
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|
bitfld.long 0x00 4. " AR4 ,Add Request 4" "0,1"
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|
newline
|
|
bitfld.long 0x00 3. " AR3 ,Add Request 3" "0,1"
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|
bitfld.long 0x00 2. " AR2 ,Add Request 2" "0,1"
|
|
bitfld.long 0x00 1. " AR1 ,Add Request 1" "0,1"
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|
bitfld.long 0x00 0. " AR0 ,Add Request 0" "0,1"
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|
group.long (d:0x0005C600+0x6A)++0x03
|
|
line.long 0x00 "MCAN_TXBCR,MCAN Tx Buffer Cancellation Request"
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|
bitfld.long 0x00 31. " CR31 ,Cancellation Request 31" "0,1"
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|
bitfld.long 0x00 30. " CR30 ,Cancellation Request 30" "0,1"
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|
bitfld.long 0x00 29. " CR29 ,Cancellation Request 29" "0,1"
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|
bitfld.long 0x00 28. " CR28 ,Cancellation Request 28" "0,1"
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|
newline
|
|
bitfld.long 0x00 27. " CR27 ,Cancellation Request 27" "0,1"
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|
bitfld.long 0x00 26. " CR26 ,Cancellation Request 26" "0,1"
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|
bitfld.long 0x00 25. " CR25 ,Cancellation Request 25" "0,1"
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|
bitfld.long 0x00 24. " CR24 ,Cancellation Request 24" "0,1"
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|
newline
|
|
bitfld.long 0x00 23. " CR23 ,Cancellation Request 23" "0,1"
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|
bitfld.long 0x00 22. " CR22 ,Cancellation Request 22" "0,1"
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|
bitfld.long 0x00 21. " CR21 ,Cancellation Request 21" "0,1"
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|
bitfld.long 0x00 20. " CR20 ,Cancellation Request 20" "0,1"
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|
newline
|
|
bitfld.long 0x00 19. " CR19 ,Cancellation Request 19" "0,1"
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|
bitfld.long 0x00 18. " CR18 ,Cancellation Request 18" "0,1"
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|
bitfld.long 0x00 17. " CR17 ,Cancellation Request 17" "0,1"
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|
bitfld.long 0x00 16. " CR16 ,Cancellation Request 16" "0,1"
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|
newline
|
|
bitfld.long 0x00 15. " CR15 ,Cancellation Request 15" "0,1"
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|
bitfld.long 0x00 14. " CR14 ,Cancellation Request 14" "0,1"
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|
bitfld.long 0x00 13. " CR13 ,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x00 12. " CR12 ,Cancellation Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CR11 ,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x00 10. " CR10 ,Cancellation Request 10" "0,1"
|
|
bitfld.long 0x00 9. " CR9 ,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x00 8. " CR8 ,Cancellation Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CR7 ,Cancellation Request 7" "0,1"
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|
bitfld.long 0x00 6. " CR6 ,Cancellation Request 6" "0,1"
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|
bitfld.long 0x00 5. " CR5 ,Cancellation Request 5" "0,1"
|
|
bitfld.long 0x00 4. " CR4 ,Cancellation Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CR3 ,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x00 2. " CR2 ,Cancellation Request 2" "0,1"
|
|
bitfld.long 0x00 1. " CR1 ,Cancellation Request 1" "0,1"
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|
bitfld.long 0x00 0. " CR0 ,Cancellation Request 0" "0,1"
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|
rgroup.long (d:0x0005C600+0x6C)++0x03
|
|
line.long 0x00 "MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x00 31. " TO31 ,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x00 30. " TO30 ,Transmission Occurred 30" "0,1"
|
|
bitfld.long 0x00 29. " TO29 ,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x00 28. " TO28 ,Transmission Occurred 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " TO27 ,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x00 26. " TO26 ,Transmission Occurred 26" "0,1"
|
|
bitfld.long 0x00 25. " TO25 ,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x00 24. " TO24 ,Transmission Occurred 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TO23 ,Transmission Occurred 23" "0,1"
|
|
bitfld.long 0x00 22. " TO22 ,Transmission Occurred 22" "0,1"
|
|
bitfld.long 0x00 21. " TO21 ,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x00 20. " TO20 ,Transmission Occurred 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TO19 ,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x00 18. " TO18 ,Transmission Occurred 18" "0,1"
|
|
bitfld.long 0x00 17. " TO17 ,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x00 16. " TO16 ,Transmission Occurred 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TO15 ,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x00 14. " TO14 ,Transmission Occurred 14" "0,1"
|
|
bitfld.long 0x00 13. " TO13 ,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x00 12. " TO12 ,Transmission Occurred 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TO11 ,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x00 10. " TO10 ,Transmission Occurred 10" "0,1"
|
|
bitfld.long 0x00 9. " TO9 ,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x00 8. " TO8 ,Transmission Occurred 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TO7 ,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x00 6. " TO6 ,Transmission Occurred 6" "0,1"
|
|
bitfld.long 0x00 5. " TO5 ,Transmission Occurred 5" "0,1"
|
|
bitfld.long 0x00 4. " TO4 ,Transmission Occurred 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TO3 ,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x00 2. " TO2 ,Transmission Occurred 2" "0,1"
|
|
bitfld.long 0x00 1. " TO1 ,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x00 0. " TO0 ,Transmission Occurred 0" "0,1"
|
|
rgroup.long (d:0x0005C600+0x6E)++0x03
|
|
line.long 0x00 "MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x00 31. " CF31 ,Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x00 30. " CF30 ,Cancellation Finished 30" "0,1"
|
|
bitfld.long 0x00 29. " CF29 ,Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x00 28. " CF28 ,Cancellation Finished 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CF27 ,Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x00 26. " CF26 ,Cancellation Finished 26" "0,1"
|
|
bitfld.long 0x00 25. " CF25 ,Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x00 24. " CF24 ,Cancellation Finished 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CF23 ,Cancellation Finished 23" "0,1"
|
|
bitfld.long 0x00 22. " CF22 ,Cancellation Finished 22" "0,1"
|
|
bitfld.long 0x00 21. " CF21 ,Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x00 20. " CF20 ,Cancellation Finished 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CF19 ,Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x00 18. " CF18 ,Cancellation Finished 18" "0,1"
|
|
bitfld.long 0x00 17. " CF17 ,Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x00 16. " CF16 ,Cancellation Finished 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CF15 ,Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x00 14. " CF14 ,Cancellation Finished 14" "0,1"
|
|
bitfld.long 0x00 13. " CF13 ,Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x00 12. " CF12 ,Cancellation Finished 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CF11 ,Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x00 10. " CF10 ,Cancellation Finished 10" "0,1"
|
|
bitfld.long 0x00 9. " CF9 ,Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x00 8. " CF8 ,Cancellation Finished 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CF7 ,Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x00 6. " CF6 ,Cancellation Finished 6" "0,1"
|
|
bitfld.long 0x00 5. " CF5 ,Cancellation Finished 5" "0,1"
|
|
bitfld.long 0x00 4. " CF4 ,Cancellation Finished 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CF3 ,Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x00 2. " CF2 ,Cancellation Finished 2" "0,1"
|
|
bitfld.long 0x00 1. " CF1 ,Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x00 0. " CF0 ,Cancellation Finished 0" "0,1"
|
|
group.long (d:0x0005C600+0x70)++0x03
|
|
line.long 0x00 "MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x00 31. " TIE31 ,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x00 30. " TIE30 ,Transmission Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x00 29. " TIE29 ,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x00 28. " TIE28 ,Transmission Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " TIE27 ,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x00 26. " TIE26 ,Transmission Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x00 25. " TIE25 ,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x00 24. " TIE24 ,Transmission Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TIE23 ,Transmission Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x00 22. " TIE22 ,Transmission Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x00 21. " TIE21 ,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x00 20. " TIE20 ,Transmission Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TIE19 ,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x00 18. " TIE18 ,Transmission Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x00 17. " TIE17 ,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x00 16. " TIE16 ,Transmission Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TIE15 ,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x00 14. " TIE14 ,Transmission Interrupt Enable 14" "0,1"
|
|
bitfld.long 0x00 13. " TIE13 ,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x00 12. " TIE12 ,Transmission Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TIE11 ,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x00 10. " TIE10 ,Transmission Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x00 9. " TIE9 ,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x00 8. " TIE8 ,Transmission Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TIE7 ,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x00 6. " TIE6 ,Transmission Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x00 5. " TIE5 ,Transmission Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x00 4. " TIE4 ,Transmission Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TIE3 ,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x00 2. " TIE2 ,Transmission Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x00 1. " TIE1 ,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x00 0. " TIE0 ,Transmission Interrupt Enable 0" "0,1"
|
|
group.long (d:0x0005C600+0x72)++0x03
|
|
line.long 0x00 "MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x00 31. " CFIE31 ,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x00 30. " CFIE30 ,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x00 29. " CFIE29 ,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x00 28. " CFIE28 ,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CFIE27 ,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x00 26. " CFIE26 ,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x00 25. " CFIE25 ,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x00 24. " CFIE24 ,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CFIE23 ,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x00 22. " CFIE22 ,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x00 21. " CFIE21 ,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x00 20. " CFIE20 ,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CFIE19 ,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x00 18. " CFIE18 ,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x00 17. " CFIE17 ,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x00 16. " CFIE16 ,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CFIE15 ,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x00 14. " CFIE14 ,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
bitfld.long 0x00 13. " CFIE13 ,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x00 12. " CFIE12 ,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CFIE11 ,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x00 10. " CFIE10 ,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x00 9. " CFIE9 ,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x00 8. " CFIE8 ,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CFIE7 ,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x00 6. " CFIE6 ,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x00 5. " CFIE5 ,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x00 4. " CFIE4 ,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CFIE3 ,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x00 2. " CFIE2 ,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x00 1. " CFIE1 ,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x00 0. " CFIE0 ,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long (d:0x0005C600+0x78)++0x03
|
|
line.long 0x00 "MCAN_TXEFC,MCAN Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long (d:0x0005C600+0x7A)++0x03
|
|
line.long 0x00 "MCAN_TXEFS,MCAN Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C600+0x7C)++0x03
|
|
line.long 0x00 "MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "McanErrorRegs"
|
|
width 25.
|
|
rgroup.long (d:0x0005C800+0x00)++0x03
|
|
line.long 0x00 "MCANERR_REV,MCAN Error Aggregator Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C800+0x04)++0x03
|
|
line.long 0x00 "MCANERR_VECTOR,MCAN ECC Vector Register"
|
|
rbitfld.long 0x00 24. " RD_SVBUS_DONE ,Read Completion Flag" "0,1"
|
|
hexmask.long 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset"
|
|
bitfld.long 0x00 15. " RD_SVBUS ,Read Trigger" "0,1"
|
|
hexmask.long 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID"
|
|
rgroup.long (d:0x0005C800+0x06)++0x03
|
|
line.long 0x00 "MCANERR_STAT,MCAN Error Misc Status"
|
|
hexmask.long 0x00 0.--10. 1. "NUM_RAMS,Number of RAMs"
|
|
rgroup.long (d:0x0005C800+0x08)++0x03
|
|
line.long 0x00 "MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C800+0x0A)++0x03
|
|
line.long 0x00 "MCANERR_CTRL,MCAN ECC Control"
|
|
bitfld.long 0x00 8. " CHECK_SVBUS_TIMEOUT ,SVBUS Timeout Enable" "0,1"
|
|
bitfld.long 0x00 6. " ERROR_ONCE ,Force Error Only Once Enable" "0,1"
|
|
bitfld.long 0x00 5. " FORCE_N_ROW ,Force Next Single/Double Bit Error" "0,1"
|
|
bitfld.long 0x00 4. " FORCE_DED ,Force Double Bit Error Detected Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FORCE_SEC ,Force Single Bit Error Corrected Error" "0,1"
|
|
bitfld.long 0x00 2. " ENABLE_RMW ,Enable Read-Modify-Write" "0,1"
|
|
bitfld.long 0x00 1. " ECC_CHECK ,Enable ECC Check" "0,1"
|
|
bitfld.long 0x00 0. " ECC_ENABLE ,Enable ECC Generation" "0,1"
|
|
group.long (d:0x0005C800+0x0C)++0x03
|
|
line.long 0x00 "MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register"
|
|
group.long (d:0x0005C800+0x0E)++0x03
|
|
line.long 0x00 "MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register"
|
|
hexmask.long 0x00 16.--31. 1. "ECC_BIT2,Force Error Bit2 Column Index"
|
|
hexmask.long 0x00 0.--15. 1. "ECC_BIT1,Force Error Bit1 Column Index"
|
|
group.long (d:0x0005C800+0x10)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register"
|
|
hexmask.long 0x00 16.--31. 1. "ECC_BIT1,ECC Error Bit Position"
|
|
bitfld.long 0x00 15. " CLR_CTRL_REG_ERROR ,Clear Control Register Error" "0,1"
|
|
bitfld.long 0x00 12. " CLR_ECC_OTHER ,Clear ECC_OTHER" "0,1"
|
|
bitfld.long 0x00 10.--11. " CLR_ECC_DED ,Clear ECC_DED" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CLR_ECC_SEC ,Clear ECC_SEC" "0,1,2,3"
|
|
bitfld.long 0x00 7. " CTRL_REG_ERROR ,Control Register Error" "0,1"
|
|
bitfld.long 0x00 4. " ECC_OTHER ,SEC While Writeback Error Status" "0,1"
|
|
bitfld.long 0x00 2.--3. " ECC_DED ,Double Bit Error Detected Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " ECC_SEC ,Single Bit Error Corrected Status" "0,1,2,3"
|
|
rgroup.long (d:0x0005C800+0x12)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register"
|
|
rgroup.long (d:0x0005C800+0x14)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register"
|
|
bitfld.long 0x00 9. " CLR_SVBUS_TIMEOUT ,Clear Serial VBUS Timeout" "0,1"
|
|
bitfld.long 0x00 1. " SVBUS_TIMEOUT ,Serial VBUS Timeout Flag" "0,1"
|
|
rbitfld.long 0x00 0. " WB_PEND ,Delayed Write Back Pending Status" "0,1"
|
|
group.long (d:0x0005C800+0x1E)++0x03
|
|
line.long 0x00 "MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI_WR ,End of Interrupt" "0,1"
|
|
group.long (d:0x0005C800+0x20)++0x03
|
|
line.long 0x00 "MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register"
|
|
bitfld.long 0x00 0. " MSGMEM_PEND ,Message RAM SEC Interrupt Pending" "0,1"
|
|
group.long (d:0x0005C800+0x40)++0x03
|
|
line.long 0x00 "MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_SET ,Message RAM SEC Interrupt Pending Enable Set" "0,1"
|
|
group.long (d:0x0005C800+0x60)++0x03
|
|
line.long 0x00 "MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_CLR ,Message RAM SEC Interrupt Pending Enable Clear" "0,1"
|
|
group.long (d:0x0005C800+0x9E)++0x03
|
|
line.long 0x00 "MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI_WR ,End of Interrupt" "0,1"
|
|
group.long (d:0x0005C800+0xA0)++0x03
|
|
line.long 0x00 "MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register"
|
|
bitfld.long 0x00 0. " MSGMEM_PEND ,Message RAM DED Interrupt Pending" "0,1"
|
|
group.long (d:0x0005C800+0xC0)++0x03
|
|
line.long 0x00 "MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_SET ,Message RAM DED Interrupt Pending Enable Set" "0,1"
|
|
group.long (d:0x0005C800+0xE0)++0x03
|
|
line.long 0x00 "MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_CLR ,Message RAM DED Interrupt Pending Enable Clear" "0,1"
|
|
group.long (d:0x0005C800+0x100)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register"
|
|
bitfld.long 0x00 1. " ENABLE_TIMEOUT_SET ,Enable Timeout Errors Set" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE_PARITY_SET ,Enable Parity Errors Set" "0,1"
|
|
group.long (d:0x0005C800+0x102)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register"
|
|
bitfld.long 0x00 1. " ENABLE_TIMEOUT_CLR ,Enable Timeout Errors Clear" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE_PARITY_CLR ,Enable Parity Errors Clear" "0,1"
|
|
group.long (d:0x0005C800+0x104)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register"
|
|
bitfld.long 0x00 2.--3. " SVBUS_TIMEOUT ,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AGGR_PARITY_ERR ,Aggregator Parity Error Status" "0,1,2,3"
|
|
group.long (d:0x0005C800+0x106)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register"
|
|
bitfld.long 0x00 2.--3. " SVBUS_TIMEOUT ,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AGGR_PARITY_ERR ,Aggregator Parity Error Status" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "McanssRegs"
|
|
width 36.
|
|
rgroup.long (d:0x0005C400+0x00)++0x03
|
|
line.long 0x00 "MCANSS_PID,MCAN Subsystem Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x0005C400+0x02)++0x03
|
|
line.long 0x00 "MCANSS_CTRL,MCAN Subsystem Control Register"
|
|
bitfld.long 0x00 6. " EXT_TS_CNTR_EN ,External Timestamp Counter Enable" "0,1"
|
|
bitfld.long 0x00 5. " AUTOWAKEUP ,Automatic Wakeup Enable" "0,1"
|
|
bitfld.long 0x00 4. " WAKEUPREQEN ,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x00 3. " DBGSUSP_FREE ,Debug Suspend Free" "0,1"
|
|
rgroup.long (d:0x0005C400+0x04)++0x03
|
|
line.long 0x00 "MCANSS_STAT,MCAN Subsystem Status Register"
|
|
bitfld.long 0x00 2. " ENABLE_FDOE ,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x00 1. " MEM_INIT_DONE ,Memory Initialization Done" "0,1"
|
|
bitfld.long 0x00 0. " RESET ,Soft Reset Status" "0,1"
|
|
group.long (d:0x0005C400+0x06)++0x03
|
|
line.long 0x00 "MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Clear" "0,1"
|
|
group.long (d:0x0005C400+0x08)++0x03
|
|
line.long 0x00 "MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status" "0,1"
|
|
group.long (d:0x0005C400+0x0A)++0x03
|
|
line.long 0x00 "MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable Clear" "0,1"
|
|
group.long (d:0x0005C400+0x0C)++0x03
|
|
line.long 0x00 "MCANSS_IE,MCAN Subsystem Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable" "0,1"
|
|
rgroup.long (d:0x0005C400+0x0E)++0x03
|
|
line.long 0x00 "MCANSS_IES,MCAN Subsystem Interrupt Enable Status"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable Status" "0,1"
|
|
group.long (d:0x0005C400+0x10)++0x03
|
|
line.long 0x00 "MCANSS_EOI,MCAN Subsystem End of Interrupt"
|
|
hexmask.long 0x00 0.--7. 1. "EOI,External Timestamp Counter Overflow End of Interrupt"
|
|
group.long (d:0x0005C400+0x12)++0x03
|
|
line.long 0x00 "MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0"
|
|
hexmask.long 0x00 0.--23. 1. "PRESCALER,External Timestamp Prescaler"
|
|
rgroup.long (d:0x0005C400+0x14)++0x03
|
|
line.long 0x00 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter"
|
|
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,External Timestamp Counter Unserviced Rollover Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Multichannel Buffered Serial Port (McBSP)"
|
|
tree "Port A"
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width 8.
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group.word (d:0x00006000+0x00)++0x01
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line.word 0x00 "DRR2,Data receive register bits 31-16"
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hexmask.word 0x00 8.--15. 1. "HWHB,High word high byte"
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hexmask.word 0x00 0.--7. 1. "HWLB,High word low byte"
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group.word (d:0x00006000+0x01)++0x01
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line.word 0x00 "DRR1,Data receive register bits 15-0"
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hexmask.word 0x00 8.--15. 1. "LWHB,Low word high byte"
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hexmask.word 0x00 0.--7. 1. "LWLB,Low word low byte"
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group.word (d:0x00006000+0x02)++0x01
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line.word 0x00 "DXR2,Data transmit register bits 31-16"
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hexmask.word 0x00 8.--15. 1. "HWHB,High word high byte"
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hexmask.word 0x00 0.--7. 1. "HWLB,High word low byte"
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group.word (d:0x00006000+0x03)++0x01
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line.word 0x00 "DXR1,Data transmit register bits 15-0"
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hexmask.word 0x00 8.--15. 1. "LWHB,Low word high byte"
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hexmask.word 0x00 0.--7. 1. "LWLB,Low word low byte"
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group.word (d:0x00006000+0x04)++0x01
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line.word 0x00 "SPCR2,Serial port control register 2"
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bitfld.word 0x00 9. " FREE ,FREE bit" "0,1"
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bitfld.word 0x00 8. " SOFT ,SOFT bit" "0,1"
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bitfld.word 0x00 7. " FRST ,Frame sync logic reset" "0,1"
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bitfld.word 0x00 6. " GRST ,Sample rate generator reset" "0,1"
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newline
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bitfld.word 0x00 4.--5. " XINTM ,Transmit Interupt mode bits" "0,1,2,3"
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bitfld.word 0x00 3. " XSYNCERR ,Transmit sync error INT flag" "0,1"
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rbitfld.word 0x00 2. " XEMPTY ,Transmitter empty" "0,1"
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rbitfld.word 0x00 1. " XRDY ,Transmitter ready" "0,1"
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newline
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bitfld.word 0x00 0. " XRST ,Transmitter reset" "0,1"
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group.word (d:0x00006000+0x05)++0x01
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line.word 0x00 "SPCR1,Serial port control register 1"
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bitfld.word 0x00 15. " DLB ,Digital loopback" "0,1"
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bitfld.word 0x00 13.--14. " RJUST ,Rx sign extension and justification mode" "0,1,2,3"
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bitfld.word 0x00 11.--12. " CLKSTP ,Clock stop mode" "0,1,2,3"
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bitfld.word 0x00 7. " DXENA ,DX delay enable" "0,1"
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newline
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bitfld.word 0x00 4.--5. " RINTM ,Receive Interupt mode bits" "0,1,2,3"
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bitfld.word 0x00 3. " RSYNCERR ,Receive sync error INT flag" "0,1"
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rbitfld.word 0x00 2. " RFULL ,Receiver full" "0,1"
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rbitfld.word 0x00 1. " RRDY ,Receiver ready" "0,1"
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newline
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bitfld.word 0x00 0. " RRST ,Receiver reset" "0,1"
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group.word (d:0x00006000+0x06)++0x01
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line.word 0x00 "RCR2,Receive Control register 2"
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bitfld.word 0x00 15. " RPHASE ,Receive Phase" "0,1"
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bitfld.word 0x00 8.--14. " RFRLEN2 ,Receive Frame length 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " RWDLEN2 ,Receive word length 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--4. " RCOMPAND ,Receive Companding Mode selects" "0,1,2,3"
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newline
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bitfld.word 0x00 2. " RFIG ,Receive frame sync ignore" "0,1"
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bitfld.word 0x00 0.--1. " RDATDLY ,Receive data delay" "0,1,2,3"
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group.word (d:0x00006000+0x07)++0x01
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line.word 0x00 "RCR1,Receive Control register 1"
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bitfld.word 0x00 8.--14. " RFRLEN1 ,Receive Frame length 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " RWDLEN1 ,Receive word length 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00006000+0x08)++0x01
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line.word 0x00 "XCR2,Transmit Control register 2"
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bitfld.word 0x00 15. " XPHASE ,Transmit Phase" "0,1"
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bitfld.word 0x00 8.--14. " XFRLEN2 ,Transmit Frame length 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " XWDLEN2 ,Transmit word length 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--4. " XCOMPAND ,Transmit Companding Mode selects" "0,1,2,3"
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newline
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bitfld.word 0x00 2. " XFIG ,Transmit frame sync ignore" "0,1"
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bitfld.word 0x00 0.--1. " XDATDLY ,Transmit data delay" "0,1,2,3"
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group.word (d:0x00006000+0x09)++0x01
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line.word 0x00 "XCR1,Transmit Control register 1"
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bitfld.word 0x00 8.--14. " XFRLEN1 ,Transmit Frame length 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " XWDLEN1 ,Transmit word length 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00006000+0x0A)++0x01
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line.word 0x00 "SRGR2,Sample rate generator register 2"
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bitfld.word 0x00 15. " GSYNC ,CLKG sync" "0,1"
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bitfld.word 0x00 13. " CLKSM ,Sample rate generator mode" "0,1"
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bitfld.word 0x00 12. " FSGM ,Frame sync generator mode" "0,1"
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hexmask.word 0x00 0.--11. 1. "FPER,Frame-sync period"
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group.word (d:0x00006000+0x0B)++0x01
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line.word 0x00 "SRGR1,Sample rate generator register 1"
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hexmask.word 0x00 8.--15. 1. "FWID,Frame width"
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hexmask.word 0x00 0.--7. 1. "CLKGDV,CLKG divider"
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group.word (d:0x00006000+0x0C)++0x01
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line.word 0x00 "MCR2,Multi-channel control register 2"
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bitfld.word 0x00 9. " XMCME ,Transmit Frame length 2" "0,1"
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bitfld.word 0x00 7.--8. " XPBBLK ,Transmit word length 2" "0,1,2,3"
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bitfld.word 0x00 5.--6. " XPABLK ,Transmit Companding Mode selects" "0,1,2,3"
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rbitfld.word 0x00 2.--4. " XCBLK ,Transmit frame sync ignore" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 0.--1. " XMCM ,Transmit data delay" "0,1,2,3"
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group.word (d:0x00006000+0x0D)++0x01
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line.word 0x00 "MCR1,Multi-channel control register 1"
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bitfld.word 0x00 9. " RMCME ,Receive multi-channel enhance mode" "0,1"
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bitfld.word 0x00 7.--8. " RPBBLK ,Receive partition B Block" "0,1,2,3"
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bitfld.word 0x00 5.--6. " RPABLK ,Receive partition A Block" "0,1,2,3"
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rbitfld.word 0x00 2.--4. " RCBLK ,eceive current block" "0,1,2,3,4,5,6,7"
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newline
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bitfld.word 0x00 0. " RMCM ,Receive multichannel mode" "0,1"
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group.word (d:0x00006000+0x0E)++0x01
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line.word 0x00 "RCERA,Receive channel enable partition A"
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group.word (d:0x00006000+0x0F)++0x01
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line.word 0x00 "RCERB,Receive channel enable partition B"
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group.word (d:0x00006000+0x10)++0x01
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line.word 0x00 "XCERA,Transmit channel enable partition A"
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group.word (d:0x00006000+0x11)++0x01
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line.word 0x00 "XCERB,Transmit channel enable partition B"
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group.word (d:0x00006000+0x12)++0x01
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line.word 0x00 "PCR,Pin Control register"
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bitfld.word 0x00 11. " FSXM ,Transmit Frame Synchronization Mode" "0,1"
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bitfld.word 0x00 10. " FSRM ,Receive Frame Synchronization Mode" "0,1"
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bitfld.word 0x00 9. " CLKXM ,Transmit Clock Mode." "0,1"
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bitfld.word 0x00 8. " CLKRM ,Receiver Clock Mode" "0,1"
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newline
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bitfld.word 0x00 7. " SCLKME ,Sample clock mode selection" "0,1"
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bitfld.word 0x00 3. " FSXP ,Transmit Frame synchronization polarity" "0,1"
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rbitfld.word 0x00 2. " FSRP ,Receive Frame synchronization polarity" "0,1"
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rbitfld.word 0x00 1. " CLKXP ,Transmit clock polarity" "0,1"
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newline
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bitfld.word 0x00 0. " CLKRP ,Receive Clock polarity" "0,1"
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group.word (d:0x00006000+0x13)++0x01
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line.word 0x00 "RCERC,Receive channel enable partition C"
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group.word (d:0x00006000+0x14)++0x01
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line.word 0x00 "RCERD,Receive channel enable partition D"
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group.word (d:0x00006000+0x15)++0x01
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line.word 0x00 "XCERC,Transmit channel enable partition C"
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group.word (d:0x00006000+0x16)++0x01
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line.word 0x00 "XCERD,Transmit channel enable partition D"
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group.word (d:0x00006000+0x17)++0x01
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line.word 0x00 "RCERE,Receive channel enable partition E"
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group.word (d:0x00006000+0x18)++0x01
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line.word 0x00 "RCERF,Receive channel enable partition F"
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group.word (d:0x00006000+0x19)++0x01
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line.word 0x00 "XCERE,Transmit channel enable partition E"
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group.word (d:0x00006000+0x1A)++0x01
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line.word 0x00 "XCERF,Transmit channel enable partition F"
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group.word (d:0x00006000+0x1B)++0x01
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line.word 0x00 "RCERG,Receive channel enable partition G"
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group.word (d:0x00006000+0x1C)++0x01
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line.word 0x00 "RCERH,Receive channel enable partition H"
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group.word (d:0x00006000+0x1D)++0x01
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line.word 0x00 "XCERG,Transmit channel enable partition G"
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group.word (d:0x00006000+0x1E)++0x01
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line.word 0x00 "XCERH,Transmit channel enable partition H"
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group.word (d:0x00006000+0x23)++0x01
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line.word 0x00 "MFFINT,Interrupt enable"
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bitfld.word 0x00 2. " RINT ,Enable for transmit Interrupt" "0,1"
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bitfld.word 0x00 0. " XINT ,Enable for Receive Interrupt" "0,1"
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width 0x0B
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tree.end
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tree "Port B"
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width 8.
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group.word (d:0x00006040+0x00)++0x01
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line.word 0x00 "DRR2,Data receive register bits 31-16"
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hexmask.word 0x00 8.--15. 1. "HWHB,High word high byte"
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hexmask.word 0x00 0.--7. 1. "HWLB,High word low byte"
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group.word (d:0x00006040+0x01)++0x01
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line.word 0x00 "DRR1,Data receive register bits 15-0"
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hexmask.word 0x00 8.--15. 1. "LWHB,Low word high byte"
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hexmask.word 0x00 0.--7. 1. "LWLB,Low word low byte"
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group.word (d:0x00006040+0x02)++0x01
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line.word 0x00 "DXR2,Data transmit register bits 31-16"
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hexmask.word 0x00 8.--15. 1. "HWHB,High word high byte"
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hexmask.word 0x00 0.--7. 1. "HWLB,High word low byte"
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group.word (d:0x00006040+0x03)++0x01
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line.word 0x00 "DXR1,Data transmit register bits 15-0"
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hexmask.word 0x00 8.--15. 1. "LWHB,Low word high byte"
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hexmask.word 0x00 0.--7. 1. "LWLB,Low word low byte"
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group.word (d:0x00006040+0x04)++0x01
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line.word 0x00 "SPCR2,Serial port control register 2"
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bitfld.word 0x00 9. " FREE ,FREE bit" "0,1"
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bitfld.word 0x00 8. " SOFT ,SOFT bit" "0,1"
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bitfld.word 0x00 7. " FRST ,Frame sync logic reset" "0,1"
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bitfld.word 0x00 6. " GRST ,Sample rate generator reset" "0,1"
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newline
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bitfld.word 0x00 4.--5. " XINTM ,Transmit Interupt mode bits" "0,1,2,3"
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bitfld.word 0x00 3. " XSYNCERR ,Transmit sync error INT flag" "0,1"
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rbitfld.word 0x00 2. " XEMPTY ,Transmitter empty" "0,1"
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rbitfld.word 0x00 1. " XRDY ,Transmitter ready" "0,1"
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newline
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bitfld.word 0x00 0. " XRST ,Transmitter reset" "0,1"
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group.word (d:0x00006040+0x05)++0x01
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line.word 0x00 "SPCR1,Serial port control register 1"
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bitfld.word 0x00 15. " DLB ,Digital loopback" "0,1"
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bitfld.word 0x00 13.--14. " RJUST ,Rx sign extension and justification mode" "0,1,2,3"
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bitfld.word 0x00 11.--12. " CLKSTP ,Clock stop mode" "0,1,2,3"
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bitfld.word 0x00 7. " DXENA ,DX delay enable" "0,1"
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newline
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bitfld.word 0x00 4.--5. " RINTM ,Receive Interupt mode bits" "0,1,2,3"
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bitfld.word 0x00 3. " RSYNCERR ,Receive sync error INT flag" "0,1"
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rbitfld.word 0x00 2. " RFULL ,Receiver full" "0,1"
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rbitfld.word 0x00 1. " RRDY ,Receiver ready" "0,1"
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newline
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bitfld.word 0x00 0. " RRST ,Receiver reset" "0,1"
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group.word (d:0x00006040+0x06)++0x01
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line.word 0x00 "RCR2,Receive Control register 2"
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bitfld.word 0x00 15. " RPHASE ,Receive Phase" "0,1"
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bitfld.word 0x00 8.--14. " RFRLEN2 ,Receive Frame length 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " RWDLEN2 ,Receive word length 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--4. " RCOMPAND ,Receive Companding Mode selects" "0,1,2,3"
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newline
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bitfld.word 0x00 2. " RFIG ,Receive frame sync ignore" "0,1"
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bitfld.word 0x00 0.--1. " RDATDLY ,Receive data delay" "0,1,2,3"
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group.word (d:0x00006040+0x07)++0x01
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line.word 0x00 "RCR1,Receive Control register 1"
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bitfld.word 0x00 8.--14. " RFRLEN1 ,Receive Frame length 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " RWDLEN1 ,Receive word length 1" "0,1,2,3,4,5,6,7"
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group.word (d:0x00006040+0x08)++0x01
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line.word 0x00 "XCR2,Transmit Control register 2"
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bitfld.word 0x00 15. " XPHASE ,Transmit Phase" "0,1"
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bitfld.word 0x00 8.--14. " XFRLEN2 ,Transmit Frame length 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
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bitfld.word 0x00 5.--7. " XWDLEN2 ,Transmit word length 2" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 3.--4. " XCOMPAND ,Transmit Companding Mode selects" "0,1,2,3"
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newline
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bitfld.word 0x00 2. " XFIG ,Transmit frame sync ignore" "0,1"
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bitfld.word 0x00 0.--1. " XDATDLY ,Transmit data delay" "0,1,2,3"
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group.word (d:0x00006040+0x09)++0x01
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line.word 0x00 "XCR1,Transmit Control register 1"
|
|
bitfld.word 0x00 8.--14. " XFRLEN1 ,Transmit Frame length 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.word 0x00 5.--7. " XWDLEN1 ,Transmit word length 1" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00006040+0x0A)++0x01
|
|
line.word 0x00 "SRGR2,Sample rate generator register 2"
|
|
bitfld.word 0x00 15. " GSYNC ,CLKG sync" "0,1"
|
|
bitfld.word 0x00 13. " CLKSM ,Sample rate generator mode" "0,1"
|
|
bitfld.word 0x00 12. " FSGM ,Frame sync generator mode" "0,1"
|
|
hexmask.word 0x00 0.--11. 1. "FPER,Frame-sync period"
|
|
group.word (d:0x00006040+0x0B)++0x01
|
|
line.word 0x00 "SRGR1,Sample rate generator register 1"
|
|
hexmask.word 0x00 8.--15. 1. "FWID,Frame width"
|
|
hexmask.word 0x00 0.--7. 1. "CLKGDV,CLKG divider"
|
|
group.word (d:0x00006040+0x0C)++0x01
|
|
line.word 0x00 "MCR2,Multi-channel control register 2"
|
|
bitfld.word 0x00 9. " XMCME ,Transmit Frame length 2" "0,1"
|
|
bitfld.word 0x00 7.--8. " XPBBLK ,Transmit word length 2" "0,1,2,3"
|
|
bitfld.word 0x00 5.--6. " XPABLK ,Transmit Companding Mode selects" "0,1,2,3"
|
|
rbitfld.word 0x00 2.--4. " XCBLK ,Transmit frame sync ignore" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " XMCM ,Transmit data delay" "0,1,2,3"
|
|
group.word (d:0x00006040+0x0D)++0x01
|
|
line.word 0x00 "MCR1,Multi-channel control register 1"
|
|
bitfld.word 0x00 9. " RMCME ,Receive multi-channel enhance mode" "0,1"
|
|
bitfld.word 0x00 7.--8. " RPBBLK ,Receive partition B Block" "0,1,2,3"
|
|
bitfld.word 0x00 5.--6. " RPABLK ,Receive partition A Block" "0,1,2,3"
|
|
rbitfld.word 0x00 2.--4. " RCBLK ,eceive current block" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 0. " RMCM ,Receive multichannel mode" "0,1"
|
|
group.word (d:0x00006040+0x0E)++0x01
|
|
line.word 0x00 "RCERA,Receive channel enable partition A"
|
|
group.word (d:0x00006040+0x0F)++0x01
|
|
line.word 0x00 "RCERB,Receive channel enable partition B"
|
|
group.word (d:0x00006040+0x10)++0x01
|
|
line.word 0x00 "XCERA,Transmit channel enable partition A"
|
|
group.word (d:0x00006040+0x11)++0x01
|
|
line.word 0x00 "XCERB,Transmit channel enable partition B"
|
|
group.word (d:0x00006040+0x12)++0x01
|
|
line.word 0x00 "PCR,Pin Control register"
|
|
bitfld.word 0x00 11. " FSXM ,Transmit Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x00 10. " FSRM ,Receive Frame Synchronization Mode" "0,1"
|
|
bitfld.word 0x00 9. " CLKXM ,Transmit Clock Mode." "0,1"
|
|
bitfld.word 0x00 8. " CLKRM ,Receiver Clock Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. " SCLKME ,Sample clock mode selection" "0,1"
|
|
bitfld.word 0x00 3. " FSXP ,Transmit Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x00 2. " FSRP ,Receive Frame synchronization polarity" "0,1"
|
|
rbitfld.word 0x00 1. " CLKXP ,Transmit clock polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " CLKRP ,Receive Clock polarity" "0,1"
|
|
group.word (d:0x00006040+0x13)++0x01
|
|
line.word 0x00 "RCERC,Receive channel enable partition C"
|
|
group.word (d:0x00006040+0x14)++0x01
|
|
line.word 0x00 "RCERD,Receive channel enable partition D"
|
|
group.word (d:0x00006040+0x15)++0x01
|
|
line.word 0x00 "XCERC,Transmit channel enable partition C"
|
|
group.word (d:0x00006040+0x16)++0x01
|
|
line.word 0x00 "XCERD,Transmit channel enable partition D"
|
|
group.word (d:0x00006040+0x17)++0x01
|
|
line.word 0x00 "RCERE,Receive channel enable partition E"
|
|
group.word (d:0x00006040+0x18)++0x01
|
|
line.word 0x00 "RCERF,Receive channel enable partition F"
|
|
group.word (d:0x00006040+0x19)++0x01
|
|
line.word 0x00 "XCERE,Transmit channel enable partition E"
|
|
group.word (d:0x00006040+0x1A)++0x01
|
|
line.word 0x00 "XCERF,Transmit channel enable partition F"
|
|
group.word (d:0x00006040+0x1B)++0x01
|
|
line.word 0x00 "RCERG,Receive channel enable partition G"
|
|
group.word (d:0x00006040+0x1C)++0x01
|
|
line.word 0x00 "RCERH,Receive channel enable partition H"
|
|
group.word (d:0x00006040+0x1D)++0x01
|
|
line.word 0x00 "XCERG,Transmit channel enable partition G"
|
|
group.word (d:0x00006040+0x1E)++0x01
|
|
line.word 0x00 "XCERH,Transmit channel enable partition H"
|
|
group.word (d:0x00006040+0x23)++0x01
|
|
line.word 0x00 "MFFINT,Interrupt enable"
|
|
bitfld.word 0x00 2. " RINT ,Enable for transmit Interrupt" "0,1"
|
|
bitfld.word 0x00 0. " XINT ,Enable for Receive Interrupt" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Power Management Bus Module (PMBus)"
|
|
width 18.
|
|
group.long (d:0x00006400+0x00)++0x03
|
|
line.long 0x00 "PMBMC,PMBUS Master Mode Control Register"
|
|
bitfld.long 0x00 20. " PRC_CALL ,Master Process Call Message Enable" "0,1"
|
|
bitfld.long 0x00 19. " GRP_CMD ,Master Group Command Message Enable" "0,1"
|
|
bitfld.long 0x00 18. " PEC_ENA ,Master PEC Processing Enable" "0,1"
|
|
bitfld.long 0x00 17. " EXT_CMD ,Master Extended Command Code Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " CMD_ENA ,Master Command Code Enable" "0,1"
|
|
hexmask.long 0x00 8.--15. 1. "BYTE_COUNT,Number of Bytes Transmitted"
|
|
bitfld.long 0x00 1.--7. " SLAVE_ADDR ,Slave Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0. " RW ,RnW bit of the Message" "0,1"
|
|
group.long (d:0x00006400+0x02)++0x03
|
|
line.long 0x00 "PMBTXBUF,PMBUS Transmit Buffer"
|
|
rgroup.long (d:0x00006400+0x04)++0x03
|
|
line.long 0x00 "PMBRXBUF,PMBUS Receive buffer"
|
|
group.long (d:0x00006400+0x06)++0x03
|
|
line.long 0x00 "PMBACK,PMBUS Acknowledge Register"
|
|
bitfld.long 0x00 0. " ACK ,Allows firmware to ack/nack received data" "0,1"
|
|
rgroup.long (d:0x00006400+0x08)++0x03
|
|
line.long 0x00 "PMBSTS,PMBUS Status Register"
|
|
bitfld.long 0x00 21. " SCL_RAW ,PMBus Clock Pin Real Time Status" "0,1"
|
|
bitfld.long 0x00 20. " SDA_RAW ,PMBus Data Pin Real Time Status" "0,1"
|
|
bitfld.long 0x00 19. " CONTROL_RAW ,Control Pin Real Time Status" "0,1"
|
|
bitfld.long 0x00 18. " ALERT_RAW ,Alert Pin Real Time Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " CONTROL_EDGE ,Control Edge Detection Status" "0,1"
|
|
bitfld.long 0x00 16. " ALERT_EDGE ,Alert Edge Detection Status" "0,1"
|
|
bitfld.long 0x00 15. " MASTER ,Master Indicator" "0,1"
|
|
bitfld.long 0x00 14. " LOST_ARB ,Lost Arbitration Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " BUS_FREE ,PMBus Free Indicator" "0,1"
|
|
bitfld.long 0x00 12. " UNIT_BUSY ,PMBus Busy Indicator" "0,1"
|
|
bitfld.long 0x00 11. " RPT_START ,Repeated Start Flag" "0,1"
|
|
bitfld.long 0x00 10. " SLAVE_ADDR_READY ,Slave Address Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CLK_HIGH_DETECTED ,Clock High Detection Status" "0,1"
|
|
bitfld.long 0x00 8. " CLK_LOW_TIMEOUT ,Clock Low Timeout Status" "0,1"
|
|
bitfld.long 0x00 7. " PEC_VALID ,PEC Valid Indicator" "0,1"
|
|
bitfld.long 0x00 6. " NACK ,Not Acknowledge Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EOM ,End of Message Indicator" "0,1"
|
|
bitfld.long 0x00 4. " DATA_REQUEST ,Data Request Flag" "0,1"
|
|
bitfld.long 0x00 3. " DATA_READY ,Data Ready Flag" "0,1"
|
|
bitfld.long 0x00 0.--2. " RD_BYTE_COUNT ,Number of Data Bytes available in Receive Data Register" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x00006400+0x0A)++0x03
|
|
line.long 0x00 "PMBINTM,PMBUS Interrupt Mask Register"
|
|
bitfld.long 0x00 9. " CLK_HIGH_DETECT ,Clock High Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 8. " LOST_ARB ,Lost Arbitration Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 7. " CONTROL ,Control Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " ALERT ,Alert Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EOM ,End of Message Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 4. " SLAVE_ADDR_READY ,Slave Address Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 3. " DATA_REQUEST ,Data Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 2. " DATA_READY ,Data Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " BUS_LOW_TIMEOUT ,Clock Low Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 0. " BUS_FREE ,Bus Free Interrupt Mask" "0,1"
|
|
group.long (d:0x00006400+0x0C)++0x03
|
|
line.long 0x00 "PMBSC,PMBUS Slave Mode Configuration Register"
|
|
bitfld.long 0x00 21.--22. " RX_BYTE_ACK_CNT ,Number of data bytes to automatically acknowledge" "0,1,2,3"
|
|
bitfld.long 0x00 20. " MAN_CMD ,Manual Command Acknowledgement Mode" "0,1"
|
|
bitfld.long 0x00 19. " TX_PEC ,send a PEC byte at end of message" "0,1"
|
|
bitfld.long 0x00 16.--18. " TX_COUNT ,Number of valid bytes in Transmit Data Register" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " PEC_ENA ,PEC Processing Enable" "0,1"
|
|
bitfld.long 0x00 8.--14. " SLAVE_MASK ,Slave address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 7. " MAN_SLAVE_ACK ,Manual Slave Address Acknowledgement Mode" "0,1"
|
|
bitfld.long 0x00 0.--6. " SLAVE_ADDR ,Configures the current device address of the slave." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x00006400+0x0E)++0x03
|
|
line.long 0x00 "PMBHSA,PMBUS Hold Slave Address Register"
|
|
bitfld.long 0x00 1.--7. " SLAVE_ADDR ,Stored device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0. " SLAVE_RW ,Stored R/W bit" "0,1"
|
|
group.long (d:0x00006400+0x10)++0x03
|
|
line.long 0x00 "PMBCTRL,PMBUS Control Register"
|
|
bitfld.long 0x00 31. " I2CMODE ,Bit to enable I2C mode" "0,1"
|
|
bitfld.long 0x00 23.--27. " CLKDIV ,PMBUS Clock Divide Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 22. " MASTER_EN ,PMBus Master Enable" "0,1"
|
|
bitfld.long 0x00 21. " SLAVE_EN ,PMBus Slave Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. " CLK_LO_DIS ,Clock Low Timeout Disable" "0,1"
|
|
bitfld.long 0x00 19. " IBIAS_B_EN ,PMBus Current Source B Control" "0,1"
|
|
bitfld.long 0x00 18. " IBIAS_A_EN ,PMBus Current Source A Control" "0,1"
|
|
bitfld.long 0x00 17. " SCL_DIR ,Configures direction of PMBus clock pin in GPIO mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " SCL_VALUE ,Configures output value of PMBus clock pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x00 15. " SCL_MODE ,Configures mode of PMBus Clock pin" "0,1"
|
|
bitfld.long 0x00 14. " SDA_DIR ,Configures direction of PMBus data pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 13. " SDA_VALUE ,Configures output value of PMBus data pin in GPIO Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " SDA_MODE ,Configures mode of PMBus Data pin" "0,1"
|
|
bitfld.long 0x00 11. " CNTL_DIR ,Configures direction of Control pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 10. " CNTL_VALUE ,Configures output value of Control pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x00 9. " CNTL_MODE ,Configures mode of Control pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " ALERT_DIR ,Configures direction of Alert pin in GPIO mode" "0,1"
|
|
bitfld.long 0x00 7. " ALERT_VALUE ,Configures output value of Alert pin in GPIO Mode" "0,1"
|
|
bitfld.long 0x00 6. " ALERT_MODE ,Configures mode of Alert pin" "0,1"
|
|
bitfld.long 0x00 5. " CNTL_INT_EDGE ,Control Interrupt Edge Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FAST_MODE ,Fast Mode Enable" "0,1"
|
|
bitfld.long 0x00 2. " BUS_LO_INT_EDGE ,Clock Low Timeout Interrupt Edge Select" "0,1"
|
|
bitfld.long 0x00 1. " ALERT_EN ,Slave Alert Enable" "0,1"
|
|
bitfld.long 0x00 0. " RESET ,PMBus Interface Synchronous Reset" "0,1"
|
|
group.long (d:0x00006400+0x12)++0x03
|
|
line.long 0x00 "PMBTIMCTL,PMBUS Timing Control Register"
|
|
bitfld.long 0x00 0. " TIM_OVERRIDE ,Overide the default settings of the timing parameters." "0,1"
|
|
group.long (d:0x00006400+0x14)++0x03
|
|
line.long 0x00 "PMBTIMCLK,PMBUS Clock Timing Register"
|
|
hexmask.long 0x00 16.--23. 1. "CLK_FREQ,Determines the PMBUS master clock frequency."
|
|
hexmask.long 0x00 0.--7. 1. "CLK_HIGH_LIMIT,Determines the PMBUS master clock high pulse width."
|
|
group.long (d:0x00006400+0x16)++0x03
|
|
line.long 0x00 "PMBTIMSTSETUP,PMBUS Start Setup Time Register"
|
|
hexmask.long 0x00 0.--7. 1. "TSU_STA,Setup time, rise edge of PMBUS master clock to start edge."
|
|
group.long (d:0x00006400+0x18)++0x03
|
|
line.long 0x00 "PMBTIMBIDLE,PMBUS Bus Idle Time Register"
|
|
hexmask.long 0x00 0.--9. 1. "BUSIDLE,Determines the Bus Idle Limit"
|
|
group.long (d:0x00006400+0x1A)++0x03
|
|
line.long 0x00 "PMBTIMLOWTIMOUT,PMBUS Clock Low Timeout Value Register"
|
|
hexmask.long 0x00 0.--19. 1. "CLKLOWTIMOUT,Determines the clock low timeout value"
|
|
group.long (d:0x00006400+0x1C)++0x03
|
|
line.long 0x00 "PMBTIMHIGHTIMOUT,PMBUS Clock High Timeout Value Register"
|
|
hexmask.long 0x00 0.--9. 1. "CLKHIGHTIMOUT,Determines the clock high timeout value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Serial Communications Interface (SCI)"
|
|
tree "SCI A"
|
|
width 10.
|
|
group.word (d:0x00007200+0x0+0x00)++0x01
|
|
line.word 0x00 "SCICCR,Communications control register"
|
|
bitfld.word 0x00 7. " STOPBITS ,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x00 6. " PARITY ,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x00 5. " PARITYENA ,Parity enable" "0,1"
|
|
bitfld.word 0x00 4. " LOOPBKENA ,Loop Back enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " ADDRIDLE_MODE ,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x00 0.--2. " SCICHAR ,Character length control" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007200+0x0+0x01)++0x01
|
|
line.word 0x00 "SCICTL1,Control register 1"
|
|
bitfld.word 0x00 6. " RXERRINTENA ,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SWRESET ,Software reset" "0,1"
|
|
bitfld.word 0x00 3. " TXWAKE ,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x00 2. " SLEEP ,SCI sleep" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TXENA ,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x00 0. " RXENA ,SCI receiver enable" "0,1"
|
|
group.word (d:0x00007200+0x0+0x02)++0x01
|
|
line.word 0x00 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
group.word (d:0x00007200+0x0+0x03)++0x01
|
|
line.word 0x00 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
group.word (d:0x00007200+0x0+0x04)++0x01
|
|
line.word 0x00 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x00 7. " TXRDY ,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x00 6. " TXEMPTY ,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x00 1. " RXBKINTENA ,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x00 0. " TXINTENA ,Transmit __interrupt enable" "0,1"
|
|
rgroup.word (d:0x00007200+0x0+0x05)++0x01
|
|
line.word 0x00 "SCIRXST,Receive status register"
|
|
bitfld.word 0x00 7. " RXERROR ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 6. " RXRDY ,Receiver ready flag" "0,1"
|
|
bitfld.word 0x00 5. " BRKDT ,Break-detect flag" "0,1"
|
|
bitfld.word 0x00 4. " FE ,Framing error flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OE ,Overrun error flag" "0,1"
|
|
bitfld.word 0x00 2. " PE ,Parity error flag" "0,1"
|
|
bitfld.word 0x00 1. " RXWAKE ,Receiver wakeup detect flag" "0,1"
|
|
rgroup.word (d:0x00007200+0x0+0x06)++0x01
|
|
line.word 0x00 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word 0x00 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
rgroup.word (d:0x00007200+0x0+0x07)++0x01
|
|
line.word 0x00 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x00 15. " SCIFFFE ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFPE ,Receiver error flag" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word (d:0x00007200+0x0+0x09)++0x01
|
|
line.word 0x00 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word 0x00 0.--7. 1. "TXDT,Transmit data buffer"
|
|
group.word (d:0x00007200+0x0+0x0A)++0x01
|
|
line.word 0x00 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x00 15. " SCIRST ,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFENA ,Enhancement enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x0+0x0B)++0x01
|
|
line.word 0x00 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,FIFO overflow" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVRCLR ,Clear overflow" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x0+0x0C)++0x01
|
|
line.word 0x00 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x00 15. " ABD ,Auto baud detect" "0,1"
|
|
bitfld.word 0x00 14. " ABDCLR ,Auto baud clear" "0,1"
|
|
bitfld.word 0x00 13. " CDC ,Auto baud mode enable" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word (d:0x00007200+0x0+0x0F)++0x01
|
|
line.word 0x00 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x00 3.--4. " FREESOFT ,Emulation modes" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI B"
|
|
width 10.
|
|
group.word (d:0x00007200+0x10+0x00)++0x01
|
|
line.word 0x00 "SCICCR,Communications control register"
|
|
bitfld.word 0x00 7. " STOPBITS ,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x00 6. " PARITY ,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x00 5. " PARITYENA ,Parity enable" "0,1"
|
|
bitfld.word 0x00 4. " LOOPBKENA ,Loop Back enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " ADDRIDLE_MODE ,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x00 0.--2. " SCICHAR ,Character length control" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007200+0x10+0x01)++0x01
|
|
line.word 0x00 "SCICTL1,Control register 1"
|
|
bitfld.word 0x00 6. " RXERRINTENA ,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SWRESET ,Software reset" "0,1"
|
|
bitfld.word 0x00 3. " TXWAKE ,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x00 2. " SLEEP ,SCI sleep" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TXENA ,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x00 0. " RXENA ,SCI receiver enable" "0,1"
|
|
group.word (d:0x00007200+0x10+0x02)++0x01
|
|
line.word 0x00 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
group.word (d:0x00007200+0x10+0x03)++0x01
|
|
line.word 0x00 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
group.word (d:0x00007200+0x10+0x04)++0x01
|
|
line.word 0x00 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x00 7. " TXRDY ,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x00 6. " TXEMPTY ,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x00 1. " RXBKINTENA ,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x00 0. " TXINTENA ,Transmit __interrupt enable" "0,1"
|
|
rgroup.word (d:0x00007200+0x10+0x05)++0x01
|
|
line.word 0x00 "SCIRXST,Receive status register"
|
|
bitfld.word 0x00 7. " RXERROR ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 6. " RXRDY ,Receiver ready flag" "0,1"
|
|
bitfld.word 0x00 5. " BRKDT ,Break-detect flag" "0,1"
|
|
bitfld.word 0x00 4. " FE ,Framing error flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OE ,Overrun error flag" "0,1"
|
|
bitfld.word 0x00 2. " PE ,Parity error flag" "0,1"
|
|
bitfld.word 0x00 1. " RXWAKE ,Receiver wakeup detect flag" "0,1"
|
|
rgroup.word (d:0x00007200+0x10+0x06)++0x01
|
|
line.word 0x00 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word 0x00 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
rgroup.word (d:0x00007200+0x10+0x07)++0x01
|
|
line.word 0x00 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x00 15. " SCIFFFE ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFPE ,Receiver error flag" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word (d:0x00007200+0x10+0x09)++0x01
|
|
line.word 0x00 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word 0x00 0.--7. 1. "TXDT,Transmit data buffer"
|
|
group.word (d:0x00007200+0x10+0x0A)++0x01
|
|
line.word 0x00 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x00 15. " SCIRST ,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFENA ,Enhancement enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x10+0x0B)++0x01
|
|
line.word 0x00 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,FIFO overflow" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVRCLR ,Clear overflow" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x10+0x0C)++0x01
|
|
line.word 0x00 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x00 15. " ABD ,Auto baud detect" "0,1"
|
|
bitfld.word 0x00 14. " ABDCLR ,Auto baud clear" "0,1"
|
|
bitfld.word 0x00 13. " CDC ,Auto baud mode enable" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word (d:0x00007200+0x10+0x0F)++0x01
|
|
line.word 0x00 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x00 3.--4. " FREESOFT ,Emulation modes" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI C"
|
|
width 10.
|
|
group.word (d:0x00007200+0x20+0x00)++0x01
|
|
line.word 0x00 "SCICCR,Communications control register"
|
|
bitfld.word 0x00 7. " STOPBITS ,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x00 6. " PARITY ,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x00 5. " PARITYENA ,Parity enable" "0,1"
|
|
bitfld.word 0x00 4. " LOOPBKENA ,Loop Back enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " ADDRIDLE_MODE ,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x00 0.--2. " SCICHAR ,Character length control" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007200+0x20+0x01)++0x01
|
|
line.word 0x00 "SCICTL1,Control register 1"
|
|
bitfld.word 0x00 6. " RXERRINTENA ,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SWRESET ,Software reset" "0,1"
|
|
bitfld.word 0x00 3. " TXWAKE ,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x00 2. " SLEEP ,SCI sleep" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TXENA ,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x00 0. " RXENA ,SCI receiver enable" "0,1"
|
|
group.word (d:0x00007200+0x20+0x02)++0x01
|
|
line.word 0x00 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
group.word (d:0x00007200+0x20+0x03)++0x01
|
|
line.word 0x00 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
group.word (d:0x00007200+0x20+0x04)++0x01
|
|
line.word 0x00 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x00 7. " TXRDY ,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x00 6. " TXEMPTY ,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x00 1. " RXBKINTENA ,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x00 0. " TXINTENA ,Transmit __interrupt enable" "0,1"
|
|
rgroup.word (d:0x00007200+0x20+0x05)++0x01
|
|
line.word 0x00 "SCIRXST,Receive status register"
|
|
bitfld.word 0x00 7. " RXERROR ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 6. " RXRDY ,Receiver ready flag" "0,1"
|
|
bitfld.word 0x00 5. " BRKDT ,Break-detect flag" "0,1"
|
|
bitfld.word 0x00 4. " FE ,Framing error flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OE ,Overrun error flag" "0,1"
|
|
bitfld.word 0x00 2. " PE ,Parity error flag" "0,1"
|
|
bitfld.word 0x00 1. " RXWAKE ,Receiver wakeup detect flag" "0,1"
|
|
rgroup.word (d:0x00007200+0x20+0x06)++0x01
|
|
line.word 0x00 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word 0x00 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
rgroup.word (d:0x00007200+0x20+0x07)++0x01
|
|
line.word 0x00 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x00 15. " SCIFFFE ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFPE ,Receiver error flag" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word (d:0x00007200+0x20+0x09)++0x01
|
|
line.word 0x00 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word 0x00 0.--7. 1. "TXDT,Transmit data buffer"
|
|
group.word (d:0x00007200+0x20+0x0A)++0x01
|
|
line.word 0x00 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x00 15. " SCIRST ,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFENA ,Enhancement enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x20+0x0B)++0x01
|
|
line.word 0x00 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,FIFO overflow" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVRCLR ,Clear overflow" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x20+0x0C)++0x01
|
|
line.word 0x00 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x00 15. " ABD ,Auto baud detect" "0,1"
|
|
bitfld.word 0x00 14. " ABDCLR ,Auto baud clear" "0,1"
|
|
bitfld.word 0x00 13. " CDC ,Auto baud mode enable" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word (d:0x00007200+0x20+0x0F)++0x01
|
|
line.word 0x00 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x00 3.--4. " FREESOFT ,Emulation modes" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI D"
|
|
width 10.
|
|
group.word (d:0x00007200+0x30+0x00)++0x01
|
|
line.word 0x00 "SCICCR,Communications control register"
|
|
bitfld.word 0x00 7. " STOPBITS ,Number of Stop Bits" "0,1"
|
|
bitfld.word 0x00 6. " PARITY ,Even or Odd Parity" "0,1"
|
|
bitfld.word 0x00 5. " PARITYENA ,Parity enable" "0,1"
|
|
bitfld.word 0x00 4. " LOOPBKENA ,Loop Back enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " ADDRIDLE_MODE ,ADDR/IDLE Mode control" "0,1"
|
|
bitfld.word 0x00 0.--2. " SCICHAR ,Character length control" "0,1,2,3,4,5,6,7"
|
|
group.word (d:0x00007200+0x30+0x01)++0x01
|
|
line.word 0x00 "SCICTL1,Control register 1"
|
|
bitfld.word 0x00 6. " RXERRINTENA ,Receive error interrupt enable" "0,1"
|
|
bitfld.word 0x00 5. " SWRESET ,Software reset" "0,1"
|
|
bitfld.word 0x00 3. " TXWAKE ,Transmitter wakeup method" "0,1"
|
|
bitfld.word 0x00 2. " SLEEP ,SCI sleep" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " TXENA ,SCI transmitter enable" "0,1"
|
|
bitfld.word 0x00 0. " RXENA ,SCI receiver enable" "0,1"
|
|
group.word (d:0x00007200+0x30+0x02)++0x01
|
|
line.word 0x00 "SCIHBAUD,Baud rate (high) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCIHBAUD"
|
|
group.word (d:0x00007200+0x30+0x03)++0x01
|
|
line.word 0x00 "SCILBAUD,Baud rate (low) register"
|
|
hexmask.word 0x00 0.--7. 1. "BAUD,SCI 16-bit baud selection Registers SCILBAUD"
|
|
group.word (d:0x00007200+0x30+0x04)++0x01
|
|
line.word 0x00 "SCICTL2,Control register 2"
|
|
rbitfld.word 0x00 7. " TXRDY ,Transmitter ready flag" "0,1"
|
|
rbitfld.word 0x00 6. " TXEMPTY ,Transmitter empty flag" "0,1"
|
|
bitfld.word 0x00 1. " RXBKINTENA ,Receiver-buffer break enable" "0,1"
|
|
bitfld.word 0x00 0. " TXINTENA ,Transmit __interrupt enable" "0,1"
|
|
rgroup.word (d:0x00007200+0x30+0x05)++0x01
|
|
line.word 0x00 "SCIRXST,Receive status register"
|
|
bitfld.word 0x00 7. " RXERROR ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 6. " RXRDY ,Receiver ready flag" "0,1"
|
|
bitfld.word 0x00 5. " BRKDT ,Break-detect flag" "0,1"
|
|
bitfld.word 0x00 4. " FE ,Framing error flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " OE ,Overrun error flag" "0,1"
|
|
bitfld.word 0x00 2. " PE ,Parity error flag" "0,1"
|
|
bitfld.word 0x00 1. " RXWAKE ,Receiver wakeup detect flag" "0,1"
|
|
rgroup.word (d:0x00007200+0x30+0x06)++0x01
|
|
line.word 0x00 "SCIRXEMU,Receive emulation buffer register"
|
|
hexmask.word 0x00 0.--7. 1. "ERXDT,Receive emulation buffer data"
|
|
rgroup.word (d:0x00007200+0x30+0x07)++0x01
|
|
line.word 0x00 "SCIRXBUF,Receive data buffer"
|
|
bitfld.word 0x00 15. " SCIFFFE ,Receiver error flag" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFPE ,Receiver error flag" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "SAR,Receive Character bits"
|
|
group.word (d:0x00007200+0x30+0x09)++0x01
|
|
line.word 0x00 "SCITXBUF,Transmit data buffer"
|
|
hexmask.word 0x00 0.--7. 1. "TXDT,Transmit data buffer"
|
|
group.word (d:0x00007200+0x30+0x0A)++0x01
|
|
line.word 0x00 "SCIFFTX,FIFO transmit register"
|
|
bitfld.word 0x00 15. " SCIRST ,SCI reset rx/tx channels" "0,1"
|
|
bitfld.word 0x00 14. " SCIFFENA ,Enhancement enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x30+0x0B)++0x01
|
|
line.word 0x00 "SCIFFRX,FIFO receive register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,FIFO overflow" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVRCLR ,Clear overflow" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,FIFO reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,FIFO status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,INT flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,Clear INT flag" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,Interrupt enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,Interrupt level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00007200+0x30+0x0C)++0x01
|
|
line.word 0x00 "SCIFFCT,FIFO control register"
|
|
rbitfld.word 0x00 15. " ABD ,Auto baud detect" "0,1"
|
|
bitfld.word 0x00 14. " ABDCLR ,Auto baud clear" "0,1"
|
|
bitfld.word 0x00 13. " CDC ,Auto baud mode enable" "0,1"
|
|
hexmask.word 0x00 0.--7. 1. "FFTXDLY,FIFO transmit delay"
|
|
group.word (d:0x00007200+0x30+0x0F)++0x01
|
|
line.word 0x00 "SCIPRI,SCI priority control"
|
|
bitfld.word 0x00 3.--4. " FREESOFT ,Emulation modes" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Sigma Delta Filter Module (SDFM)"
|
|
tree "SDFM 1"
|
|
width 22.
|
|
rgroup.long (d:0x00005E00+0x00)++0x03
|
|
line.long 0x00 "SDIFLG,SD Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " MIF ,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 23. " SDFFINT4 ,SDFIFO interrupt for Ch4" "0,1"
|
|
bitfld.long 0x00 22. " SDFFINT3 ,SDFIFO interrupt for Ch3" "0,1"
|
|
bitfld.long 0x00 21. " SDFFINT2 ,SDFIFO interrupt for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. " SDFFINT1 ,SDFIFO interrupt for Ch1" "0,1"
|
|
bitfld.long 0x00 19. " SDFFOVF4 ,FIFO Overflow Flag for Ch4" "0,1"
|
|
bitfld.long 0x00 18. " SDFFOVF3 ,FIFO Overflow Flag for Ch3" "0,1"
|
|
bitfld.long 0x00 17. " SDFFOVF2 ,FIFO Overflow Flag for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " SDFFOVF1 ,FIFO Overflow Flag for Ch1." "0,1"
|
|
bitfld.long 0x00 15. " AF4 ,Acknowledge flag for Filter 4" "0,1"
|
|
bitfld.long 0x00 14. " AF3 ,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x00 13. " AF2 ,Acknowledge flag for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " AF1 ,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x00 11. " MF4 ,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x00 10. " MF3 ,Modulator Failure for Filter 3" "0,1"
|
|
bitfld.long 0x00 9. " MF2 ,Modulator Failure for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " MF1 ,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x00 7. " FLT4_FLG_CEVT2 ,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 6. " FLT4_FLG_CEVT1 ,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 5. " FLT3_FLG_CEVT2 ,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " FLT3_FLG_CEVT1 ,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x00 3. " FLT2_FLG_CEVT2 ,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 2. " FLT2_FLG_CEVT1 ,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 1. " FLT1_FLG_CEVT2 ,Low-level Interrupt flag for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " FLT1_FLG_CEVT1 ,High-level Interrupt flag for Ch1" "0,1"
|
|
group.long (d:0x00005E00+0x02)++0x03
|
|
line.long 0x00 "SDIFLGCLR,SD Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 31. " MIF ,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 23. " SDFFINT4 ,SDFIFO Interrupt flag-clear bit for Ch4" "0,1"
|
|
bitfld.long 0x00 22. " SDFFINT3 ,SDFIFO Interrupt flag-clear bit for Ch3" "0,1"
|
|
bitfld.long 0x00 21. " SDFFINT2 ,SDFIFO Interrupt flag-clear bit for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. " SDFFINT1 ,SDFIFO Interrupt flag-clear bit for Ch1" "0,1"
|
|
bitfld.long 0x00 19. " SDFFOVF4 ,SDFIFO overflow clear Ch4" "0,1"
|
|
bitfld.long 0x00 18. " SDFFOVF3 ,SDFIFO overflow clear Ch3" "0,1"
|
|
bitfld.long 0x00 17. " SDFFOVF2 ,SDFIFO overflow clear Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " SDFFOVF1 ,SDFIFO overflow clear Ch1" "0,1"
|
|
bitfld.long 0x00 15. " AF4 ,Acknowledge flag for Filter 4" "0,1"
|
|
bitfld.long 0x00 14. " AF3 ,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x00 13. " AF2 ,Acknowledge flag for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " AF1 ,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x00 11. " MF4 ,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x00 10. " MF3 ,Modulator Failure for Filter 3" "0,1"
|
|
bitfld.long 0x00 9. " MF2 ,Modulator Failure for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " MF1 ,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x00 7. " FLT4_FLG_CEVT2 ,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 6. " FLT4_FLG_CEVT1 ,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 5. " FLT3_FLG_CEVT2 ,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " FLT3_FLG_CEVT1 ,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x00 3. " FLT2_FLG_CEVT2 ,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 2. " FLT2_FLG_CEVT1 ,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 1. " FLT1_FLG_CEVT2 ,Low-level Interrupt flag for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " FLT1_FLG_CEVT1 ,High-level Interrupt flag for Ch1" "0,1"
|
|
group.word (d:0x00005E00+0x04)++0x01
|
|
line.word 0x00 "SDCTL,SD Control Register"
|
|
bitfld.word 0x00 13. " MIE ,Master SDy_ERR Interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " HZ4 ,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x00 2. " HZ3 ,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x00 1. " HZ2 ,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " HZ1 ,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word (d:0x00005E00+0x06)++0x01
|
|
line.word 0x00 "SDMFILEN,SD Master Filter Enable"
|
|
bitfld.word 0x00 11. " MFE ,Master Filter Enable." "0,1"
|
|
rgroup.word (d:0x00005E00+0x07)++0x01
|
|
line.word 0x00 "SDSTATUS,SD Status Register"
|
|
bitfld.word 0x00 15. " MAL4 ,Manchester locked status for filter module 4." "0,1"
|
|
bitfld.word 0x00 14. " MAL3 ,Manchester locked status for filter module 3." "0,1"
|
|
bitfld.word 0x00 13. " MAL2 ,Manchester locked status for filter module 2." "0,1"
|
|
bitfld.word 0x00 12. " MAL1 ,Manchester locked status for filter module 1." "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " MS4 ,Manchester clock decode phase complete for filter module 4." "0,1"
|
|
bitfld.word 0x00 10. " MS3 ,Manchester clock decode phase complete for filter module 3." "0,1"
|
|
bitfld.word 0x00 9. " MS2 ,Manchester clock decode phase complete for filter module 2." "0,1"
|
|
bitfld.word 0x00 8. " MS1 ,Manchester clock decode phase complete for filter module 1." "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HZ4 ,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x00 2. " HZ3 ,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x00 1. " HZ2 ,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x00 0. " HZ1 ,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word (d:0x00005E00+0x10)++0x01
|
|
line.word 0x00 "SDCTLPARM1,Control Parameter Register for Ch1"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD1 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x11)++0x01
|
|
line.word 0x00 "SDDFPARM1,Data Filter Parameter Register for Ch1"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E00+0x12)++0x01
|
|
line.word 0x00 "SDDPARM1,Data Parameter Register for Ch1"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E00+0x13)++0x01
|
|
line.word 0x00 "SDFLT1CMPH1,High-level Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x14)++0x01
|
|
line.word 0x00 "SDFLT1CMPL1,Low-level Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x15)++0x01
|
|
line.word 0x00 "SDCPARM1,Comparator Filter Parameter Register for Ch1"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E00+0x16)++0x03
|
|
line.long 0x00 "SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E00+0x18)++0x03
|
|
line.long 0x00 "SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E00+0x1A)++0x01
|
|
line.word 0x00 "SDCDATA1,Comparator Filter Data Register (16b) for Ch1"
|
|
group.word (d:0x00005E00+0x1B)++0x01
|
|
line.word 0x00 "SDFLT1CMPH2,Second high level threhold for CH1"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E00+0x1C)++0x01
|
|
line.word 0x00 "SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E00+0x1D)++0x01
|
|
line.word 0x00 "SDFIFOCTL1,FIFO Control Register for Ch1"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x1E)++0x01
|
|
line.word 0x00 "SDSYNC1,SD Filter Sync control for Ch1"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E00+0x1F)++0x01
|
|
line.word 0x00 "SDFLT1CMPL2,Second low level threhold for CH1"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E00+0x20)++0x01
|
|
line.word 0x00 "SDCTLPARM2,Control Parameter Register for Ch2"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD2 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x21)++0x01
|
|
line.word 0x00 "SDDFPARM2,Data Filter Parameter Register for Ch2"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E00+0x22)++0x01
|
|
line.word 0x00 "SDDPARM2,Data Parameter Register for Ch2"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E00+0x23)++0x01
|
|
line.word 0x00 "SDFLT2CMPH1,High-level Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x24)++0x01
|
|
line.word 0x00 "SDFLT2CMPL1,Low-level Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x25)++0x01
|
|
line.word 0x00 "SDCPARM2,Comparator Filter Parameter Register for Ch2"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E00+0x26)++0x03
|
|
line.long 0x00 "SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E00+0x28)++0x03
|
|
line.long 0x00 "SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E00+0x2A)++0x01
|
|
line.word 0x00 "SDCDATA2,Comparator Filter Data Register (16b) for Ch2"
|
|
group.word (d:0x00005E00+0x2B)++0x01
|
|
line.word 0x00 "SDFLT2CMPH2,Second high level threhold for CH2"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E00+0x2C)++0x01
|
|
line.word 0x00 "SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E00+0x2D)++0x01
|
|
line.word 0x00 "SDFIFOCTL2,FIFO Control Register for Ch2"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x2E)++0x01
|
|
line.word 0x00 "SDSYNC2,SD Filter Sync control for Ch2"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E00+0x2F)++0x01
|
|
line.word 0x00 "SDFLT2CMPL2,Second low level threhold for CH2"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E00+0x30)++0x01
|
|
line.word 0x00 "SDCTLPARM3,Control Parameter Register for Ch3"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD3 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x31)++0x01
|
|
line.word 0x00 "SDDFPARM3,Data Filter Parameter Register for Ch3"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E00+0x32)++0x01
|
|
line.word 0x00 "SDDPARM3,Data Parameter Register for Ch3"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E00+0x33)++0x01
|
|
line.word 0x00 "SDFLT3CMPH1,High-level Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x34)++0x01
|
|
line.word 0x00 "SDFLT3CMPL1,Low-level Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x35)++0x01
|
|
line.word 0x00 "SDCPARM3,Comparator Filter Parameter Register for Ch3"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E00+0x36)++0x03
|
|
line.long 0x00 "SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E00+0x38)++0x03
|
|
line.long 0x00 "SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E00+0x3A)++0x01
|
|
line.word 0x00 "SDCDATA3,Comparator Filter Data Register (16b) for Ch3"
|
|
group.word (d:0x00005E00+0x3B)++0x01
|
|
line.word 0x00 "SDFLT3CMPH2,Second high level threhold for CH3"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E00+0x3C)++0x01
|
|
line.word 0x00 "SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E00+0x3D)++0x01
|
|
line.word 0x00 "SDFIFOCTL3,FIFO Control Register for Ch3"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x3E)++0x01
|
|
line.word 0x00 "SDSYNC3,SD Filter Sync control for Ch3"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E00+0x3F)++0x01
|
|
line.word 0x00 "SDFLT3CMPL2,Second low level threhold for CH3"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E00+0x40)++0x01
|
|
line.word 0x00 "SDCTLPARM4,Control Parameter Register for Ch4"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD4 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x41)++0x01
|
|
line.word 0x00 "SDDFPARM4,Data Filter Parameter Register for Ch4"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E00+0x42)++0x01
|
|
line.word 0x00 "SDDPARM4,Data Parameter Register for Ch4"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E00+0x43)++0x01
|
|
line.word 0x00 "SDFLT4CMPH1,High-level Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x44)++0x01
|
|
line.word 0x00 "SDFLT4CMPL1,Low-level Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E00+0x45)++0x01
|
|
line.word 0x00 "SDCPARM4,Comparator Filter Parameter Register for Ch4"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E00+0x46)++0x03
|
|
line.long 0x00 "SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E00+0x48)++0x03
|
|
line.long 0x00 "SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E00+0x4A)++0x01
|
|
line.word 0x00 "SDCDATA4,Comparator Filter Data Register (16b) for Ch4"
|
|
group.word (d:0x00005E00+0x4B)++0x01
|
|
line.word 0x00 "SDFLT4CMPH2,Second high level threhold for CH4"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E00+0x4C)++0x01
|
|
line.word 0x00 "SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E00+0x4D)++0x01
|
|
line.word 0x00 "SDFIFOCTL4,FIFO Control Register for Ch4"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x4E)++0x01
|
|
line.word 0x00 "SDSYNC4,SD Filter Sync control for Ch4"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E00+0x4F)++0x01
|
|
line.word 0x00 "SDFLT4CMPL2,Second low level threhold for CH4"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E00+0x60)++0x01
|
|
line.word 0x00 "SDCOMP1CTL,SD Comparator event filter1 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x61)++0x01
|
|
line.word 0x00 "SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x62)++0x01
|
|
line.word 0x00 "SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x63)++0x01
|
|
line.word 0x00 "SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x64)++0x01
|
|
line.word 0x00 "SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x67)++0x01
|
|
line.word 0x00 "SDCOMP1LOCK,SD compartor event filter1 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP1CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E00+0x68)++0x01
|
|
line.word 0x00 "SDCOMP2CTL,SD Comparator event filter2 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x69)++0x01
|
|
line.word 0x00 "SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x6A)++0x01
|
|
line.word 0x00 "SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x6B)++0x01
|
|
line.word 0x00 "SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x6C)++0x01
|
|
line.word 0x00 "SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x6F)++0x01
|
|
line.word 0x00 "SDCOMP2LOCK,SD compartor event filter2 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP2CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E00+0x70)++0x01
|
|
line.word 0x00 "SDCOMP3CTL,SD Comparator event filter3 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x71)++0x01
|
|
line.word 0x00 "SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x72)++0x01
|
|
line.word 0x00 "SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x73)++0x01
|
|
line.word 0x00 "SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x74)++0x01
|
|
line.word 0x00 "SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x77)++0x01
|
|
line.word 0x00 "SDCOMP3LOCK,SD compartor event filter3 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP3CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E00+0x78)++0x01
|
|
line.word 0x00 "SDCOMP4CTL,SD Comparator event filter4 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E00+0x79)++0x01
|
|
line.word 0x00 "SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x7A)++0x01
|
|
line.word 0x00 "SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x7B)++0x01
|
|
line.word 0x00 "SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E00+0x7C)++0x01
|
|
line.word 0x00 "SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E00+0x7F)++0x01
|
|
line.word 0x00 "SDCOMP4LOCK,SD compartor event filter4 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP4CTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDFM 2"
|
|
width 22.
|
|
rgroup.long (d:0x00005E80+0x00)++0x03
|
|
line.long 0x00 "SDIFLG,SD Interrupt Flag Register"
|
|
bitfld.long 0x00 31. " MIF ,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 23. " SDFFINT4 ,SDFIFO interrupt for Ch4" "0,1"
|
|
bitfld.long 0x00 22. " SDFFINT3 ,SDFIFO interrupt for Ch3" "0,1"
|
|
bitfld.long 0x00 21. " SDFFINT2 ,SDFIFO interrupt for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. " SDFFINT1 ,SDFIFO interrupt for Ch1" "0,1"
|
|
bitfld.long 0x00 19. " SDFFOVF4 ,FIFO Overflow Flag for Ch4" "0,1"
|
|
bitfld.long 0x00 18. " SDFFOVF3 ,FIFO Overflow Flag for Ch3" "0,1"
|
|
bitfld.long 0x00 17. " SDFFOVF2 ,FIFO Overflow Flag for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " SDFFOVF1 ,FIFO Overflow Flag for Ch1." "0,1"
|
|
bitfld.long 0x00 15. " AF4 ,Acknowledge flag for Filter 4" "0,1"
|
|
bitfld.long 0x00 14. " AF3 ,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x00 13. " AF2 ,Acknowledge flag for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " AF1 ,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x00 11. " MF4 ,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x00 10. " MF3 ,Modulator Failure for Filter 3" "0,1"
|
|
bitfld.long 0x00 9. " MF2 ,Modulator Failure for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " MF1 ,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x00 7. " FLT4_FLG_CEVT2 ,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 6. " FLT4_FLG_CEVT1 ,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 5. " FLT3_FLG_CEVT2 ,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " FLT3_FLG_CEVT1 ,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x00 3. " FLT2_FLG_CEVT2 ,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 2. " FLT2_FLG_CEVT1 ,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 1. " FLT1_FLG_CEVT2 ,Low-level Interrupt flag for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " FLT1_FLG_CEVT1 ,High-level Interrupt flag for Ch1" "0,1"
|
|
group.long (d:0x00005E80+0x02)++0x03
|
|
line.long 0x00 "SDIFLGCLR,SD Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 31. " MIF ,Master Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 23. " SDFFINT4 ,SDFIFO Interrupt flag-clear bit for Ch4" "0,1"
|
|
bitfld.long 0x00 22. " SDFFINT3 ,SDFIFO Interrupt flag-clear bit for Ch3" "0,1"
|
|
bitfld.long 0x00 21. " SDFFINT2 ,SDFIFO Interrupt flag-clear bit for Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. " SDFFINT1 ,SDFIFO Interrupt flag-clear bit for Ch1" "0,1"
|
|
bitfld.long 0x00 19. " SDFFOVF4 ,SDFIFO overflow clear Ch4" "0,1"
|
|
bitfld.long 0x00 18. " SDFFOVF3 ,SDFIFO overflow clear Ch3" "0,1"
|
|
bitfld.long 0x00 17. " SDFFOVF2 ,SDFIFO overflow clear Ch2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " SDFFOVF1 ,SDFIFO overflow clear Ch1" "0,1"
|
|
bitfld.long 0x00 15. " AF4 ,Acknowledge flag for Filter 4" "0,1"
|
|
bitfld.long 0x00 14. " AF3 ,Acknowledge flag for Filter 3" "0,1"
|
|
bitfld.long 0x00 13. " AF2 ,Acknowledge flag for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " AF1 ,Acknowledge flag for Filter 1" "0,1"
|
|
bitfld.long 0x00 11. " MF4 ,Modulator Failure for Filter 4" "0,1"
|
|
bitfld.long 0x00 10. " MF3 ,Modulator Failure for Filter 3" "0,1"
|
|
bitfld.long 0x00 9. " MF2 ,Modulator Failure for Filter 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " MF1 ,Modulator Failure for Filter 1" "0,1"
|
|
bitfld.long 0x00 7. " FLT4_FLG_CEVT2 ,Low-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 6. " FLT4_FLG_CEVT1 ,High-level Interrupt flag for Ch4" "0,1"
|
|
bitfld.long 0x00 5. " FLT3_FLG_CEVT2 ,Low-level Interrupt flag for Ch3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " FLT3_FLG_CEVT1 ,High-level Interrupt flag for Ch3" "0,1"
|
|
bitfld.long 0x00 3. " FLT2_FLG_CEVT2 ,Low-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 2. " FLT2_FLG_CEVT1 ,High-level Interrupt flag for Ch2" "0,1"
|
|
bitfld.long 0x00 1. " FLT1_FLG_CEVT2 ,Low-level Interrupt flag for Ch1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " FLT1_FLG_CEVT1 ,High-level Interrupt flag for Ch1" "0,1"
|
|
group.word (d:0x00005E80+0x04)++0x01
|
|
line.word 0x00 "SDCTL,SD Control Register"
|
|
bitfld.word 0x00 13. " MIE ,Master SDy_ERR Interrupt enable" "0,1"
|
|
bitfld.word 0x00 3. " HZ4 ,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x00 2. " HZ3 ,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x00 1. " HZ2 ,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " HZ1 ,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word (d:0x00005E80+0x06)++0x01
|
|
line.word 0x00 "SDMFILEN,SD Master Filter Enable"
|
|
bitfld.word 0x00 11. " MFE ,Master Filter Enable." "0,1"
|
|
rgroup.word (d:0x00005E80+0x07)++0x01
|
|
line.word 0x00 "SDSTATUS,SD Status Register"
|
|
bitfld.word 0x00 15. " MAL4 ,Manchester locked status for filter module 4." "0,1"
|
|
bitfld.word 0x00 14. " MAL3 ,Manchester locked status for filter module 3." "0,1"
|
|
bitfld.word 0x00 13. " MAL2 ,Manchester locked status for filter module 2." "0,1"
|
|
bitfld.word 0x00 12. " MAL1 ,Manchester locked status for filter module 1." "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. " MS4 ,Manchester clock decode phase complete for filter module 4." "0,1"
|
|
bitfld.word 0x00 10. " MS3 ,Manchester clock decode phase complete for filter module 3." "0,1"
|
|
bitfld.word 0x00 9. " MS2 ,Manchester clock decode phase complete for filter module 2." "0,1"
|
|
bitfld.word 0x00 8. " MS1 ,Manchester clock decode phase complete for filter module 1." "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. " HZ4 ,High-level Threshold crossing (Z) flag Ch4" "0,1"
|
|
bitfld.word 0x00 2. " HZ3 ,High-level Threshold crossing (Z) flag Ch3" "0,1"
|
|
bitfld.word 0x00 1. " HZ2 ,High-level Threshold crossing (Z) flag Ch2" "0,1"
|
|
bitfld.word 0x00 0. " HZ1 ,High-level Threshold crossing (Z) flag Ch1" "0,1"
|
|
group.word (d:0x00005E80+0x10)++0x01
|
|
line.word 0x00 "SDCTLPARM1,Control Parameter Register for Ch1"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD1 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x11)++0x01
|
|
line.word 0x00 "SDDFPARM1,Data Filter Parameter Register for Ch1"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E80+0x12)++0x01
|
|
line.word 0x00 "SDDPARM1,Data Parameter Register for Ch1"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E80+0x13)++0x01
|
|
line.word 0x00 "SDFLT1CMPH1,High-level Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x14)++0x01
|
|
line.word 0x00 "SDFLT1CMPL1,Low-level Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x15)++0x01
|
|
line.word 0x00 "SDCPARM1,Comparator Filter Parameter Register for Ch1"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E80+0x16)++0x03
|
|
line.long 0x00 "SDDATA1,Data Filter Data Register (16 or 32bit) for Ch1"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E80+0x18)++0x03
|
|
line.long 0x00 "SDDATFIFO1,Filter Data FIFO Output(32b) for Ch1"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E80+0x1A)++0x01
|
|
line.word 0x00 "SDCDATA1,Comparator Filter Data Register (16b) for Ch1"
|
|
group.word (d:0x00005E80+0x1B)++0x01
|
|
line.word 0x00 "SDFLT1CMPH2,Second high level threhold for CH1"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E80+0x1C)++0x01
|
|
line.word 0x00 "SDFLT1CMPHZ,High-level (Z) Threshold Register for Ch1"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E80+0x1D)++0x01
|
|
line.word 0x00 "SDFIFOCTL1,FIFO Control Register for Ch1"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x1E)++0x01
|
|
line.word 0x00 "SDSYNC1,SD Filter Sync control for Ch1"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E80+0x1F)++0x01
|
|
line.word 0x00 "SDFLT1CMPL2,Second low level threhold for CH1"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E80+0x20)++0x01
|
|
line.word 0x00 "SDCTLPARM2,Control Parameter Register for Ch2"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD2 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x21)++0x01
|
|
line.word 0x00 "SDDFPARM2,Data Filter Parameter Register for Ch2"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E80+0x22)++0x01
|
|
line.word 0x00 "SDDPARM2,Data Parameter Register for Ch2"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E80+0x23)++0x01
|
|
line.word 0x00 "SDFLT2CMPH1,High-level Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x24)++0x01
|
|
line.word 0x00 "SDFLT2CMPL1,Low-level Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x25)++0x01
|
|
line.word 0x00 "SDCPARM2,Comparator Filter Parameter Register for Ch2"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E80+0x26)++0x03
|
|
line.long 0x00 "SDDATA2,Data Filter Data Register (16 or 32bit) for Ch2"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E80+0x28)++0x03
|
|
line.long 0x00 "SDDATFIFO2,Filter Data FIFO Output(32b) for Ch2"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E80+0x2A)++0x01
|
|
line.word 0x00 "SDCDATA2,Comparator Filter Data Register (16b) for Ch2"
|
|
group.word (d:0x00005E80+0x2B)++0x01
|
|
line.word 0x00 "SDFLT2CMPH2,Second high level threhold for CH2"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E80+0x2C)++0x01
|
|
line.word 0x00 "SDFLT2CMPHZ,High-level (Z) Threshold Register for Ch2"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E80+0x2D)++0x01
|
|
line.word 0x00 "SDFIFOCTL2,FIFO Control Register for Ch2"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x2E)++0x01
|
|
line.word 0x00 "SDSYNC2,SD Filter Sync control for Ch2"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E80+0x2F)++0x01
|
|
line.word 0x00 "SDFLT2CMPL2,Second low level threhold for CH2"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E80+0x30)++0x01
|
|
line.word 0x00 "SDCTLPARM3,Control Parameter Register for Ch3"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD3 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x31)++0x01
|
|
line.word 0x00 "SDDFPARM3,Data Filter Parameter Register for Ch3"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E80+0x32)++0x01
|
|
line.word 0x00 "SDDPARM3,Data Parameter Register for Ch3"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E80+0x33)++0x01
|
|
line.word 0x00 "SDFLT3CMPH1,High-level Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x34)++0x01
|
|
line.word 0x00 "SDFLT3CMPL1,Low-level Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x35)++0x01
|
|
line.word 0x00 "SDCPARM3,Comparator Filter Parameter Register for Ch3"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E80+0x36)++0x03
|
|
line.long 0x00 "SDDATA3,Data Filter Data Register (16 or 32bit) for Ch3"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E80+0x38)++0x03
|
|
line.long 0x00 "SDDATFIFO3,Filter Data FIFO Output(32b) for Ch3"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E80+0x3A)++0x01
|
|
line.word 0x00 "SDCDATA3,Comparator Filter Data Register (16b) for Ch3"
|
|
group.word (d:0x00005E80+0x3B)++0x01
|
|
line.word 0x00 "SDFLT3CMPH2,Second high level threhold for CH3"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E80+0x3C)++0x01
|
|
line.word 0x00 "SDFLT3CMPHZ,High-level (Z) Threshold Register for Ch3"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E80+0x3D)++0x01
|
|
line.word 0x00 "SDFIFOCTL3,FIFO Control Register for Ch3"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x3E)++0x01
|
|
line.word 0x00 "SDSYNC3,SD Filter Sync control for Ch3"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E80+0x3F)++0x01
|
|
line.word 0x00 "SDFLT3CMPL2,Second low level threhold for CH3"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E80+0x40)++0x01
|
|
line.word 0x00 "SDCTLPARM4,Control Parameter Register for Ch4"
|
|
hexmask.word 0x00 8.--15. 1. "MSCLKPRD,Manchester Clock Period"
|
|
bitfld.word 0x00 6. " SDDATASYNC ,Enable Synchronizer on SD data" "0,1"
|
|
bitfld.word 0x00 4. " SDCLKSYNC ,Enable Synchronizer on SD clock" "0,1"
|
|
bitfld.word 0x00 3. " SDCLKSEL ,SD4 Clock source select." "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. " PLLCLKSEL ,PLL clock select" "0,1"
|
|
bitfld.word 0x00 0.--1. " MOD ,Modulator clocking modes" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x41)++0x01
|
|
line.word 0x00 "SDDFPARM4,Data Filter Parameter Register for Ch4"
|
|
bitfld.word 0x00 12. " SDSYNCEN ,Data Filter Reset Enable" "0,1"
|
|
bitfld.word 0x00 10.--11. " SST ,Data filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 9. " AE ,Ack Enable" "0,1"
|
|
bitfld.word 0x00 8. " FEN ,Filter Enable" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--7. 1. "DOSR,Data Filter Oversample Ratio= DOSR+1"
|
|
group.word (d:0x00005E80+0x42)++0x01
|
|
line.word 0x00 "SDDPARM4,Data Parameter Register for Ch4"
|
|
bitfld.word 0x00 11.--15. " SH ,Shift Control (# bits to shift in 16b mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 10. " DR ,Data Representation (0/1 = 16/32b 2's complement)" "0,1"
|
|
group.word (d:0x00005E80+0x43)++0x01
|
|
line.word 0x00 "SDFLT4CMPH1,High-level Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "HLT,High-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x44)++0x01
|
|
line.word 0x00 "SDFLT4CMPL1,Low-level Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "LLT,Low-level threshold for the comparator filter output"
|
|
group.word (d:0x00005E80+0x45)++0x01
|
|
line.word 0x00 "SDCPARM4,Comparator Filter Parameter Register for Ch4"
|
|
bitfld.word 0x00 14.--15. " CEVT2SEL ,Comparator Event2 select" "0,1,2,3"
|
|
bitfld.word 0x00 13. " CEN ,Comparator Enable" "0,1"
|
|
bitfld.word 0x00 11.--12. " CEVT1SEL ,Comparator Event1 select" "0,1,2,3"
|
|
bitfld.word 0x00 10. " HZEN ,High level (Z) Threshold crossing output enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 9. " MFIE ,Modulator Failure Interrupt enable" "0,1"
|
|
bitfld.word 0x00 7.--8. " CS1_CS0 ,Comparator Filter Structure (SincFast/1/2/3)" "0,1,2,3"
|
|
bitfld.word 0x00 6. " EN_CEVT2 ,CEVT2 Interrupt enable." "0,1"
|
|
bitfld.word 0x00 5. " EN_CEVT1 ,CEVT1 Interrupt enable." "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--4. " COSR ,Comparator Oversample Ratio. Actual rate COSR+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long (d:0x00005E80+0x46)++0x03
|
|
line.long 0x00 "SDDATA4,Data Filter Data Register (16 or 32bit) for Ch4"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.long (d:0x00005E80+0x48)++0x03
|
|
line.long 0x00 "SDDATFIFO4,Filter Data FIFO Output(32b) for Ch4"
|
|
hexmask.long 0x00 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode, 16-bit Data in 16b mode"
|
|
hexmask.long 0x00 0.--15. 1. "DATA16,Lo-order 16b in 32b mode"
|
|
rgroup.word (d:0x00005E80+0x4A)++0x01
|
|
line.word 0x00 "SDCDATA4,Comparator Filter Data Register (16b) for Ch4"
|
|
group.word (d:0x00005E80+0x4B)++0x01
|
|
line.word 0x00 "SDFLT4CMPH2,Second high level threhold for CH4"
|
|
hexmask.word 0x00 0.--14. 1. "HLT2,Second High level threshold."
|
|
group.word (d:0x00005E80+0x4C)++0x01
|
|
line.word 0x00 "SDFLT4CMPHZ,High-level (Z) Threshold Register for Ch4"
|
|
hexmask.word 0x00 0.--14. 1. "HLTZ,High-level threshold (Z) for the comparator filter output"
|
|
group.word (d:0x00005E80+0x4D)++0x01
|
|
line.word 0x00 "SDFIFOCTL4,FIFO Control Register for Ch4"
|
|
bitfld.word 0x00 15. " OVFIEN ,SDFIFO Overflow interrupt enable" "0,1"
|
|
bitfld.word 0x00 14. " DRINTSEL ,Data-Ready Interrupt Source Select" "0,1"
|
|
bitfld.word 0x00 13. " FFEN ,SDFIFO Enable" "0,1"
|
|
bitfld.word 0x00 12. " FFIEN ,SDFIFO data ready Interrupt Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x00 6.--10. " SDFFST ,SDFIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " SDFFIL ,SDFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x4E)++0x01
|
|
line.word 0x00 "SDSYNC4,SD Filter Sync control for Ch4"
|
|
bitfld.word 0x00 10. " WTSCLREN ,WTSYNFLG Clear-on-FIFOINT Enable" "0,1"
|
|
bitfld.word 0x00 9. " FFSYNCCLREN ,FIFO Clear-on-SDSYNC Enable" "0,1"
|
|
bitfld.word 0x00 8. " WTSYNCLR ,Wait-for-Sync Flag Clear" "0,1"
|
|
rbitfld.word 0x00 7. " WTSYNFLG ,Wait-for-Sync Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. " WTSYNCEN ,Wait-for-Sync Enable" "0,1"
|
|
bitfld.word 0x00 0.--5. " SYNCSEL ,SDSYNC Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word (d:0x00005E80+0x4F)++0x01
|
|
line.word 0x00 "SDFLT4CMPL2,Second low level threhold for CH4"
|
|
hexmask.word 0x00 0.--14. 1. "LLT2,Second low-level threshold for the comparator filter output."
|
|
group.word (d:0x00005E80+0x60)++0x01
|
|
line.word 0x00 "SDCOMP1CTL,SD Comparator event filter1 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x61)++0x01
|
|
line.word 0x00 "SDCOMP1EVT2FLTCTL,COMPL/CEVT2 Digital filter1 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x62)++0x01
|
|
line.word 0x00 "SDCOMP1EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x63)++0x01
|
|
line.word 0x00 "SDCOMP1EVT1FLTCTL,COMPH/CEVT1 Digital filter1 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x64)++0x01
|
|
line.word 0x00 "SDCOMP1EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter1 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x67)++0x01
|
|
line.word 0x00 "SDCOMP1LOCK,SD compartor event filter1 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP1CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E80+0x68)++0x01
|
|
line.word 0x00 "SDCOMP2CTL,SD Comparator event filter2 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x69)++0x01
|
|
line.word 0x00 "SDCOMP2EVT2FLTCTL,COMPL/CEVT2 Digital filter2 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x6A)++0x01
|
|
line.word 0x00 "SDCOMP2EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x6B)++0x01
|
|
line.word 0x00 "SDCOMP2EVT1FLTCTL,COMPH/CEVT1 Digital filter2 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x6C)++0x01
|
|
line.word 0x00 "SDCOMP2EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter2 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x6F)++0x01
|
|
line.word 0x00 "SDCOMP2LOCK,SD compartor event filter2 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP2CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E80+0x70)++0x01
|
|
line.word 0x00 "SDCOMP3CTL,SD Comparator event filter3 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x71)++0x01
|
|
line.word 0x00 "SDCOMP3EVT2FLTCTL,COMPL/CEVT2 Digital filter3 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x72)++0x01
|
|
line.word 0x00 "SDCOMP3EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x73)++0x01
|
|
line.word 0x00 "SDCOMP3EVT1FLTCTL,COMPH/CEVT1 Digital filter3 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x74)++0x01
|
|
line.word 0x00 "SDCOMP3EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter3 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x77)++0x01
|
|
line.word 0x00 "SDCOMP3LOCK,SD compartor event filter3 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP3CTL ,COMPCTL Lock" "0,1"
|
|
group.word (d:0x00005E80+0x78)++0x01
|
|
line.word 0x00 "SDCOMP4CTL,SD Comparator event filter4 Control Register"
|
|
bitfld.word 0x00 10.--11. " CEVT2DIGFILTSEL ,Low Comparator Trip Select" "0,1,2,3"
|
|
bitfld.word 0x00 2.--3. " CEVT1DIGFILTSEL ,High Comparator Trip Select" "0,1,2,3"
|
|
group.word (d:0x00005E80+0x79)++0x01
|
|
line.word 0x00 "SDCOMP4EVT2FLTCTL,COMPL/CEVT2 Digital filter4 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x7A)++0x01
|
|
line.word 0x00 "SDCOMP4EVT2FLTCLKCTL,COMPL/CEVT2 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x7B)++0x01
|
|
line.word 0x00 "SDCOMP4EVT1FLTCTL,COMPH/CEVT1 Digital filter4 Control Register"
|
|
bitfld.word 0x00 15. " FILINIT ,Filter Initialization Bit" "0,1"
|
|
bitfld.word 0x00 9.--13. " THRESH ,Majority Voting Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 4.--8. " SAMPWIN ,Sample Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00005E80+0x7C)++0x01
|
|
line.word 0x00 "SDCOMP4EVT1FLTCLKCTL,COMPH/CEVT1 Digital filter4 Clock Control Register"
|
|
hexmask.word 0x00 0.--9. 1. "CLKPRESCALE,Sample Clock Prescale"
|
|
group.word (d:0x00005E80+0x7F)++0x01
|
|
line.word 0x00 "SDCOMP4LOCK,SD compartor event filter4 Lock Register"
|
|
bitfld.word 0x00 3. " COMP ,COMPevent filter registers Lock" "0,1"
|
|
bitfld.word 0x00 0. " SDCOMP4CTL ,COMPCTL Lock" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Serial Peripheral Interface (SPI)"
|
|
tree "SPI A"
|
|
width 10.
|
|
group.word (d:0x00006100+0x0+0x00)++0x01
|
|
line.word 0x00 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x00 7. " SPISWRESET ,SPI Software Reset" "0,1"
|
|
bitfld.word 0x00 6. " CLKPOLARITY ,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x00 5. " HS_MODE ,High Speed mode control" "0,1"
|
|
bitfld.word 0x00 4. " SPILBK ,SPI Loopback" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--3. " SPICHAR ,Character Length Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006100+0x0+0x01)++0x01
|
|
line.word 0x00 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x00 4. " OVERRUNINTENA ,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 3. " CLK_PHASE ,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x00 2. " MASTER_SLAVE ,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x00 1. " TALK ,Master/Slave Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " SPIINTENA ,SPI Interupt Enable" "0,1"
|
|
group.word (d:0x00006100+0x0+0x02)++0x01
|
|
line.word 0x00 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x00 7. " OVERRUN_FLAG ,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x00 6. " INT_FLAG ,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x00 5. " BUFFULL_FLAG ,SPI Transmit Buffer Full Flag" "0,1"
|
|
group.word (d:0x00006100+0x0+0x04)++0x01
|
|
line.word 0x00 "SPIBRR,SPI Baud Rate Register"
|
|
bitfld.word 0x00 0.--6. " SPI_BIT_RATE ,SPI Bit Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.word (d:0x00006100+0x0+0x06)++0x01
|
|
line.word 0x00 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
rgroup.word (d:0x00006100+0x0+0x07)++0x01
|
|
line.word 0x00 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
group.word (d:0x00006100+0x0+0x08)++0x01
|
|
line.word 0x00 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
group.word (d:0x00006100+0x0+0x09)++0x01
|
|
line.word 0x00 "SPIDAT,SPI Serial Data Register"
|
|
group.word (d:0x00006100+0x0+0x0A)++0x01
|
|
line.word 0x00 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x00 15. " SPIRST ,SPI Reset" "0,1"
|
|
bitfld.word 0x00 14. " SPIFFENA ,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFO ,TXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,TXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,TXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x0+0x0B)++0x01
|
|
line.word 0x00 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVFCLR ,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,RXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,RXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,RXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x0+0x0C)++0x01
|
|
line.word 0x00 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word 0x00 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word (d:0x00006100+0x0+0x0F)++0x01
|
|
line.word 0x00 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x00 5. " SOFT ,Soft emulation mode" "0,1"
|
|
bitfld.word 0x00 4. " FREE ,Free emulation mode" "0,1"
|
|
bitfld.word 0x00 1. " STEINV ,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x00 0. " TRIWIRE ,3-wire mode select bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI B"
|
|
width 10.
|
|
group.word (d:0x00006100+0x10+0x00)++0x01
|
|
line.word 0x00 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x00 7. " SPISWRESET ,SPI Software Reset" "0,1"
|
|
bitfld.word 0x00 6. " CLKPOLARITY ,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x00 5. " HS_MODE ,High Speed mode control" "0,1"
|
|
bitfld.word 0x00 4. " SPILBK ,SPI Loopback" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--3. " SPICHAR ,Character Length Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006100+0x10+0x01)++0x01
|
|
line.word 0x00 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x00 4. " OVERRUNINTENA ,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 3. " CLK_PHASE ,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x00 2. " MASTER_SLAVE ,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x00 1. " TALK ,Master/Slave Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " SPIINTENA ,SPI Interupt Enable" "0,1"
|
|
group.word (d:0x00006100+0x10+0x02)++0x01
|
|
line.word 0x00 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x00 7. " OVERRUN_FLAG ,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x00 6. " INT_FLAG ,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x00 5. " BUFFULL_FLAG ,SPI Transmit Buffer Full Flag" "0,1"
|
|
group.word (d:0x00006100+0x10+0x04)++0x01
|
|
line.word 0x00 "SPIBRR,SPI Baud Rate Register"
|
|
bitfld.word 0x00 0.--6. " SPI_BIT_RATE ,SPI Bit Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.word (d:0x00006100+0x10+0x06)++0x01
|
|
line.word 0x00 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
rgroup.word (d:0x00006100+0x10+0x07)++0x01
|
|
line.word 0x00 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
group.word (d:0x00006100+0x10+0x08)++0x01
|
|
line.word 0x00 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
group.word (d:0x00006100+0x10+0x09)++0x01
|
|
line.word 0x00 "SPIDAT,SPI Serial Data Register"
|
|
group.word (d:0x00006100+0x10+0x0A)++0x01
|
|
line.word 0x00 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x00 15. " SPIRST ,SPI Reset" "0,1"
|
|
bitfld.word 0x00 14. " SPIFFENA ,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFO ,TXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,TXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,TXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x10+0x0B)++0x01
|
|
line.word 0x00 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVFCLR ,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,RXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,RXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,RXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x10+0x0C)++0x01
|
|
line.word 0x00 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word 0x00 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word (d:0x00006100+0x10+0x0F)++0x01
|
|
line.word 0x00 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x00 5. " SOFT ,Soft emulation mode" "0,1"
|
|
bitfld.word 0x00 4. " FREE ,Free emulation mode" "0,1"
|
|
bitfld.word 0x00 1. " STEINV ,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x00 0. " TRIWIRE ,3-wire mode select bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI C"
|
|
width 10.
|
|
group.word (d:0x00006100+0x20+0x00)++0x01
|
|
line.word 0x00 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x00 7. " SPISWRESET ,SPI Software Reset" "0,1"
|
|
bitfld.word 0x00 6. " CLKPOLARITY ,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x00 5. " HS_MODE ,High Speed mode control" "0,1"
|
|
bitfld.word 0x00 4. " SPILBK ,SPI Loopback" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--3. " SPICHAR ,Character Length Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006100+0x20+0x01)++0x01
|
|
line.word 0x00 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x00 4. " OVERRUNINTENA ,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 3. " CLK_PHASE ,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x00 2. " MASTER_SLAVE ,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x00 1. " TALK ,Master/Slave Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " SPIINTENA ,SPI Interupt Enable" "0,1"
|
|
group.word (d:0x00006100+0x20+0x02)++0x01
|
|
line.word 0x00 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x00 7. " OVERRUN_FLAG ,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x00 6. " INT_FLAG ,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x00 5. " BUFFULL_FLAG ,SPI Transmit Buffer Full Flag" "0,1"
|
|
group.word (d:0x00006100+0x20+0x04)++0x01
|
|
line.word 0x00 "SPIBRR,SPI Baud Rate Register"
|
|
bitfld.word 0x00 0.--6. " SPI_BIT_RATE ,SPI Bit Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.word (d:0x00006100+0x20+0x06)++0x01
|
|
line.word 0x00 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
rgroup.word (d:0x00006100+0x20+0x07)++0x01
|
|
line.word 0x00 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
group.word (d:0x00006100+0x20+0x08)++0x01
|
|
line.word 0x00 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
group.word (d:0x00006100+0x20+0x09)++0x01
|
|
line.word 0x00 "SPIDAT,SPI Serial Data Register"
|
|
group.word (d:0x00006100+0x20+0x0A)++0x01
|
|
line.word 0x00 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x00 15. " SPIRST ,SPI Reset" "0,1"
|
|
bitfld.word 0x00 14. " SPIFFENA ,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFO ,TXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,TXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,TXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x20+0x0B)++0x01
|
|
line.word 0x00 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVFCLR ,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,RXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,RXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,RXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x20+0x0C)++0x01
|
|
line.word 0x00 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word 0x00 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word (d:0x00006100+0x20+0x0F)++0x01
|
|
line.word 0x00 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x00 5. " SOFT ,Soft emulation mode" "0,1"
|
|
bitfld.word 0x00 4. " FREE ,Free emulation mode" "0,1"
|
|
bitfld.word 0x00 1. " STEINV ,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x00 0. " TRIWIRE ,3-wire mode select bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI D"
|
|
width 10.
|
|
group.word (d:0x00006100+0x30+0x00)++0x01
|
|
line.word 0x00 "SPICCR,SPI Configuration Control Register"
|
|
bitfld.word 0x00 7. " SPISWRESET ,SPI Software Reset" "0,1"
|
|
bitfld.word 0x00 6. " CLKPOLARITY ,Shift Clock Polarity" "0,1"
|
|
bitfld.word 0x00 5. " HS_MODE ,High Speed mode control" "0,1"
|
|
bitfld.word 0x00 4. " SPILBK ,SPI Loopback" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--3. " SPICHAR ,Character Length Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00006100+0x30+0x01)++0x01
|
|
line.word 0x00 "SPICTL,SPI Operation Control Register"
|
|
bitfld.word 0x00 4. " OVERRUNINTENA ,Overrun Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 3. " CLK_PHASE ,SPI Clock Phase" "0,1"
|
|
bitfld.word 0x00 2. " MASTER_SLAVE ,SPI Network Mode Control" "0,1"
|
|
bitfld.word 0x00 1. " TALK ,Master/Slave Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. " SPIINTENA ,SPI Interupt Enable" "0,1"
|
|
group.word (d:0x00006100+0x30+0x02)++0x01
|
|
line.word 0x00 "SPISTS,SPI Status Register"
|
|
bitfld.word 0x00 7. " OVERRUN_FLAG ,SPI Receiver Overrun Flag" "0,1"
|
|
rbitfld.word 0x00 6. " INT_FLAG ,SPI Interrupt Flag" "0,1"
|
|
rbitfld.word 0x00 5. " BUFFULL_FLAG ,SPI Transmit Buffer Full Flag" "0,1"
|
|
group.word (d:0x00006100+0x30+0x04)++0x01
|
|
line.word 0x00 "SPIBRR,SPI Baud Rate Register"
|
|
bitfld.word 0x00 0.--6. " SPI_BIT_RATE ,SPI Bit Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.word (d:0x00006100+0x30+0x06)++0x01
|
|
line.word 0x00 "SPIRXEMU,SPI Emulation Buffer Register"
|
|
rgroup.word (d:0x00006100+0x30+0x07)++0x01
|
|
line.word 0x00 "SPIRXBUF,SPI Serial Input Buffer Register"
|
|
group.word (d:0x00006100+0x30+0x08)++0x01
|
|
line.word 0x00 "SPITXBUF,SPI Serial Output Buffer Register"
|
|
group.word (d:0x00006100+0x30+0x09)++0x01
|
|
line.word 0x00 "SPIDAT,SPI Serial Data Register"
|
|
group.word (d:0x00006100+0x30+0x0A)++0x01
|
|
line.word 0x00 "SPIFFTX,SPI FIFO Transmit Register"
|
|
bitfld.word 0x00 15. " SPIRST ,SPI Reset" "0,1"
|
|
bitfld.word 0x00 14. " SPIFFENA ,FIFO Enhancements Enable" "0,1"
|
|
bitfld.word 0x00 13. " TXFIFO ,TXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " TXFFST ,Transmit FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " TXFFINT ,TXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " TXFFINTCLR ,TXFIFO Interrupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " TXFFIENA ,TXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " TXFFIL ,TXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x30+0x0B)++0x01
|
|
line.word 0x00 "SPIFFRX,SPI FIFO Receive Register"
|
|
rbitfld.word 0x00 15. " RXFFOVF ,Receive FIFO Overflow Flag" "0,1"
|
|
bitfld.word 0x00 14. " RXFFOVFCLR ,Receive FIFO Overflow Clear" "0,1"
|
|
bitfld.word 0x00 13. " RXFIFORESET ,RXFIFO Reset" "0,1"
|
|
rbitfld.word 0x00 8.--12. " RXFFST ,Receive FIFO Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. " RXFFINT ,RXFIFO Interrupt Flag" "0,1"
|
|
bitfld.word 0x00 6. " RXFFINTCLR ,RXFIFO Interupt Clear" "0,1"
|
|
bitfld.word 0x00 5. " RXFFIENA ,RXFIFO Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0.--4. " RXFFIL ,RXFIFO Interrupt Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00006100+0x30+0x0C)++0x01
|
|
line.word 0x00 "SPIFFCT,SPI FIFO Control Register"
|
|
hexmask.word 0x00 0.--7. 1. "TXDLY,FIFO Transmit Delay Bits"
|
|
group.word (d:0x00006100+0x30+0x0F)++0x01
|
|
line.word 0x00 "SPIPRI,SPI Priority Control Register"
|
|
bitfld.word 0x00 5. " SOFT ,Soft emulation mode" "0,1"
|
|
bitfld.word 0x00 4. " FREE ,Free emulation mode" "0,1"
|
|
bitfld.word 0x00 1. " STEINV ,SPISTE inversion bit" "0,1"
|
|
bitfld.word 0x00 0. " TRIWIRE ,3-wire mode select bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Universal Serial Bus (USB)"
|
|
width 21.
|
|
group.byte (d:0x00040000+0x00)++0x00
|
|
line.byte 0x00 "USBFADDR,USB Device Functional Address"
|
|
bitfld.byte 0x00 0.--6. " FUNCADDR ,Functional Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x01)++0x00
|
|
line.byte 0x00 "USBPOWER,USB Power"
|
|
bitfld.byte 0x00 7. " ISOUP ,Isochronous Update" "0,1"
|
|
bitfld.byte 0x00 6. " SOFT_CONN ,Soft Connect/Disconnect" "0,1"
|
|
bitfld.byte 0x00 3. " RESET ,Enable Reset Signaling" "0,1"
|
|
bitfld.byte 0x00 2. " RESUME ,Enable Resume Signaling" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. " SUSPEND ,Enable Suspend" "0,1"
|
|
bitfld.byte 0x00 0. " PWRDNPHY ,Power Down PHY" "0,1"
|
|
rgroup.word (d:0x00040000+0x02)++0x01
|
|
line.word 0x00 "USBTXIS,USB Transmit Interrupt Status"
|
|
bitfld.word 0x00 3. " EP3 ,Transmit Endpoint 3 Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,Transmit Endpoint 2 Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,Transmit Endpoint 1 Interrupt" "0,1"
|
|
bitfld.word 0x00 0. " EP0 ,Transmit Endpoint 0 Interrupt" "0,1"
|
|
rgroup.word (d:0x00040000+0x04)++0x01
|
|
line.word 0x00 "USBRXIS,USB Receive Interrupt Status"
|
|
bitfld.word 0x00 3. " EP3 ,Recieve Endpoint 3 Interrupt" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,Recieve Endpoint 2 Interrupt" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,Recieve Endpoint 1 Interrupt" "0,1"
|
|
group.word (d:0x00040000+0x06)++0x01
|
|
line.word 0x00 "USBTXIE,USB Transmit Interrupt Enable"
|
|
bitfld.word 0x00 3. " EP3 ,Transmit Endpoint 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,Transmit Endpoint 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,Transmit Endpoint 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 0. " EP0 ,Transmit Endpoint 0 Interrupt Enable" "0,1"
|
|
group.word (d:0x00040000+0x08)++0x01
|
|
line.word 0x00 "USBRXIE,USB Receive Interrupt Enable"
|
|
bitfld.word 0x00 3. " EP3 ,Recieve Endpoint 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,Recieve Endpoint 2 Interrupt Enable" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,Recieve Endpoint 1 Interrupt Enable" "0,1"
|
|
group.byte (d:0x00040000+0x0A)++0x00
|
|
line.byte 0x00 "USBIS,USB General Interrupt Status"
|
|
bitfld.byte 0x00 5. " DISCON ,Session Disconnect" "0,1"
|
|
bitfld.byte 0x00 3. " SOF ,Start of frame" "0,1"
|
|
bitfld.byte 0x00 2. " RESET ,RESET Signaling Detected" "0,1"
|
|
bitfld.byte 0x00 1. " RESUME ,RESUME Signaling Detected." "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 0. " SUSPEND ,SUSPEND Signaling Detected" "0,1"
|
|
group.byte (d:0x00040000+0x0B)++0x00
|
|
line.byte 0x00 "USBIE,USB Interrupt Enable"
|
|
bitfld.byte 0x00 5. " DISCON ,Session Disconnect" "0,1"
|
|
bitfld.byte 0x00 3. " SOF ,Start of frame" "0,1"
|
|
bitfld.byte 0x00 2. " RESET ,RESET Signaling Detected" "0,1"
|
|
bitfld.byte 0x00 1. " RESUME ,RESUME Signaling Detected." "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 0. " SUSPEND ,SUSPEND Signaling Detected" "0,1"
|
|
rgroup.word (d:0x00040000+0x0C)++0x01
|
|
line.word 0x00 "USBFRAME,USB Frame Value"
|
|
hexmask.word 0x00 0.--10. 1. "FRAME,Frame Number"
|
|
group.byte (d:0x00040000+0x0E)++0x00
|
|
line.byte 0x00 "USBEPIDX,USB Endpoint Index"
|
|
bitfld.byte 0x00 0.--3. " EPIDX ,Endpoint Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x0F)++0x00
|
|
line.byte 0x00 "USBTEST,USB Test Mode"
|
|
bitfld.byte 0x00 7. " FORCEH ,Force Host Mode" "0,1"
|
|
bitfld.byte 0x00 6. " FIFOACC ,FIFO Access" "0,1"
|
|
bitfld.byte 0x00 5. " FORCEFS ,Force Full Speed Upon Reset" "0,1"
|
|
group.long (d:0x00040000+0x20)++0x03
|
|
line.long 0x00 "USBFIFO0,USB FIFO Endpoint 0"
|
|
group.long (d:0x00040000+0x24)++0x03
|
|
line.long 0x00 "USBFIFO1,USB FIFO Endpoint 1"
|
|
group.long (d:0x00040000+0x28)++0x03
|
|
line.long 0x00 "USBFIFO2,USB FIFO Endpoint 2"
|
|
group.long (d:0x00040000+0x2C)++0x03
|
|
line.long 0x00 "USBFIFO3,USB FIFO Endpoint 3"
|
|
group.word (d:0x00040000+0x60)++0x01
|
|
line.word 0x00 "USBDEVCTL,USB Device Control"
|
|
rbitfld.word 0x00 7. " DEV ,Device Mode" "0,1"
|
|
bitfld.word 0x00 6. " FSDEV ,Full Speed Device Detected" "0,1"
|
|
rbitfld.word 0x00 5. " LSDEV ,Low Speed Device Detected" "0,1"
|
|
bitfld.word 0x00 3.--4. " VBUS ,Vbus Level" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 2. " HOST ,Host Mode" "0,1"
|
|
bitfld.word 0x00 1. " HOSTREQ ,Host Request" "0,1"
|
|
rbitfld.word 0x00 0. " SESSION ,Session Start/End" "0,1"
|
|
group.byte (d:0x00040000+0x62)++0x00
|
|
line.byte 0x00 "USBTXFIFOSZ,USB Transmit Dynamic FIFO Sizing"
|
|
bitfld.byte 0x00 4. " DPB ,Double Packet Buffer Support" "0,1"
|
|
rbitfld.byte 0x00 0.--3. " SIZE ,Max Packet Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x63)++0x00
|
|
line.byte 0x00 "USBRXFIFOSZ,USB Receive Dynamic FIFO Sizing"
|
|
bitfld.byte 0x00 4. " DPB ,Double Packet Buffer Support" "0,1"
|
|
rbitfld.byte 0x00 0.--3. " SIZE ,Max Packet Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word (d:0x00040000+0x64)++0x01
|
|
line.word 0x00 "USBTXFIFOADD,USB Transmit FIFO Start Address"
|
|
hexmask.word 0x00 0.--8. 1. "ADDR,Endpoint Data"
|
|
group.word (d:0x00040000+0x66)++0x01
|
|
line.word 0x00 "USBRXFIFOADD,USB Receive FIFO Start Address"
|
|
hexmask.word 0x00 0.--8. 1. "ADDR,Endpoint Data"
|
|
group.byte (d:0x00040000+0x7A)++0x00
|
|
line.byte 0x00 "USBCONTIM,USB Connect Timing"
|
|
bitfld.byte 0x00 4.--7. " WTCON ,Connect Wait" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " WTID ,Wait ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x7D)++0x00
|
|
line.byte 0x00 "USBFSEOF,USB Full-Speed Last Transaction to End of Frame Timing"
|
|
group.byte (d:0x00040000+0x7E)++0x00
|
|
line.byte 0x00 "USBLSEOF,USB Low-Speed Last Transaction to End of Frame Timing"
|
|
group.byte (d:0x00040000+0x80)++0x00
|
|
line.byte 0x00 "USBTXFUNCADDR0,USB Transmit Functional Address Endpoint 0"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x82)++0x00
|
|
line.byte 0x00 "USBTXHUBADDR0,USB Transmit Hub Address Endpoint 0"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x83)++0x00
|
|
line.byte 0x00 "USBTXHUBPORT0,USB Transmit Hub Port Endpoint 0"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x88)++0x00
|
|
line.byte 0x00 "USBTXFUNCADDR1,USB Transmit Functional Address Endpoint 1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x8A)++0x00
|
|
line.byte 0x00 "USBTXHUBADDR1,USB Transmit Hub Address Endpoint 1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x8B)++0x00
|
|
line.byte 0x00 "USBTXHUBPORT1,USB Transmit Hub Port Endpoint 1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x8C)++0x00
|
|
line.byte 0x00 "USBRXFUNCADDR1,USB Receive Functional Address Endpoint 1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x8E)++0x00
|
|
line.byte 0x00 "USBRXHUBADDR1,USB Receive Hub Address Endpoint 1"
|
|
bitfld.byte 0x00 7. " MULTTRAN ,Hub has Multiple Translators" "0,1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x8F)++0x00
|
|
line.byte 0x00 "USBRXHUBPORT1,USB Receive Hub Port Endpoint 1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x90)++0x00
|
|
line.byte 0x00 "USBTXFUNCADDR2,USB Transmit Functional Address Endpoint 2"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x92)++0x00
|
|
line.byte 0x00 "USBTXHUBADDR2,USB Transmit Hub Address Endpoint 2"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x93)++0x00
|
|
line.byte 0x00 "USBTXHUBPORT2,USB Transmit Hub Port Endpoint 2"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x94)++0x00
|
|
line.byte 0x00 "USBRXFUNCADDR2,USB Receive Functional Address Endpoint 2"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x96)++0x00
|
|
line.byte 0x00 "USBRXHUBADDR2,USB Receive Hub Address Endpoint 2"
|
|
bitfld.byte 0x00 7. " MULTTRAN ,Hub has Multiple Translators" "0,1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x97)++0x00
|
|
line.byte 0x00 "USBRXHUBPORT2,USB Receive Hub Port Endpoint 2"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x98)++0x00
|
|
line.byte 0x00 "USBTXFUNCADDR3,USB Transmit Functional Address Endpoint 3"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x9A)++0x00
|
|
line.byte 0x00 "USBTXHUBADDR3,USB Transmit Hub Address Endpoint 3"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x9B)++0x00
|
|
line.byte 0x00 "USBTXHUBPORT3,USB Transmit Hub Port Endpoint 3"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x9C)++0x00
|
|
line.byte 0x00 "USBRXFUNCADDR3,USB Receive Functional Address Endpoint 3"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Device Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x9E)++0x00
|
|
line.byte 0x00 "USBRXHUBADDR3,USB Receive Hub Address Endpoint 3"
|
|
bitfld.byte 0x00 7. " MULTTRAN ,Hub has Multiple Translators" "0,1"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x9F)++0x00
|
|
line.byte 0x00 "USBRXHUBPORT3,USB Receive Hub Port Endpoint 3"
|
|
bitfld.byte 0x00 0.--6. " ADDR ,Hub Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x102)++0x00
|
|
line.byte 0x00 "USBCSRL0,USB Control and Status Endpoint 0 Low"
|
|
bitfld.byte 0x00 7. " SETENDC_NAKTO ,Setup End Clear/NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 6. " RXRDYC_STATUS ,RXRDY Clear/STATUS Packet" "0,1"
|
|
bitfld.byte 0x00 5. " STALL_RQPKT ,Send Stall /Request Packet" "0,1"
|
|
bitfld.byte 0x00 4. " SETEND_ERROR ,Setup End/Error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DATAEND_SETUP ,Data End/Setup Packet" "0,1"
|
|
bitfld.byte 0x00 2. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 1. " TXRDY ,Transmit Packet Ready" "0,1"
|
|
bitfld.byte 0x00 0. " RXRDY ,Receive Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x103)++0x00
|
|
line.byte 0x00 "USBCSRH0,USB Control and Status Endpoint 0 High"
|
|
bitfld.byte 0x00 2. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 1. " DT ,Data Toggle" "0,1"
|
|
bitfld.byte 0x00 0. " FLUSH ,Flush FIFO" "0,1"
|
|
group.byte (d:0x00040000+0x108)++0x00
|
|
line.byte 0x00 "USBCOUNT0,USB Receive Byte Count Endpoint 0"
|
|
bitfld.byte 0x00 0.--6. " COUNT ,FIFO Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.byte (d:0x00040000+0x10A)++0x00
|
|
line.byte 0x00 "USBTYPE0,USB Type Endpoint 0"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
group.byte (d:0x00040000+0x10B)++0x00
|
|
line.byte 0x00 "USBNAKLMT,USB NAK Limit"
|
|
bitfld.byte 0x00 0.--4. " NAKLMT ,EP0 NAK Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word (d:0x00040000+0x110)++0x01
|
|
line.word 0x00 "USBTXMAXP1,USB Maximum Transmit Data Endpoint 1"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x112)++0x00
|
|
line.byte 0x00 "USBTXCSRL1,USB Transmit Control and Status Endpoint 1 Low"
|
|
bitfld.byte 0x00 7. " NAKTO ,NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 6. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 5. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 4. " STALL_SETUP ,Send Stall/Setup Packet" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FLUSH ,Flush FIFO" "0,1"
|
|
bitfld.byte 0x00 2. " UNDRN_ERROR1 ,Underun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FIFONE ,FIFO Not Empty" "0,1"
|
|
bitfld.byte 0x00 0. " TXRDY ,Transmit Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x113)++0x00
|
|
line.byte 0x00 "USBTXCSRH1,USB Transmit Control and Status Endpoint 1 High"
|
|
bitfld.byte 0x00 7. " AUTOSET ,Auto Set" "0,1"
|
|
bitfld.byte 0x00 6. " ISO ,Isochronous Transfers" "0,1"
|
|
bitfld.byte 0x00 5. " MODE ,Mode" "0,1"
|
|
bitfld.byte 0x00 4. " DMAEN ,DMA Request Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FDT ,Force Data Toggle" "0,1"
|
|
bitfld.byte 0x00 2. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 1. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 0. " DT ,Data Toggle" "0,1"
|
|
group.word (d:0x00040000+0x114)++0x01
|
|
line.word 0x00 "USBRXMAXP1,USB Maximum Receive Data Endpoint 1"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x116)++0x00
|
|
line.byte 0x00 "USBRXCSRL1,USB Receive Control and Status Endpoint 1 Low"
|
|
bitfld.byte 0x00 7. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 6. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 5. " STALLREQPKT ,Send Stall/Request Packet" "0,1"
|
|
bitfld.byte 0x00 4. " FLUSH ,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DATAERRNAKTO ,Data Error/NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 2. " OVERERROR1 ,Overrun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FULL ,FIFO Full" "0,1"
|
|
bitfld.byte 0x00 0. " RXRDY ,Recieve Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x117)++0x00
|
|
line.byte 0x00 "USBRXCSRH1,USB Receive Control and Status Endpoint 1 High"
|
|
bitfld.byte 0x00 7. " AUTOCL ,Auto Clear" "0,1"
|
|
bitfld.byte 0x00 6. " ISOAUTORQ ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.byte 0x00 5. " DMAEN ,DMA Request Enable" "0,1"
|
|
bitfld.byte 0x00 4. " DISNYETPIDERR ,Disable NYET / PID Error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 2. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 1. " DT ,Data Toggle" "0,1"
|
|
rgroup.word (d:0x00040000+0x118)++0x01
|
|
line.word 0x00 "USBRXCOUNT1,USB Receive Byte Count Endpoint 1"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.byte (d:0x00040000+0x11A)++0x00
|
|
line.byte 0x00 "USBTXTYPE1,USB Host Transmit Configure Type Endpoint 1"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x11B)++0x00
|
|
line.byte 0x00 "USBTXINTERVAL1,USB Host Transmit Interval Endpoint 1"
|
|
group.byte (d:0x00040000+0x11C)++0x00
|
|
line.byte 0x00 "USBRXTYPE1,USB Host Configure Receive Type Endpoint 1"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x11D)++0x00
|
|
line.byte 0x00 "USBRXINTERVAL1,USB Host Receive Polling Interval Endpoint 1"
|
|
group.word (d:0x00040000+0x120)++0x01
|
|
line.word 0x00 "USBTXMAXP2,USB Maximum Transmit Data Endpoint 2"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x122)++0x00
|
|
line.byte 0x00 "USBTXCSRL2,USB Transmit Control and Status Endpoint 2 Low"
|
|
bitfld.byte 0x00 7. " NAKTO ,NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 6. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 5. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 4. " STALL_SETUP ,Send Stall/Setup Packet" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FLUSH ,Flush FIFO" "0,1"
|
|
bitfld.byte 0x00 2. " UNDRNERROR2 ,Underun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FIFONE ,FIFO Not Empty" "0,1"
|
|
bitfld.byte 0x00 0. " TXRDY ,Transmit Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x123)++0x00
|
|
line.byte 0x00 "USBTXCSRH2,USB Transmit Control and Status Endpoint 2 High"
|
|
bitfld.byte 0x00 7. " AUTOSET ,Auto Set" "0,1"
|
|
bitfld.byte 0x00 6. " ISO ,Isochronous Transfers" "0,1"
|
|
bitfld.byte 0x00 5. " MODE ,Mode" "0,1"
|
|
bitfld.byte 0x00 4. " DMAEN ,DMA Request Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FDT ,Force Data Toggle" "0,1"
|
|
bitfld.byte 0x00 2. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 1. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 0. " DT ,Data Toggle" "0,1"
|
|
group.word (d:0x00040000+0x124)++0x01
|
|
line.word 0x00 "USBRXMAXP2,USB Maximum Receive Data Endpoint 2"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x126)++0x00
|
|
line.byte 0x00 "USBRXCSRL2,USB Receive Control and Status Endpoint 2 Low"
|
|
bitfld.byte 0x00 7. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 6. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 5. " STALLREQPKT ,Send Stall/Request Packet" "0,1"
|
|
bitfld.byte 0x00 4. " FLUSH ,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DATAERRNAKTO ,Data Error/NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 2. " OVERERROR2 ,Overrun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FULL ,FIFO Full" "0,1"
|
|
bitfld.byte 0x00 0. " RXRDY ,Recieve Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x127)++0x00
|
|
line.byte 0x00 "USBRXCSRH2,USB Receive Control and Status Endpoint 2 High"
|
|
bitfld.byte 0x00 7. " AUTOCL ,Auto Clear" "0,1"
|
|
bitfld.byte 0x00 6. " ISOAUTORQ ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.byte 0x00 5. " DMAEN ,DMA Request Enable" "0,1"
|
|
bitfld.byte 0x00 4. " DISNYETPIDERR ,Disable NYET / PID Error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 2. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 1. " DT ,Data Toggle" "0,1"
|
|
rgroup.word (d:0x00040000+0x128)++0x01
|
|
line.word 0x00 "USBRXCOUNT2,USB Receive Byte Count Endpoint 2"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.byte (d:0x00040000+0x12A)++0x00
|
|
line.byte 0x00 "USBTXTYPE2,USB Host Transmit Configure Type Endpoint 2"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x12B)++0x00
|
|
line.byte 0x00 "USBTXINTERVAL2,USB Host Transmit Interval Endpoint 2"
|
|
group.byte (d:0x00040000+0x12C)++0x00
|
|
line.byte 0x00 "USBRXTYPE2,USB Host Configure Receive Type Endpoint 2"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x12D)++0x00
|
|
line.byte 0x00 "USBRXINTERVAL2,USB Host Receive Polling Interval Endpoint 2"
|
|
group.word (d:0x00040000+0x130)++0x01
|
|
line.word 0x00 "USBTXMAXP3,USB Maximum Transmit Data Endpoint 3"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x132)++0x00
|
|
line.byte 0x00 "USBTXCSRL3,USB Transmit Control and Status Endpoint 3 Low"
|
|
bitfld.byte 0x00 7. " NAKTO ,NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 6. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 5. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 4. " STALL_SETUP ,Send Stall/Setup Packet" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FLUSH ,Flush FIFO" "0,1"
|
|
bitfld.byte 0x00 2. " UNDRNERROR3 ,Underun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FIFONE ,FIFO Not Empty" "0,1"
|
|
bitfld.byte 0x00 0. " TXRDY ,Transmit Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x133)++0x00
|
|
line.byte 0x00 "USBTXCSRH3,USB Transmit Control and Status Endpoint 3 High"
|
|
bitfld.byte 0x00 7. " AUTOSET ,Auto Set" "0,1"
|
|
bitfld.byte 0x00 6. " ISO ,Isochronous Transfers" "0,1"
|
|
bitfld.byte 0x00 5. " MODE ,Mode" "0,1"
|
|
bitfld.byte 0x00 4. " DMAEN ,DMA Request Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " FDT ,Force Data Toggle" "0,1"
|
|
bitfld.byte 0x00 2. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 1. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 0. " DT ,Data Toggle" "0,1"
|
|
group.word (d:0x00040000+0x134)++0x01
|
|
line.word 0x00 "USBRXMAXP3,USB Maximum Receive Data Endpoint 3"
|
|
hexmask.word 0x00 0.--10. 1. "MAXLOAD,Maximum Payload"
|
|
group.byte (d:0x00040000+0x136)++0x00
|
|
line.byte 0x00 "USBRXCSRL3,USB Receive Control and Status Endpoint 3 Low"
|
|
bitfld.byte 0x00 7. " CLRDT ,Clear Data Toggle" "0,1"
|
|
bitfld.byte 0x00 6. " STALLED ,Endpoint Stalled" "0,1"
|
|
bitfld.byte 0x00 5. " STALLREQPKT ,Send Stall/Request Packet" "0,1"
|
|
bitfld.byte 0x00 4. " FLUSH ,Flush FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DATAERRNAKTO ,Data Error/NAK Timeout" "0,1"
|
|
bitfld.byte 0x00 2. " OVERERROR3 ,Overrun/Error" "0,1"
|
|
bitfld.byte 0x00 1. " FULL ,FIFO Full" "0,1"
|
|
bitfld.byte 0x00 0. " RXRDY ,Recieve Packet Ready" "0,1"
|
|
group.byte (d:0x00040000+0x137)++0x00
|
|
line.byte 0x00 "USBRXCSRH3,USB Receive Control and Status Endpoint 3 High"
|
|
bitfld.byte 0x00 7. " AUTOCL ,Auto Clear" "0,1"
|
|
bitfld.byte 0x00 6. " ISOAUTORQ ,Isochronous Transfers/Auto Request" "0,1"
|
|
bitfld.byte 0x00 5. " DMAEN ,DMA Request Enable" "0,1"
|
|
bitfld.byte 0x00 4. " DISNYETPIDERR ,Disable NYET / PID Error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. " DMAMOD ,DMA Request Mode" "0,1"
|
|
bitfld.byte 0x00 2. " DTWE ,Data Toggle Write Enable" "0,1"
|
|
bitfld.byte 0x00 1. " DT ,Data Toggle" "0,1"
|
|
rgroup.word (d:0x00040000+0x138)++0x01
|
|
line.word 0x00 "USBRXCOUNT3,USB Receive Byte Count Endpoint 3"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,Receive Packet Count"
|
|
group.byte (d:0x00040000+0x13A)++0x00
|
|
line.byte 0x00 "USBTXTYPE3,USB Host Transmit Configure Type Endpoint 3"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x13B)++0x00
|
|
line.byte 0x00 "USBTXINTERVAL3,USB Host Transmit Interval Endpoint 3"
|
|
group.byte (d:0x00040000+0x13C)++0x00
|
|
line.byte 0x00 "USBRXTYPE3,USB Host Configure Receive Type Endpoint 3"
|
|
bitfld.byte 0x00 6.--7. " SPEED ,Operating Speed" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. " PROTO ,Protocol" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " TEP ,Target Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte (d:0x00040000+0x13D)++0x00
|
|
line.byte 0x00 "USBRXINTERVAL3,USB Host Receive Polling Interval Endpoint 3"
|
|
group.word (d:0x00040000+0x304)++0x01
|
|
line.word 0x00 "USBRQPKTCOUNT1,USB Request Packet Count in Block Transfer Endpoint 1"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,FIFO Count"
|
|
group.word (d:0x00040000+0x308)++0x01
|
|
line.word 0x00 "USBRQPKTCOUNT2,USB Request Packet Count in Block Transfer Endpoint 2"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,FIFO Count"
|
|
group.word (d:0x00040000+0x30C)++0x01
|
|
line.word 0x00 "USBRQPKTCOUNT3,USB Request Packet Count in Block Transfer Endpoint 3"
|
|
hexmask.word 0x00 0.--12. 1. "COUNT,FIFO Count"
|
|
rgroup.word (d:0x00040000+0x340)++0x01
|
|
line.word 0x00 "USBRXDPKTBUFDIS,USB Receive Double Packet Buffer Disable"
|
|
bitfld.word 0x00 3. " EP3 ,EP3 RX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,EP2 RX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,EP1 RX Double Packet Buffer Disable" "0,1"
|
|
rgroup.word (d:0x00040000+0x342)++0x01
|
|
line.word 0x00 "USBTXDPKTBUFDIS,USB Transmit Double Packet Buffer Disable"
|
|
bitfld.word 0x00 3. " EP3 ,EP3 TX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x00 2. " EP2 ,EP2 TX Double Packet Buffer Disable" "0,1"
|
|
bitfld.word 0x00 1. " EP1 ,EP1 TX Double Packet Buffer Disable" "0,1"
|
|
group.long (d:0x00040000+0x400)++0x03
|
|
line.long 0x00 "USBEPC,USB External Power Control"
|
|
bitfld.long 0x00 8.--9. " PFLTACT ,Power Fault Action" "0,1,2,3"
|
|
bitfld.long 0x00 6. " PFLTAEN ,Power Fault Action Enable" "0,1"
|
|
bitfld.long 0x00 5. " PFLTSEN ,Power Fault Sense" "0,1"
|
|
bitfld.long 0x00 4. " PFLTEN ,Power Fault Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " EPENDE ,EPEN Drive Enable" "0,1"
|
|
bitfld.long 0x00 0.--1. " EPEN ,External Power Supply Enable Configuration" "0,1,2,3"
|
|
rgroup.long (d:0x00040000+0x404)++0x03
|
|
line.long 0x00 "USBEPCRIS,USB External Power Control Raw Interrupt Status"
|
|
bitfld.long 0x00 0. " PF ,Power Fault Interrupt Status" "0,1"
|
|
rgroup.long (d:0x00040000+0x408)++0x03
|
|
line.long 0x00 "USBEPCIM,USB External Power Control Interrupt Mask"
|
|
bitfld.long 0x00 0. " PF ,Power Fault Interrupt Mask" "0,1"
|
|
rgroup.long (d:0x00040000+0x40C)++0x03
|
|
line.long 0x00 "USBEPCISC,USB External Power Control Interrupt Status and Clear"
|
|
bitfld.long 0x00 0. " PF ,Power Fault Interrupt Status and Clear" "0,1"
|
|
rgroup.long (d:0x00040000+0x410)++0x03
|
|
line.long 0x00 "USBDRRIS,USB Device RESUME Raw Interrupt Status"
|
|
bitfld.long 0x00 0. " RESUME ,Resume Interrupt Status" "0,1"
|
|
rgroup.long (d:0x00040000+0x414)++0x03
|
|
line.long 0x00 "USBDRIM,USB Device RESUME Interrupt Mask"
|
|
bitfld.long 0x00 0. " RESUME ,Resume Interrupt Mask" "0,1"
|
|
group.long (d:0x00040000+0x418)++0x03
|
|
line.long 0x00 "USBDRISC,USB Device RESUME Interrupt Status and Clear"
|
|
bitfld.long 0x00 0. " RESUME ,Resume Interrupt Status and Clear" "0,1"
|
|
group.long (d:0x00040000+0x41C)++0x03
|
|
line.long 0x00 "USBGPCS,USB General-Purpose Control and Status"
|
|
bitfld.long 0x00 1. " DEVMODOTG ,Enable Device Mode" "0,1"
|
|
bitfld.long 0x00 0. " DEVMOD ,Device Mode" "0,1"
|
|
group.long (d:0x00040000+0x430)++0x03
|
|
line.long 0x00 "USBVDC,USB VBUS Droop Control"
|
|
bitfld.long 0x00 0. " VBDEN ,Vbus Droop Enable" "0,1"
|
|
rgroup.long (d:0x00040000+0x434)++0x03
|
|
line.long 0x00 "USBVDCRIS,USB VBUS Droop Control Raw Interrupt Status"
|
|
bitfld.long 0x00 0. " VD ,Vbus Droop Raw Interrupt Status" "0,1"
|
|
rgroup.long (d:0x00040000+0x438)++0x03
|
|
line.long 0x00 "USBVDCIM,USB VBUS Droop Control Interrupt Mask"
|
|
bitfld.long 0x00 0. " VD ,Vbus Droop Interrupt Mask" "0,1"
|
|
group.long (d:0x00040000+0x43C)++0x03
|
|
line.long 0x00 "USBVDCISC,USB VBUS Droop Control Interrupt Status and Clear"
|
|
bitfld.long 0x00 0. " VD ,Vbus Droop Interrupt Status and Clear" "0,1"
|
|
group.long (d:0x00040000+0x444)++0x03
|
|
line.long 0x00 "USBIDVRIS,USB ID Valid Detect Raw Interrupt Status"
|
|
bitfld.long 0x00 0. " ID ,ID Valid Detect Raw Interrupt Status" "0,1"
|
|
group.long (d:0x00040000+0x448)++0x03
|
|
line.long 0x00 "USBIDVIM,USB ID Valid Detect Interrupt Mask"
|
|
bitfld.long 0x00 0. " ID ,ID Valid Detect Interrupt mask" "0,1"
|
|
group.long (d:0x00040000+0x44C)++0x03
|
|
line.long 0x00 "USBIDVISC,USB ID Valid Detect Interrupt Status and Clear"
|
|
bitfld.long 0x00 0. " ID ,ID Valid Detect Interrupt Status and Clear" "0,1"
|
|
group.long (d:0x00040000+0x450)++0x03
|
|
line.long 0x00 "USBDMASEL,USB DMA Select"
|
|
bitfld.long 0x00 20.--23. " DMACTX ,DMA C TX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DMACRX ,DMA C RX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DMABTX ,DMA B TX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DMABRX ,DMA B RX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DMAATX ,DMA A TX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DMAARX ,DMA A RX Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x00040000+0x480)++0x03
|
|
line.long 0x00 "USB_GLB_INT_EN,USB Global Interrupt Enable Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x00 0. " INTEN ,Global Interrupt Enable" "0,1"
|
|
group.long (d:0x00040000+0x484)++0x03
|
|
line.long 0x00 "USB_GLB_INT_FLG,USB Global Interrupt Flag Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x00 0. " INTFLG ,Global Interrupt Flag" "0,1"
|
|
group.long (d:0x00040000+0x488)++0x03
|
|
line.long 0x00 "USB_GLB_INT_FLG_CLR,USB Global Interrupt Flag Clear Register[[br]]Note: This Register is applicable only when USB is mapped to CPU1"
|
|
bitfld.long 0x00 0. " INTFLG ,Global Interrupt Flag Clear" "0,1"
|
|
rgroup.long (d:0x00040000+0x500)++0x03
|
|
line.long 0x00 "USBDMARIS,USB uDMA Raw Interrupt Status register.[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x00 5. " USB_DMAC_TX_DONE ,DMA Tx done interrupt for DMAC" "0,1"
|
|
bitfld.long 0x00 4. " USB_DMAC_RX_DONE ,DMA Rx done interrupt for DMAC" "0,1"
|
|
bitfld.long 0x00 3. " USB_DMAB_TX_DONE ,DMA Tx done interrupt for DMAB" "0,1"
|
|
bitfld.long 0x00 2. " USB_DMAB_RX_DONE ,DMA Rx done interrupt for DMAB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " USB_DMAA_TX_DONE ,DMA Tx done interrupt for DMAA" "0,1"
|
|
bitfld.long 0x00 0. " USB_DMAA_Rx_DONE ,DMA Rx done interrupt for DMAA" "0,1"
|
|
group.long (d:0x00040000+0x504)++0x03
|
|
line.long 0x00 "USBDMAIM,USB uDMA Interrupt Mask Register[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x00 5. " USB_DMAC_TX_DONE ,DMA Tx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x00 4. " USB_DMAC_RX_DONE ,DMA Rx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x00 3. " USB_DMAB_TX_DONE ,DMA Tx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x00 2. " USB_DMAB_RX_DONE ,DMA Rx done interrupt mask for DMAB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " USB_DMAA_TX_DONE ,DMA Tx done interrupt mask for DMAA" "0,1"
|
|
bitfld.long 0x00 0. " USB_DMAA_Rx_DONE ,DMA Rx done interrupt mask for DMAA" "0,1"
|
|
group.long (d:0x00040000+0x508)++0x03
|
|
line.long 0x00 "USBDMAISC,USB uDMA Interrupt Status and Clear Register[[br]]Note: This Register is applicable only when USB is mapped to CM"
|
|
bitfld.long 0x00 5. " USB_DMAC_TX_DONE ,DMA Tx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x00 4. " USB_DMAC_RX_DONE ,DMA Rx done interrupt mask for DMAC" "0,1"
|
|
bitfld.long 0x00 3. " USB_DMAB_TX_DONE ,DMA Tx done interrupt mask for DMAB" "0,1"
|
|
bitfld.long 0x00 2. " USB_DMAB_RX_DONE ,DMA Rx done interrupt mask for DMAB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " USB_DMAA_TX_DONE ,DMA Tx done interrupt mask for DMAA" "0,1"
|
|
bitfld.long 0x00 0. " USB_DMAA_Rx_DONE ,DMA Rx done interrupt mask for DMAA" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Crossbar (X-BAR)"
|
|
sif !cpuis("F28384D*")&&!cpuis("F28384S*")
|
|
tree "ClbXbarRegs"
|
|
width 21.
|
|
group.long (d:0x00007A40+0x00)++0x03
|
|
line.long 0x00 "AUXSIG0MUX0TO15CFG,CLB XBAR Mux Configuration for Output-0"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x02)++0x03
|
|
line.long 0x00 "AUXSIG0MUX16TO31CFG,CLB XBAR Mux Configuration for Output-0"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG0 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x04)++0x03
|
|
line.long 0x00 "AUXSIG1MUX0TO15CFG,CLB XBAR Mux Configuration for Output-1"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x06)++0x03
|
|
line.long 0x00 "AUXSIG1MUX16TO31CFG,CLB XBAR Mux Configuration for Output-1"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG1 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x08)++0x03
|
|
line.long 0x00 "AUXSIG2MUX0TO15CFG,CLB XBAR Mux Configuration for Output-2"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x0A)++0x03
|
|
line.long 0x00 "AUXSIG2MUX16TO31CFG,CLB XBAR Mux Configuration for Output-2"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG2 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x0C)++0x03
|
|
line.long 0x00 "AUXSIG3MUX0TO15CFG,CLB XBAR Mux Configuration for Output-3"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x0E)++0x03
|
|
line.long 0x00 "AUXSIG3MUX16TO31CFG,CLB XBAR Mux Configuration for Output-3"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG3 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x10)++0x03
|
|
line.long 0x00 "AUXSIG4MUX0TO15CFG,CLB XBAR Mux Configuration for Output-4"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x12)++0x03
|
|
line.long 0x00 "AUXSIG4MUX16TO31CFG,CLB XBAR Mux Configuration for Output-4"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG4 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x14)++0x03
|
|
line.long 0x00 "AUXSIG5MUX0TO15CFG,CLB XBAR Mux Configuration for Output-5"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x16)++0x03
|
|
line.long 0x00 "AUXSIG5MUX16TO31CFG,CLB XBAR Mux Configuration for Output-5"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG5 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x18)++0x03
|
|
line.long 0x00 "AUXSIG6MUX0TO15CFG,CLB XBAR Mux Configuration for Output-6"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x1A)++0x03
|
|
line.long 0x00 "AUXSIG6MUX16TO31CFG,CLB XBAR Mux Configuration for Output-6"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG6 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x1C)++0x03
|
|
line.long 0x00 "AUXSIG7MUX0TO15CFG,CLB XBAR Mux Configuration for Output-7"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,MUX15 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,MUX14 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,MUX13 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,MUX12 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,MUX11 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,MUX10 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,MUX9 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,MUX8 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,MUX7 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,MUX6 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,MUX5 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,MUX4 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,MUX3 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,MUX2 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,MUX1 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,MUX0 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x1E)++0x03
|
|
line.long 0x00 "AUXSIG7MUX16TO31CFG,CLB XBAR Mux Configuration for Output-7"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,MUX31 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,MUX30 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,MUX29 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,MUX28 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,MUX27 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,MUX26 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,MUX25 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,MUX24 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,MUX23 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,MUX22 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,MUX21 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,MUX20 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,MUX19 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,MUX18 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,MUX17 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,MUX16 Configuration for AUXSIG7 of CLB-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A40+0x20)++0x03
|
|
line.long 0x00 "AUXSIG0MUXENABLE,CLB XBAR Mux Enable Register for Output-0"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG0 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x22)++0x03
|
|
line.long 0x00 "AUXSIG1MUXENABLE,CLB XBAR Mux Enable Register for Output-1"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG1 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x24)++0x03
|
|
line.long 0x00 "AUXSIG2MUXENABLE,CLB XBAR Mux Enable Register for Output-2"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG2 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x26)++0x03
|
|
line.long 0x00 "AUXSIG3MUXENABLE,CLB XBAR Mux Enable Register for Output-3"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG3 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x28)++0x03
|
|
line.long 0x00 "AUXSIG4MUXENABLE,CLB XBAR Mux Enable Register for Output-4"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
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bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG4 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x2A)++0x03
|
|
line.long 0x00 "AUXSIG5MUXENABLE,CLB XBAR Mux Enable Register for Output-5"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG5 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x2C)++0x03
|
|
line.long 0x00 "AUXSIG6MUXENABLE,CLB XBAR Mux Enable Register for Output-6"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG6 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x2E)++0x03
|
|
line.long 0x00 "AUXSIG7MUXENABLE,CLB XBAR Mux Enable Register for Output-7"
|
|
bitfld.long 0x00 31. " MUX31 ,MUX31 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,MUX30 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,MUX29 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,MUX28 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,MUX27 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,MUX26 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,MUX25 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,MUX24 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,MUX23 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,MUX22 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,MUX21 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,MUX20 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,MUX19 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,MUX18 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,MUX17 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,MUX16 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,MUX15 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,MUX14 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,MUX13 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,MUX12 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,MUX11 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,MUX10 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,MUX9 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,MUX8 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,MUX7 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,MUX6 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,MUX5 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,MUX4 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,MUX3 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,MUX2 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,MUX1 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive AUXSIG7 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x38)++0x03
|
|
line.long 0x00 "AUXSIGOUTINV,CLB XBAR Output Inversion Register"
|
|
bitfld.long 0x00 7. " OUT7 ,Selects polarity for AUXSIG7 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUT6 ,Selects polarity for AUXSIG6 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUT5 ,Selects polarity for AUXSIG5 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUT4 ,Selects polarity for AUXSIG4 of CLB-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUT3 ,Selects polarity for AUXSIG3 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUT2 ,Selects polarity for AUXSIG2 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUT1 ,Selects polarity for AUXSIG1 of CLB-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUT0 ,Selects polarity for AUXSIG0 of CLB-XBAR" "0,1"
|
|
group.long (d:0x00007A40+0x3E)++0x03
|
|
line.long 0x00 "AUXSIGLOCK,ClbXbar Configuration Lock register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Write Protection KEY"
|
|
bitfld.long 0x00 0. " LOCK ,Locks the configuration for CLB-XBAR" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "EPwmXbarRegs"
|
|
width 20.
|
|
group.long (d:0x00007A00+0x00)++0x03
|
|
line.long 0x00 "TRIP4MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP4"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x02)++0x03
|
|
line.long 0x00 "TRIP4MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP4"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP4 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x04)++0x03
|
|
line.long 0x00 "TRIP5MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP5"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x06)++0x03
|
|
line.long 0x00 "TRIP5MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP5"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP5 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x08)++0x03
|
|
line.long 0x00 "TRIP7MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP7"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x0A)++0x03
|
|
line.long 0x00 "TRIP7MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP7"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP7 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x0C)++0x03
|
|
line.long 0x00 "TRIP8MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP8"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x0E)++0x03
|
|
line.long 0x00 "TRIP8MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP8"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP8 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x10)++0x03
|
|
line.long 0x00 "TRIP9MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP9"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x12)++0x03
|
|
line.long 0x00 "TRIP9MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP9"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP9 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x14)++0x03
|
|
line.long 0x00 "TRIP10MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP10"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x16)++0x03
|
|
line.long 0x00 "TRIP10MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP10"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP10 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x18)++0x03
|
|
line.long 0x00 "TRIP11MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP11"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x1A)++0x03
|
|
line.long 0x00 "TRIP11MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP11"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP11 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x1C)++0x03
|
|
line.long 0x00 "TRIP12MUX0TO15CFG,ePWM XBAR Mux Configuration for TRIP12"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x1E)++0x03
|
|
line.long 0x00 "TRIP12MUX16TO31CFG,ePWM XBAR Mux Configuration for TRIP12"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for TRIP12 of EPWM-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A00+0x20)++0x03
|
|
line.long 0x00 "TRIP4MUXENABLE,ePWM XBAR Mux Enable for TRIP4"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP4 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x22)++0x03
|
|
line.long 0x00 "TRIP5MUXENABLE,ePWM XBAR Mux Enable for TRIP5"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP5 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x24)++0x03
|
|
line.long 0x00 "TRIP7MUXENABLE,ePWM XBAR Mux Enable for TRIP7"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP7 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x26)++0x03
|
|
line.long 0x00 "TRIP8MUXENABLE,ePWM XBAR Mux Enable for TRIP8"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP8 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x28)++0x03
|
|
line.long 0x00 "TRIP9MUXENABLE,ePWM XBAR Mux Enable for TRIP9"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP9 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x2A)++0x03
|
|
line.long 0x00 "TRIP10MUXENABLE,ePWM XBAR Mux Enable for TRIP10"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP10 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x2C)++0x03
|
|
line.long 0x00 "TRIP11MUXENABLE,ePWM XBAR Mux Enable for TRIP11"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP11 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x2E)++0x03
|
|
line.long 0x00 "TRIP12MUXENABLE,ePWM XBAR Mux Enable for TRIP12"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,mux0 to drive TRIP12 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x38)++0x03
|
|
line.long 0x00 "TRIPOUTINV,ePWM XBAR Output Inversion Register"
|
|
bitfld.long 0x00 7. " TRIP12 ,Selects polarity for TRIP12 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " TRIP11 ,Selects polarity for TRIP11 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " TRIP10 ,Selects polarity for TRIP10 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " TRIP9 ,Selects polarity for TRIP9 of EPWM-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TRIP8 ,Selects polarity for TRIP8 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " TRIP7 ,Selects polarity for TRIP7 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " TRIP5 ,Selects polarity for TRIP5 of EPWM-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " TRIP4 ,Selects polarity for TRIP4 of EPWM-XBAR" "0,1"
|
|
group.long (d:0x00007A00+0x3E)++0x03
|
|
line.long 0x00 "TRIPLOCK,ePWM XBAR Configuration Lock register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Write protection KEY"
|
|
bitfld.long 0x00 0. " LOCK ,Locks the configuration for EPWM-XBAR" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "InputXbar1Regs"
|
|
width 17.
|
|
group.word (d:0x00007900+0x00)++0x01
|
|
line.word 0x00 "INPUT1SELECT,INPUT1 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x01)++0x01
|
|
line.word 0x00 "INPUT2SELECT,INPUT2 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x02)++0x01
|
|
line.word 0x00 "INPUT3SELECT,INPUT3 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x03)++0x01
|
|
line.word 0x00 "INPUT4SELECT,INPUT4 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x04)++0x01
|
|
line.word 0x00 "INPUT5SELECT,INPUT5 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x05)++0x01
|
|
line.word 0x00 "INPUT6SELECT,INPUT6 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x06)++0x01
|
|
line.word 0x00 "INPUT7SELECT,INPUT7 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x07)++0x01
|
|
line.word 0x00 "INPUT8SELECT,INPUT8 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x08)++0x01
|
|
line.word 0x00 "INPUT9SELECT,INPUT9 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x09)++0x01
|
|
line.word 0x00 "INPUT10SELECT,INPUT10 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0A)++0x01
|
|
line.word 0x00 "INPUT11SELECT,INPUT11 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0B)++0x01
|
|
line.word 0x00 "INPUT12SELECT,INPUT12 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0C)++0x01
|
|
line.word 0x00 "INPUT13SELECT,INPUT13 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0D)++0x01
|
|
line.word 0x00 "INPUT14SELECT,INPUT14 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0E)++0x01
|
|
line.word 0x00 "INPUT15SELECT,INPUT15 Input Select Register (GPIO0 to x)"
|
|
group.word (d:0x00007900+0x0F)++0x01
|
|
line.word 0x00 "INPUT16SELECT,INPUT16 Input Select Register (GPIO0 to x)"
|
|
group.long (d:0x00007900+0x1E)++0x03
|
|
line.long 0x00 "INPUTSELECTLOCK,Input Select Lock Register"
|
|
bitfld.long 0x00 15. " INPUT16SELECT ,Lock bit for INPUT16SELECT Register" "0,1"
|
|
bitfld.long 0x00 14. " INPUT15SELECT ,Lock bit for INPUT15SELECT Register" "0,1"
|
|
bitfld.long 0x00 13. " INPUT14SELECT ,Lock bit for INPUT14SELECT Register" "0,1"
|
|
bitfld.long 0x00 12. " INPUT13SELECT ,Lock bit for INPUT13SELECT Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " INPUT12SELECT ,Lock bit for INPUT12SELECT Register" "0,1"
|
|
bitfld.long 0x00 10. " INPUT11SELECT ,Lock bit for INPUT11SELECT Register" "0,1"
|
|
bitfld.long 0x00 9. " INPUT10SELECT ,Lock bit for INPUT10SELECT Register" "0,1"
|
|
bitfld.long 0x00 8. " INPUT9SELECT ,Lock bit for INPUT9SELECT Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " INPUT8SELECT ,Lock bit for INPUT8SELECT Register" "0,1"
|
|
bitfld.long 0x00 6. " INPUT7SELECT ,Lock bit for INPUT7SELECT Register" "0,1"
|
|
bitfld.long 0x00 5. " INPUT6SELECT ,Lock bit for INPUT6SELECT Register" "0,1"
|
|
bitfld.long 0x00 4. " INPUT5SELECT ,Lock bit for INPUT5SELECT Register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INPUT4SELECT ,Lock bit for INPUT4SELECT Register" "0,1"
|
|
bitfld.long 0x00 2. " INPUT3SELECT ,Lock bit for INPUT3SELECT Register" "0,1"
|
|
bitfld.long 0x00 1. " INPUT2SELECT ,Lock bit for INPUT2SELECT Register" "0,1"
|
|
bitfld.long 0x00 0. " INPUT1SELECT ,Lock bit for INPUT1SELECT Register" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "OutputXbar1Regs"
|
|
width 21.
|
|
group.long (d:0x00007A80+0x00)++0x03
|
|
line.long 0x00 "OUTPUT1MUX0TO15CFG,Output X-BAR Mux Configuration for Output 1"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x02)++0x03
|
|
line.long 0x00 "OUTPUT1MUX16TO31CFG,Output X-BAR Mux Configuration for Output 1"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x04)++0x03
|
|
line.long 0x00 "OUTPUT2MUX0TO15CFG,Output X-BAR Mux Configuration for Output 2"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x06)++0x03
|
|
line.long 0x00 "OUTPUT2MUX16TO31CFG,Output X-BAR Mux Configuration for Output 2"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x08)++0x03
|
|
line.long 0x00 "OUTPUT3MUX0TO15CFG,Output X-BAR Mux Configuration for Output 3"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x0A)++0x03
|
|
line.long 0x00 "OUTPUT3MUX16TO31CFG,Output X-BAR Mux Configuration for Output 3"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x0C)++0x03
|
|
line.long 0x00 "OUTPUT4MUX0TO15CFG,Output X-BAR Mux Configuration for Output 4"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x0E)++0x03
|
|
line.long 0x00 "OUTPUT4MUX16TO31CFG,Output X-BAR Mux Configuration for Output 4"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x10)++0x03
|
|
line.long 0x00 "OUTPUT5MUX0TO15CFG,Output X-BAR Mux Configuration for Output 5"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x12)++0x03
|
|
line.long 0x00 "OUTPUT5MUX16TO31CFG,Output X-BAR Mux Configuration for Output 5"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x14)++0x03
|
|
line.long 0x00 "OUTPUT6MUX0TO15CFG,Output X-BAR Mux Configuration for Output 6"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x16)++0x03
|
|
line.long 0x00 "OUTPUT6MUX16TO31CFG,Output X-BAR Mux Configuration for Output 6"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x18)++0x03
|
|
line.long 0x00 "OUTPUT7MUX0TO15CFG,Output X-BAR Mux Configuration for Output 7"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x1A)++0x03
|
|
line.long 0x00 "OUTPUT7MUX16TO31CFG,Output X-BAR Mux Configuration for Output 7"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x1C)++0x03
|
|
line.long 0x00 "OUTPUT8MUX0TO15CFG,Output X-BAR Mux Configuration for Output 8"
|
|
bitfld.long 0x00 30.--31. " MUX15 ,Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX14 ,Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX13 ,Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX12 ,Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX11 ,Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX10 ,Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX9 ,Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX8 ,Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX7 ,Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX6 ,Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX5 ,Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX4 ,Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX3 ,Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX2 ,Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX1 ,Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX0 ,Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x1E)++0x03
|
|
line.long 0x00 "OUTPUT8MUX16TO31CFG,Output X-BAR Mux Configuration for Output 8"
|
|
bitfld.long 0x00 30.--31. " MUX31 ,Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " MUX30 ,Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " MUX29 ,Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " MUX28 ,Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " MUX27 ,Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " MUX26 ,Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " MUX25 ,Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " MUX24 ,Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " MUX23 ,Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " MUX22 ,Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " MUX21 ,Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " MUX20 ,Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " MUX19 ,Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " MUX18 ,Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " MUX17 ,Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " MUX16 ,Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR" "0,1,2,3"
|
|
group.long (d:0x00007A80+0x20)++0x03
|
|
line.long 0x00 "OUTPUT1MUXENABLE,Output X-BAR Mux Enable for Output 1"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x22)++0x03
|
|
line.long 0x00 "OUTPUT2MUXENABLE,Output X-BAR Mux Enable for Output 2"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x24)++0x03
|
|
line.long 0x00 "OUTPUT3MUXENABLE,Output X-BAR Mux Enable for Output 3"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x26)++0x03
|
|
line.long 0x00 "OUTPUT4MUXENABLE,Output X-BAR Mux Enable for Output 4"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x28)++0x03
|
|
line.long 0x00 "OUTPUT5MUXENABLE,Output X-BAR Mux Enable for Output 5"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x2A)++0x03
|
|
line.long 0x00 "OUTPUT6MUXENABLE,Output X-BAR Mux Enable for Output 6"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x2C)++0x03
|
|
line.long 0x00 "OUTPUT7MUXENABLE,Output X-BAR Mux Enable for Output 7"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x2E)++0x03
|
|
line.long 0x00 "OUTPUT8MUXENABLE,Output X-BAR Mux Enable for Output 8"
|
|
bitfld.long 0x00 31. " MUX31 ,Mux31 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 30. " MUX30 ,Mux30 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 29. " MUX29 ,Mux29 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 28. " MUX28 ,Mux28 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " MUX27 ,Mux27 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 26. " MUX26 ,Mux26 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 25. " MUX25 ,Mux25 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 24. " MUX24 ,Mux24 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " MUX23 ,Mux23 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 22. " MUX22 ,Mux22 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 21. " MUX21 ,Mux21 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 20. " MUX20 ,Mux20 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " MUX19 ,Mux19 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 18. " MUX18 ,Mux18 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 17. " MUX17 ,Mux17 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 16. " MUX16 ,Mux16 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " MUX15 ,Mux15 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 14. " MUX14 ,Mux14 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 13. " MUX13 ,Mux13 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 12. " MUX12 ,Mux12 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MUX11 ,Mux11 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 10. " MUX10 ,Mux10 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 9. " MUX9 ,Mux9 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 8. " MUX8 ,Mux8 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MUX7 ,Mux7 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " MUX6 ,Mux6 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " MUX5 ,Mux5 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " MUX4 ,Mux4 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " MUX3 ,Mux3 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " MUX2 ,Mux2 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " MUX1 ,Mux1 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " MUX0 ,Mux0 to drive OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
rgroup.long (d:0x00007A80+0x30)++0x03
|
|
line.long 0x00 "OUTPUTLATCH,Output X-BAR Output Latch"
|
|
bitfld.long 0x00 7. " OUTPUT8 ,Records the OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUTPUT7 ,Records the OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUTPUT6 ,Records the OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUTPUT5 ,Records the OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUTPUT4 ,Records the OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUTPUT3 ,Records the OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUTPUT2 ,Records the OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUTPUT1 ,Records the OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x32)++0x03
|
|
line.long 0x00 "OUTPUTLATCHCLR,Output X-BAR Output Latch Clear"
|
|
bitfld.long 0x00 7. " OUTPUT8 ,Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUTPUT7 ,Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUTPUT6 ,Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUTPUT5 ,Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUTPUT4 ,Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUTPUT3 ,Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUTPUT2 ,Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUTPUT1 ,Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x34)++0x03
|
|
line.long 0x00 "OUTPUTLATCHFRC,Output X-BAR Output Latch Clear"
|
|
bitfld.long 0x00 7. " OUTPUT8 ,Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUTPUT7 ,Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUTPUT6 ,Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUTPUT5 ,Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUTPUT4 ,Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUTPUT3 ,Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUTPUT2 ,Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUTPUT1 ,Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x36)++0x03
|
|
line.long 0x00 "OUTPUTLATCHENABLE,Output X-BAR Output Latch Enable"
|
|
bitfld.long 0x00 7. " OUTPUT8 ,Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUTPUT7 ,Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUTPUT6 ,Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUTPUT5 ,Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUTPUT4 ,Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUTPUT3 ,Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUTPUT2 ,Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUTPUT1 ,Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x38)++0x03
|
|
line.long 0x00 "OUTPUTINV,Output X-BAR Output Inversion"
|
|
bitfld.long 0x00 7. " OUTPUT8 ,Selects polarity for OUTPUT8 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 6. " OUTPUT7 ,Selects polarity for OUTPUT7 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 5. " OUTPUT6 ,Selects polarity for OUTPUT6 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 4. " OUTPUT5 ,Selects polarity for OUTPUT5 of OUTPUT-XBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OUTPUT4 ,Selects polarity for OUTPUT4 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 2. " OUTPUT3 ,Selects polarity for OUTPUT3 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 1. " OUTPUT2 ,Selects polarity for OUTPUT2 of OUTPUT-XBAR" "0,1"
|
|
bitfld.long 0x00 0. " OUTPUT1 ,Selects polarity for OUTPUT1 of OUTPUT-XBAR" "0,1"
|
|
group.long (d:0x00007A80+0x3E)++0x03
|
|
line.long 0x00 "OUTPUTLOCK,Output X-BAR Configuration Lock register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Write Protection KEY"
|
|
bitfld.long 0x00 0. " LOCK ,Locks the configuration for OUTPUT-XBAR" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "XbarRegs"
|
|
width 10.
|
|
rgroup.long (d:0x00007920+0x00)++0x03
|
|
line.long 0x00 "XBARFLG1,X-Bar Input Flag Register 1"
|
|
bitfld.long 0x00 31. " CMPSS8_CTRIPOUTH ,Input Flag for CMPSS8.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 30. " CMPSS8_CTRIPOUTL ,Input Flag for CMPSS8.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 29. " CMPSS7_CTRIPOUTH ,Input Flag for CMPSS7.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 28. " CMPSS7_CTRIPOUTL ,Input Flag for CMPSS7.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CMPSS6_CTRIPOUTH ,Input Flag for CMPSS6.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 26. " CMPSS6_CTRIPOUTL ,Input Flag for CMPSS6.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 25. " CMPSS5_CTRIPOUTH ,Input Flag for CMPSS5.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 24. " CMPSS5_CTRIPOUTL ,Input Flag for CMPSS5.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CMPSS4_CTRIPOUTH ,Input Flag for CMPSS4.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 22. " CMPSS4_CTRIPOUTL ,Input Flag for CMPSS4.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 21. " CMPSS3_CTRIPOUTH ,Input Flag for CMPSS3.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 20. " CMPSS3_CTRIPOUTL ,Input Flag for CMPSS3.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CMPSS2_CTRIPOUTH ,Input Flag for CMPSS2.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 18. " CMPSS2_CTRIPOUTL ,Input Flag for CMPSS2.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 17. " CMPSS1_CTRIPOUTH ,Input Flag for CMPSS1.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 16. " CMPSS1_CTRIPOUTL ,Input Flag for CMPSS1.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CMPSS8_CTRIPH ,Input Flag for CMPSS8.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 14. " CMPSS8_CTRIPL ,Input Flag for CMPSS8.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 13. " CMPSS7_CTRIPH ,Input Flag for CMPSS7.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 12. " CMPSS7_CTRIPL ,Input Flag for CMPSS7.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CMPSS6_CTRIPH ,Input Flag for CMPSS6.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 10. " CMPSS6_CTRIPL ,Input Flag for CMPSS6.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 9. " CMPSS5_CTRIPH ,Input Flag for CMPSS5.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 8. " CMPSS5_CTRIPL ,Input Flag for CMPSS5.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CMPSS4_CTRIPH ,Input Flag for CMPSS4.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 6. " CMPSS4_CTRIPL ,Input Flag for CMPSS4.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 5. " CMPSS3_CTRIPH ,Input Flag for CMPSS3.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 4. " CMPSS3_CTRIPL ,Input Flag for CMPSS3.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CMPSS2_CTRIPH ,Input Flag for CMPSS2.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 2. " CMPSS2_CTRIPL ,Input Flag for CMPSS2.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 1. " CMPSS1_CTRIPH ,Input Flag for CMPSS1.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 0. " CMPSS1_CTRIPL ,Input Flag for CMPSS1.CTRIPL Signal" "0,1"
|
|
rgroup.long (d:0x00007920+0x02)++0x03
|
|
line.long 0x00 "XBARFLG2,X-Bar Input Flag Register 2"
|
|
bitfld.long 0x00 31. " ADCCEVT1 ,Input Flag for ADCCEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 30. " ADCBEVT4 ,Input Flag for ADCBEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 29. " ADCBEVT3 ,Input Flag for ADCBEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 28. " ADCBEVT2 ,Input Flag for ADCBEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ADCBEVT1 ,Input Flag for ADCBEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 26. " ADCAEVT4 ,Input Flag for ADCAEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 25. " ADCAEVT3 ,Input Flag for ADCAEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 24. " ADCAEVT2 ,Input Flag for ADCAEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ADCAEVT1 ,Input Flag for ADCAEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 22. " EXTSYNCOUT ,Input Flag for EXTSYNCOUT Signal" "0,1"
|
|
bitfld.long 0x00 21. " ECAP6_OUT ,Input Flag for ECAP6.OUT Signal" "0,1"
|
|
bitfld.long 0x00 20. " ECAP5_OUT ,Input Flag for ECAP5.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ECAP4_OUT ,Input Flag for ECAP4.OUT Signal" "0,1"
|
|
bitfld.long 0x00 18. " ECAP3_OUT ,Input Flag for ECAP3.OUT Signal" "0,1"
|
|
bitfld.long 0x00 17. " ECAP2_OUT ,Input Flag for ECAP2.OUT Signal" "0,1"
|
|
bitfld.long 0x00 16. " ECAP1_OUT ,Input Flag for ECAP1.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " INPUT14 ,Input Flag for INPUT14 Signal" "0,1"
|
|
bitfld.long 0x00 14. " INPUT13 ,Input Flag for INPUT13 Signal" "0,1"
|
|
bitfld.long 0x00 13. " INPUT12 ,Input Flag for INPUT12 Signal" "0,1"
|
|
bitfld.long 0x00 12. " INPUT11 ,Input Flag for INPUT11 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " INPUT10 ,Input Flag for INPUT10\ Signal" "0,1"
|
|
bitfld.long 0x00 10. " INPUT9 ,Input Flag for INPUT9 Signal" "0,1"
|
|
bitfld.long 0x00 9. " INPUT8 ,Input Flag for INPUT8 Signal" "0,1"
|
|
bitfld.long 0x00 8. " INPUT7 ,Input Flag for INPUT7 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ADCSOCB ,Input Flag for ADCSOCB Signal" "0,1"
|
|
bitfld.long 0x00 6. " ADCSOCA ,Input Flag for ADCSOCA Signal" "0,1"
|
|
bitfld.long 0x00 5. " INPUT6 ,Input Flag for INPUT6 Signal" "0,1"
|
|
bitfld.long 0x00 4. " INPUT5 ,Input Flag for INPUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INPUT4 ,Input Flag for INPUT4 Signal" "0,1"
|
|
bitfld.long 0x00 2. " INPUT3 ,Input Flag for INPUT3 Signal" "0,1"
|
|
bitfld.long 0x00 1. " INPUT2 ,Input Flag for INPUT2 Signal" "0,1"
|
|
bitfld.long 0x00 0. " INPUT1 ,Input Flag for INPUT1 Signal" "0,1"
|
|
rgroup.long (d:0x00007920+0x04)++0x03
|
|
line.long 0x00 "XBARFLG3,X-Bar Input Flag Register 3"
|
|
bitfld.long 0x00 31. " SD1FLT4_DRINT ,Input Flag for SD1FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 30. " SD1FLT4_COMPZ ,Input Flag for SD1FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 29. " SD1FLT3_DRINT ,Input Flag for SD1FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 28. " SD1FLT3_COMPZ ,Input Flag for SD1FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SD1FLT2_DRINT ,Input Flag for SD1FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 26. " SD1FLT2_COMPZ ,Input Flag for SD1FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 25. " SD1FLT1_DRINT ,Input Flag for SD1FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 24. " SD1FLT1_COMPZ ,Input Flag for SD1FLT1.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ECAP7_OUT ,Input Flag for ECAP7.OUT Signal" "0,1"
|
|
bitfld.long 0x00 22. " SD2FLT4_COMPH ,Input Flag for SD2FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 21. " SD2FLT4_COMPL ,Input Flag for SD2FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 20. " SD2FLT3_COMPH ,Input Flag for SD2FLT3.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SD2FLT3_COMPL ,Input Flag for SD2FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 18. " SD2FLT2_COMPH ,Input Flag for SD2FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 17. " SD2FLT2_COMPL ,Input Flag for SD2FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 16. " SD2FLT1_COMPH ,Input Flag for SD2FLT1.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SD2FLT1_COMPL ,Input Flag for SD2FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 14. " SD1FLT4_COMPH ,Input Flag for SD1FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 13. " SD1FLT4_COMPL ,Input Flag for SD1FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 12. " SD1FLT3_COMPH ,Input Flag for SD1FLT3.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SD1FLT3_COMPL ,Input Flag for SD1FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 10. " SD1FLT2_COMPH ,Input Flag for SD1FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 9. " SD1FLT2_COMPL ,Input Flag for SD1FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 8. " SD1FLT1_COMPH ,Input Flag for SD1FLT1.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SD1FLT1_COMPL ,Input Flag for SD1FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 6. " ADCDEVT4 ,Input Flag for ADCDEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 5. " ADCDEVT3 ,Input Flag for ADCDEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 4. " ADCDEVT2 ,Input Flag for ADCDEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ADCDEVT1 ,Input Flag for ADCDEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 2. " ADCCEVT4 ,Input Flag for ADCCEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 1. " ADCCEVT3 ,Input Flag for ADCCEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 0. " ADCCEVT2 ,Input Flag for ADCCEVT2 Signal" "0,1"
|
|
rgroup.long (d:0x00007920+0x06)++0x03
|
|
line.long 0x00 "XBARFLG4,X-Bar Input Flag Register 4"
|
|
bitfld.long 0x00 31. " CLAHALT ,Input Latch for CLAHALT Signal" "0,1"
|
|
bitfld.long 0x00 30. " ECATSYNC1 ,Input Latch for ECATSYNC1 Signal" "0,1"
|
|
bitfld.long 0x00 29. " ECATSYNC0 ,Input Latch for ECATSYNC0 Signal" "0,1"
|
|
bitfld.long 0x00 28. " ERRORSTS_ERROR ,Input Latch for ERRORSTS_ERROR Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLB6_OUT5 ,Input Latch for CLB6_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 26. " CLB6_OUT4 ,Input Latch for CLB6_OUT4 Signal" "0,1"
|
|
bitfld.long 0x00 25. " CLB5_OUT5 ,Input Latch for CLB5_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 24. " CLB5_OUT4 ,Input Latch for CLB5_OUT4 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLB4_OUT5 ,Input Flag for CLB4_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 22. " CLB4_OUT4 ,Input Flag for CLB4_4.1 Signal" "0,1"
|
|
bitfld.long 0x00 21. " CLB3_OUT5 ,Input Flag for CLB3_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 20. " CLB3_OUT4 ,Input Flag for CLB3_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLB2_OUT5 ,Input Flag for CLB2_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 18. " CLB2_OUT4 ,Input Flag for CLB2_4.1 Signal" "0,1"
|
|
bitfld.long 0x00 17. " CLB1_OUT5 ,Input Flag for CLB1_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 16. " CLB1_OUT4 ,Input Flag for CLB1_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLB8_OUT5 ,Input Flag for CLB8_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 14. " CLB8_OUT4 ,Input Flag for CLB8_4.1 Signal" "0,1"
|
|
bitfld.long 0x00 13. " CLB7_OUT5 ,Input Flag for CLB7_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 12. " CLB7_OUT4 ,Input Flag for CLB7_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MCANA_FEVT2 ,Input Flag for MCANA_FEVT2 Signal" "0,1"
|
|
bitfld.long 0x00 10. " MCANA_FEVT1 ,Input Flag for MCANA_FEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 9. " MCANA_FEVT0 ,Input Flag for MCANA_FEVT0 Signal" "0,1"
|
|
bitfld.long 0x00 8. " EMAC_PPS0 ,Input Flag for EMAC_PPS0 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SD2FLT4_DRINT ,Input Flag for SD2FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 6. " SD2FLT4_COMPZ ,Input Flag for SD2FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 5. " SD2FLT3_DRINT ,Input Flag for SD2FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 4. " SD2FLT3_COMPZ ,Input Flag for SD2FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SD2FLT2_DRINT ,Input Flag for SD2FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 2. " SD2FLT2_COMPZ ,Input Flag for SD2FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 1. " SD2FLT1_DRINT ,Input Flag for SD2FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 0. " SD2FLT1_COMPZ ,Input Flag for SD2FLT1.COMPZ Signal" "0,1"
|
|
group.long (d:0x00007920+0x08)++0x03
|
|
line.long 0x00 "XBARCLR1,X-Bar Input Flag Clear Register 1"
|
|
bitfld.long 0x00 31. " CMPSS8_CTRIPOUTH ,Input Flag Clear for CMPSS8.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 30. " CMPSS8_CTRIPOUTL ,Input Flag Clear for CMPSS8.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 29. " CMPSS7_CTRIPOUTH ,Input Flag Clear for CMPSS7.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 28. " CMPSS7_CTRIPOUTL ,Input Flag Clear for CMPSS7.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CMPSS6_CTRIPOUTH ,Input Flag Clear for CMPSS6.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 26. " CMPSS6_CTRIPOUTL ,Input Flag Clear for CMPSS6.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 25. " CMPSS5_CTRIPOUTH ,Input Flag Clear for CMPSS5.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 24. " CMPSS5_CTRIPOUTL ,Input Flag Clear for CMPSS5.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CMPSS4_CTRIPOUTH ,Input Flag Clear for CMPSS4.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 22. " CMPSS4_CTRIPOUTL ,Input Flag Clear for CMPSS4.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 21. " CMPSS3_CTRIPOUTH ,Input Flag Clear for CMPSS3.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 20. " CMPSS3_CTRIPOUTL ,Input Flag Clear for CMPSS3.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CMPSS2_CTRIPOUTH ,Input Flag Clear for CMPSS2.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 18. " CMPSS2_CTRIPOUTL ,Input Flag Clear for CMPSS2.CTRIPOUTL Signal" "0,1"
|
|
bitfld.long 0x00 17. " CMPSS1_CTRIPOUTH ,Input Flag Clear for CMPSS1.CTRIPOUTH Signal" "0,1"
|
|
bitfld.long 0x00 16. " CMPSS1_CTRIPOUTL ,Input Flag Clear for CMPSS1.CTRIPOUTL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CMPSS8_CTRIPH ,Input Flag Clear for CMPSS8.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 14. " CMPSS8_CTRIPL ,Input Flag Clear for CMPSS8.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 13. " CMPSS7_CTRIPH ,Input Flag Clear for CMPSS7.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 12. " CMPSS7_CTRIPL ,Input Flag Clear for CMPSS7.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CMPSS6_CTRIPH ,Input Flag Clear for CMPSS6.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 10. " CMPSS6_CTRIPL ,Input Flag Clear for CMPSS6.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 9. " CMPSS5_CTRIPH ,Input Flag Clear for CMPSS5.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 8. " CMPSS5_CTRIPL ,Input Flag Clear for CMPSS5.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CMPSS4_CTRIPH ,Input Flag Clear for CMPSS4.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 6. " CMPSS4_CTRIPL ,Input Flag Clear for CMPSS4.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 5. " CMPSS3_CTRIPH ,Input Flag Clear for CMPSS3.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 4. " CMPSS3_CTRIPL ,Input Flag Clear for CMPSS3.CTRIPL Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CMPSS2_CTRIPH ,Input Flag Clear for CMPSS2.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 2. " CMPSS2_CTRIPL ,Input Flag Clear for CMPSS2.CTRIPL Signal" "0,1"
|
|
bitfld.long 0x00 1. " CMPSS1_CTRIPH ,Input Flag Clear for CMPSS1.CTRIPH Signal" "0,1"
|
|
bitfld.long 0x00 0. " CMPSS1_CTRIPL ,Input Flag Clear for CMPSS1.CTRIPL Signal" "0,1"
|
|
group.long (d:0x00007920+0x0A)++0x03
|
|
line.long 0x00 "XBARCLR2,X-Bar Input Flag Clear Register 2"
|
|
bitfld.long 0x00 31. " ADCCEVT1 ,Input Flag Clear for ADCCEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 30. " ADCBEVT4 ,Input Flag Clear for ADCBEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 29. " ADCBEVT3 ,Input Flag Clear for ADCBEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 28. " ADCBEVT2 ,Input Flag Clear for ADCBEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ADCBEVT1 ,Input Flag Clear for ADCBEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 26. " ADCAEVT4 ,Input Flag Clear for ADCAEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 25. " ADCAEVT3 ,Input Flag Clear for ADCAEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 24. " ADCAEVT2 ,Input Flag Clear for ADCAEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ADCAEVT1 ,Input Flag Clear for ADCAEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 22. " EXTSYNCOUT ,Input Flag Clear for EXTSYNCOUT Signal" "0,1"
|
|
bitfld.long 0x00 21. " ECAP6_OUT ,Input Flag Clear for ECAP6.OUT Signal" "0,1"
|
|
bitfld.long 0x00 20. " ECAP5_OUT ,Input Flag Clear for ECAP5.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ECAP4_OUT ,Input Flag Clear for ECAP4.OUT Signal" "0,1"
|
|
bitfld.long 0x00 18. " ECAP3_OUT ,Input Flag Clear for ECAP3.OUT Signal" "0,1"
|
|
bitfld.long 0x00 17. " ECAP2_OUT ,Input Flag Clear for ECAP2.OUT Signal" "0,1"
|
|
bitfld.long 0x00 16. " ECAP1_OUT ,Input Flag Clear for ECAP1.OUT Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " INPUT14 ,Input Flag Clear for INPUT14 Signal" "0,1"
|
|
bitfld.long 0x00 14. " INPUT13 ,Input Flag Clear for INPUT13 Signal" "0,1"
|
|
bitfld.long 0x00 13. " INPUT12 ,Input Flag Clear for INPUT12 Signal" "0,1"
|
|
bitfld.long 0x00 12. " INPUT11 ,Input Flag Clear for INPUT11 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " INPUT10 ,Input Flag Clear for INPUT10 Signal" "0,1"
|
|
bitfld.long 0x00 10. " INPUT9 ,Input Flag Clear for INPUT9 Signal" "0,1"
|
|
bitfld.long 0x00 9. " INPUT8 ,Input Flag Clear for INPUT8 Signal" "0,1"
|
|
bitfld.long 0x00 8. " INPUT7 ,Input Flag Clear for INPUT7 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ADCSOCB ,Input Flag Clear for ADCSOCB Signal" "0,1"
|
|
bitfld.long 0x00 6. " ADCSOCA ,Input Flag Clear for ADCSOCA Signal" "0,1"
|
|
bitfld.long 0x00 5. " INPUT6 ,Input Flag Clear for INPUT6 Signal" "0,1"
|
|
bitfld.long 0x00 4. " INPUT5 ,Input Flag Clear for INPUT5 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " INPUT4 ,Input Flag Clear for INPUT4 Signal" "0,1"
|
|
bitfld.long 0x00 2. " INPUT3 ,Input Flag Clear for INPUT3 Signal" "0,1"
|
|
bitfld.long 0x00 1. " INPUT2 ,Input Flag Clear for INPUT2 Signal" "0,1"
|
|
bitfld.long 0x00 0. " INPUT1 ,Input Flag Clear for INPUT1 Signal" "0,1"
|
|
group.long (d:0x00007920+0x0C)++0x03
|
|
line.long 0x00 "XBARCLR3,X-Bar Input Flag Clear Register 3"
|
|
bitfld.long 0x00 31. " SD1FLT4_DRINT ,Input Flag clear for SD1FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 30. " SD1FLT4_COMPZ ,Input Flag clear for SD1FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 29. " SD1FLT3_DRINT ,Input Flag clear for SD1FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 28. " SD1FLT3_COMPZ ,Input Flag clear for SD1FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SD1FLT2_DRINT ,Input Flag clear for SD1FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 26. " SD1FLT2_COMPZ ,Input Flag clear for SD1FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 25. " SD1FLT1_DRINT ,Input Flag clear for SD1FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 24. " SD1FLT1_COMPZ ,Input Flag clear for SD1FLT1.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ECAP7_OUT ,Input Flag clear for ECAP7.OUT Signal" "0,1"
|
|
bitfld.long 0x00 22. " SD2FLT4_COMPH ,Input Flag Clear for SD2FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 21. " SD2FLT4_COMPL ,Input Flag Clear for SD2FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 20. " SD2FLT3_COMPH ,Input Flag Clear for SD2FLT3.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SD2FLT3_COMPL ,Input Flag Clear for SD2FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 18. " SD2FLT2_COMPH ,Input Flag Clear for SD2FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 17. " SD2FLT2_COMPL ,Input Flag Clear for SD2FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 16. " SD2FLT1_COMPH ,Input Flag Clear for SD2FLT1.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SD2FLT1_COMPL ,Input Flag Clear for SD2FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 14. " SD1FLT4_COMPH ,Input Flag Clear for SD1FLT4.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 13. " SD1FLT4_COMPL ,Input Flag Clear for SD1FLT4.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 12. " SD1FLT3_COMPH ,Input Flag Clear for SD1FLT3.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SD1FLT3_COMPL ,Input Flag Clear for SD1FLT3.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 10. " SD1FLT2_COMPH ,Input Flag Clear for SD1FLT2.COMPH Signal" "0,1"
|
|
bitfld.long 0x00 9. " SD1FLT2_COMPL ,Input Flag Clear for SD1FLT2.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 8. " SD1FLT1_COMPH ,Input Flag Clear for SD1FLT1.COMPH Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SD1FLT1_COMPL ,Input Flag Clear for SD1FLT1.COMPL Signal" "0,1"
|
|
bitfld.long 0x00 6. " ADCDEVT4 ,Input Flag Clear for ADCDEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 5. " ADCDEVT3 ,Input Flag Clear for ADCDEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 4. " ADCDEVT2 ,Input Flag Clear for ADCDEVT2 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ADCDEVT1 ,Input Flag Clear for ADCDEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 2. " ADCCEVT4 ,Input Flag Clear for ADCCEVT4 Signal" "0,1"
|
|
bitfld.long 0x00 1. " ADCCEVT3 ,Input Flag Clear for ADCCEVT3 Signal" "0,1"
|
|
bitfld.long 0x00 0. " ADCCEVT2 ,Input Flag Clear for ADCCEVT2 Signal" "0,1"
|
|
group.long (d:0x00007920+0x0E)++0x03
|
|
line.long 0x00 "XBARCLR4,X-Bar Input Flag Clear Register 4"
|
|
rbitfld.long 0x00 31. " CLAHALT ,Input Flag clear for CLAHALT Signal" "0,1"
|
|
bitfld.long 0x00 30. " ECATSYNC1 ,Input Latch clear for ECATSYNC1 Signal" "0,1"
|
|
bitfld.long 0x00 29. " ECATSYNC0 ,Input Latch clear for ECATSYNC0 Signal" "0,1"
|
|
bitfld.long 0x00 28. " ERRORSTS_ERROR ,Input Latch clear for ERRORSTS_ERROR Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLB6_OUT5 ,Input Latch clear for CLB6_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 26. " CLB6_OUT4 ,Input Latch clear for CLB6_OUT4 Signal" "0,1"
|
|
bitfld.long 0x00 25. " CLB5_OUT5 ,Input Latch clear for CLB5_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 24. " CLB5_OUT4 ,Input Latch clear for CLB5_OUT4 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLB4_OUT5 ,Input Flag clear for CLB4_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 22. " CLB4_OUT4 ,Input Flag clear for CLB4_4.1 Signal" "0,1"
|
|
bitfld.long 0x00 21. " CLB3_OUT5 ,Input Flag clear for CLB3_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 20. " CLB3_OUT4 ,Input Flag clear for CLB3_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLB2_OUT5 ,Input Flag clear for CLB2_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 18. " CLB2_OUT4 ,Input Flag clear for CLB2_4.1 Signal" "0,1"
|
|
bitfld.long 0x00 17. " CLB1_OUT5 ,Input Flag clear for CLB1_5.1 Signal" "0,1"
|
|
bitfld.long 0x00 16. " CLB1_OUT4 ,Input Flag clear for CLB1_4.1 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLB8_OUT5 ,Input Flag clear for CLB8_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 14. " CLB8_OUT4 ,Input Flag clear for CLB8_OUT4 Signal" "0,1"
|
|
bitfld.long 0x00 13. " CLB7_OUT5 ,Input Flag clear for CLB7_OUT5 Signal" "0,1"
|
|
bitfld.long 0x00 12. " CLB7_OUT4 ,Input Flag clear for CLB7_OUT4 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " MCANA_FEVT2 ,Input Flag clear for MCANA_FEVT2 Signal" "0,1"
|
|
bitfld.long 0x00 10. " MCANA_FEVT1 ,Input Flag clear for MCANA_FEVT1 Signal" "0,1"
|
|
bitfld.long 0x00 9. " MCANA_FEVT0 ,Input Flag clear for MCANA_FEVT0 Signal" "0,1"
|
|
bitfld.long 0x00 8. " EMAC_PPS0 ,Input Flag clear for EMAC_PPS0 Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SD2FLT4_DRINT ,Input Flag clear for SD2FLT4.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 6. " SD2FLT4_COMPZ ,Input Flag clear for SD2FLT4.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 5. " SD2FLT3_DRINT ,Input Flag clear for SD2FLT3.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 4. " SD2FLT3_COMPZ ,Input Flag clear for SD2FLT3.COMPZ Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SD2FLT2_DRINT ,Input Flag clear for SD2FLT2.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 2. " SD2FLT2_COMPZ ,Input Flag clear for SD2FLT2.COMPZ Signal" "0,1"
|
|
bitfld.long 0x00 1. " SD2FLT1_DRINT ,Input Flag clear for SD2FLT1.DRINT Signal" "0,1"
|
|
bitfld.long 0x00 0. " SD2FLT1_COMPZ ,Input Flag clear for SD2FLT1.COMPZ Signal" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("F2838??-CM")
|
|
tree "Advance Encryption Standard Accelerator (AES)"
|
|
tree "AES"
|
|
width 19.
|
|
group.long (d:0x4004A000+0x00)++0x03
|
|
line.long 0x00 "AES_KEY2_6,XTS Second Key or CBC-MAC Third Key"
|
|
group.long (d:0x4004A000+0x04)++0x03
|
|
line.long 0x00 "AES_KEY2_7,XTS Second Key or CBC-MAC Third Key"
|
|
group.long (d:0x4004A000+0x08)++0x03
|
|
line.long 0x00 "AES_KEY2_4,XTS/CCM Second Key or CBC-MAC Third Key"
|
|
group.long (d:0x4004A000+0x0C)++0x03
|
|
line.long 0x00 "AES_KEY2_5,XTS Second Key or CBC-MAC Third Key"
|
|
group.long (d:0x4004A000+0x10)++0x03
|
|
line.long 0x00 "AES_KEY2_2,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
group.long (d:0x4004A000+0x14)++0x03
|
|
line.long 0x00 "AES_KEY2_3,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
group.long (d:0x4004A000+0x18)++0x03
|
|
line.long 0x00 "AES_KEY2_0,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
group.long (d:0x4004A000+0x1C)++0x03
|
|
line.long 0x00 "AES_KEY2_1,XTS/CCM/CBC-MAC Second Key or Hash Key Input"
|
|
group.long (d:0x4004A000+0x20)++0x03
|
|
line.long 0x00 "AES_KEY1_6,Key"
|
|
group.long (d:0x4004A000+0x24)++0x03
|
|
line.long 0x00 "AES_KEY1_7,Key"
|
|
group.long (d:0x4004A000+0x28)++0x03
|
|
line.long 0x00 "AES_KEY1_4,Key"
|
|
group.long (d:0x4004A000+0x2C)++0x03
|
|
line.long 0x00 "AES_KEY1_5,Key"
|
|
group.long (d:0x4004A000+0x30)++0x03
|
|
line.long 0x00 "AES_KEY1_2,Key"
|
|
group.long (d:0x4004A000+0x34)++0x03
|
|
line.long 0x00 "AES_KEY1_3,Key"
|
|
group.long (d:0x4004A000+0x38)++0x03
|
|
line.long 0x00 "AES_KEY1_0,Key"
|
|
group.long (d:0x4004A000+0x3C)++0x03
|
|
line.long 0x00 "AES_KEY1_1,Key"
|
|
group.long (d:0x4004A000+0x40)++0x03
|
|
line.long 0x00 "AES_IV_IN_OUT_0,Initialization Vector 0"
|
|
group.long (d:0x4004A000+0x44)++0x03
|
|
line.long 0x00 "AES_IV_IN_OUT_1,Initialization Vector 1"
|
|
group.long (d:0x4004A000+0x48)++0x03
|
|
line.long 0x00 "AES_IV_IN_OUT_2,Initialization Vector 2"
|
|
group.long (d:0x4004A000+0x4C)++0x03
|
|
line.long 0x00 "AES_IV_IN_OUT_3,Initialization Vector 3"
|
|
group.long (d:0x4004A000+0x50)++0x03
|
|
line.long 0x00 "AES_CTRL,Input/Output Buffer Control and Mode Selection"
|
|
rbitfld.long 0x00 31. " CTXTRDY ,Context Data Registers Ready" "0,1"
|
|
rbitfld.long 0x00 30. " SVCTXTRDY ,AES TAG/IV Block(s) Ready" "0,1"
|
|
bitfld.long 0x00 29. " SAVE_CONTEXT ,TAG or Result IV Save" "0,1"
|
|
bitfld.long 0x00 22.--24. " CCM_M ,Length of the authentication field for CCM operations" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " CCM_L ,Width of the length field for CCM operations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. " CCM ,AES-CCM Mode Enable" "0,1"
|
|
bitfld.long 0x00 16.--17. " GCM ,AES-GCM Mode Enable" "0,1,2,3"
|
|
bitfld.long 0x00 15. " CBCMAC ,AES-CBC MAC Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " F9 ,AES f9 Mode Enable" "0,1"
|
|
bitfld.long 0x00 13. " F8 ,AES f8 Mode Enable" "0,1"
|
|
bitfld.long 0x00 11.--12. " XTS ,AES-XTS Operation Enable" "0,1,2,3"
|
|
bitfld.long 0x00 10. " CFB ,Full block AES cipher feedback mode (CFB128) Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " ICM ,AES Integer Counter Mode (ICM) Enable" "0,1"
|
|
bitfld.long 0x00 7.--8. " CTR_WIDTH ,AES-CTR Mode Counter Width" "0,1,2,3"
|
|
bitfld.long 0x00 6. " CTR ,Counter Mode" "0,1"
|
|
bitfld.long 0x00 5. " MODE ,ECB/CBC Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " KEY_SIZE ,Key Size" "0,1,2,3"
|
|
bitfld.long 0x00 2. " DIRECTION ,Encryption/Decryption Selection" "0,1"
|
|
rbitfld.long 0x00 1. " INPUT_READY ,Input Ready Status" "0,1"
|
|
rbitfld.long 0x00 0. " OUTPUT_READY ,Output Ready Status" "0,1"
|
|
group.long (d:0x4004A000+0x54)++0x03
|
|
line.long 0x00 "AES_C_LENGTH_0,Crypto Data Length 0"
|
|
group.long (d:0x4004A000+0x58)++0x03
|
|
line.long 0x00 "AES_C_LENGTH_1,Crypto Data Length 1"
|
|
group.long (d:0x4004A000+0x5C)++0x03
|
|
line.long 0x00 "AES_AUTH_LENGTH,AAD Data Length"
|
|
group.long (d:0x4004A000+0x60)++0x03
|
|
line.long 0x00 "AES_DATA_IN_OUT_0,Data Word 0"
|
|
group.long (d:0x4004A000+0x64)++0x03
|
|
line.long 0x00 "AES_DATA_IN_OUT_1,Data Word 1"
|
|
group.long (d:0x4004A000+0x68)++0x03
|
|
line.long 0x00 "AES_DATA_IN_OUT_2,Data Word 2"
|
|
group.long (d:0x4004A000+0x6C)++0x03
|
|
line.long 0x00 "AES_DATA_IN_OUT_3,Data Word 3"
|
|
rgroup.long (d:0x4004A000+0x70)++0x03
|
|
line.long 0x00 "AES_TAG_OUT_0,Hash Result 0"
|
|
rgroup.long (d:0x4004A000+0x74)++0x03
|
|
line.long 0x00 "AES_TAG_OUT_1,Hash Result 1"
|
|
rgroup.long (d:0x4004A000+0x78)++0x03
|
|
line.long 0x00 "AES_TAG_OUT_2,Hash Result 2"
|
|
rgroup.long (d:0x4004A000+0x7C)++0x03
|
|
line.long 0x00 "AES_TAG_OUT_3,Hash Result 3"
|
|
rgroup.long (d:0x4004A000+0x80)++0x03
|
|
line.long 0x00 "AES_REV,Module Revision Number"
|
|
group.long (d:0x4004A000+0x84)++0x03
|
|
line.long 0x00 "AES_SYSCONFIG,System Configuration"
|
|
bitfld.long 0x00 9. " MAP_CONTEXT_OUT_ON_DATA_OUT ,Map Context Out on Data Out Enable" "0,1"
|
|
bitfld.long 0x00 8. " DMA_REQ_CONTEXT_OUT_EN ,DMA Request Context Out Enable" "0,1"
|
|
bitfld.long 0x00 7. " DMA_REQ_CONTEXT_IN_EN ,DMA Request Context In Enable" "0,1"
|
|
bitfld.long 0x00 6. " DMA_REQ_DATA_OUT_EN ,DMA Request Data Out Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " DMA_REQ_DATA_IN_EN ,DMA Request Data In Enable" "0,1"
|
|
bitfld.long 0x00 2.--3. " SIDLE ,Slave Idle Mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Soft Reset" "0,1"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,autoidle" "0,1"
|
|
rgroup.long (d:0x4004A000+0x88)++0x03
|
|
line.long 0x00 "AES_SYSSTATUS,Reset Status"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset Done" "0,1"
|
|
rgroup.long (d:0x4004A000+0x8C)++0x03
|
|
line.long 0x00 "AES_IRQSTATUS,Interrupt Status"
|
|
bitfld.long 0x00 3. " CONTEXT_OUT ,Context Output Interrupt Status" "0,1"
|
|
bitfld.long 0x00 2. " DATA_OUT ,Data Out Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " DATA_IN ,Data In Interrupt Status" "0,1"
|
|
bitfld.long 0x00 0. " CONTEXT_IN ,Context In Interrupt Status" "0,1"
|
|
group.long (d:0x4004A000+0x90)++0x03
|
|
line.long 0x00 "AES_IRQENABLE,Interrupt Enable"
|
|
bitfld.long 0x00 3. " CONTEXT_OUT ,Context Out Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. " DATA_OUT ,Data Out Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. " DATA_IN ,Data In Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. " CONTEXT_IN ,Context In Interrupt Enable" "0,1"
|
|
group.long (d:0x4004A000+0x94)++0x03
|
|
line.long 0x00 "AES_DIRTY_BITS,Accessed / Dirty Bits"
|
|
bitfld.long 0x00 1. " S_DIRTY ,AES Dirty Bit" "0,1"
|
|
bitfld.long 0x00 0. " S_ACCESS ,AES Access Bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AES_SS"
|
|
width 17.
|
|
group.long (d:0x4004AC00+0x00)++0x03
|
|
line.long 0x00 "AESDMAINTEN,DMA Done Interrupt enable register"
|
|
bitfld.long 0x00 3. " DMADONECTXOUT ,Enable bit for DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x00 2. " DMADONEDOUT ,Enable bit for DMADONEDOUT" "0,1"
|
|
bitfld.long 0x00 1. " DMADONEDIN ,Enable bit for DMADONEDIN" "0,1"
|
|
bitfld.long 0x00 0. " DMADONECTXIN ,Enable bit for DMADONECTXIN" "0,1"
|
|
rgroup.long (d:0x4004AC00+0x04)++0x03
|
|
line.long 0x00 "AESDMASTATUS,DMA Done Interrupt status register"
|
|
bitfld.long 0x00 3. " DMADONECTXOUT ,Status bit for DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x00 2. " DMADONEDOUT ,Status bit for DMADONEDOUT" "0,1"
|
|
bitfld.long 0x00 1. " DMADONEDIN ,Status bit for DMADONEDIN" "0,1"
|
|
bitfld.long 0x00 0. " DMADONECTXIN ,Status bit for DMADONECTXIN" "0,1"
|
|
group.long (d:0x4004AC00+0x08)++0x03
|
|
line.long 0x00 "AESDMASTATUSCLR,DMA Done Interrupt status clear register"
|
|
bitfld.long 0x00 3. " DMADONECTXOUT ,Clear bit for AESDMASTSTAUS.DMADONECTXOUT" "0,1"
|
|
bitfld.long 0x00 2. " DMADONEDOUT ,Clear bit for AESDMASTSTAUS.DMADONEDOUT" "0,1"
|
|
bitfld.long 0x00 1. " DMADONEDIN ,Clear bit for AESDMASTSTAUS.DMADONEDIN" "0,1"
|
|
bitfld.long 0x00 0. " DMADONECTXIN ,Clear bit for AESDMASTSTAUS.DMADONECTXIN" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Connectivity Manager (CM)"
|
|
tree "ERRORLOG"
|
|
width 21.
|
|
rgroup.long (d:0x400FE400+0x00)++0x03
|
|
line.long 0x00 "UCERRFLG,Uncorrectable Error Flag Register"
|
|
bitfld.long 0x00 7. " EMACMEMRDERR ,EMAC IP RAM Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 6. " EtherCATMEMRDERR ,EtherCAT IP RAM Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Uncorrectable Read Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Uncorrectable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Uncorrectable Read Error Flag" "0,1"
|
|
group.long (d:0x400FE400+0x04)++0x03
|
|
line.long 0x00 "UCERRSET,Uncorrectable Error Flag Set Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 7. " EMACMEMRDERR ,EMAC IP RAM Uncorrectable Read Error Flag set" "0,1"
|
|
bitfld.long 0x00 6. " EtherCATMEMRDERR ,EtherCAT IP RAM Uncorrectable Read Error Flag set" "0,1"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Uncorrectable Write Error Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Uncorrectable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Uncorrectable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Uncorrectable Read Error Flag Set" "0,1"
|
|
group.long (d:0x400FE400+0x08)++0x03
|
|
line.long 0x00 "UCERRCLR,Uncorrectable Error Flag Clear Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 7. " EMACMEMRDERR ,EMAC IP RAM Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 6. " EtherCATMEMRDERR ,EtherCAT IP RAM Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Uncorrectable Write Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Uncorrectable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Uncorrectable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Uncorrectable Read Error Flag Clear" "0,1"
|
|
rgroup.long (d:0x400FE400+0x0C)++0x03
|
|
line.long 0x00 "UCM4EADDR,Uncorrectable M4 Error Address"
|
|
rgroup.long (d:0x400FE400+0x10)++0x03
|
|
line.long 0x00 "UCEMACEADDR,Uncorrectable EMAC Error Address"
|
|
rgroup.long (d:0x400FE400+0x14)++0x03
|
|
line.long 0x00 "UCuDMAEADDR,Uncorrectable uDMA Error Address"
|
|
rgroup.long (d:0x400FE400+0x18)++0x03
|
|
line.long 0x00 "UCEtherCATMEMREADDR,Uncorrectable EtherCAT IP RAM Read Error Address"
|
|
rgroup.long (d:0x400FE400+0x1C)++0x03
|
|
line.long 0x00 "UCEMACMEMREADDR,Uncorrectable EMAC IP RAM Read Error Address"
|
|
rgroup.long (d:0x400FE400+0x50)++0x03
|
|
line.long 0x00 "BUSFAULTFLG,BusFault Flag register"
|
|
bitfld.long 0x00 2. " EMACBUSFAULT ,EMAC busfault Flag" "0,1"
|
|
bitfld.long 0x00 1. " UDMABUSFAULT ,UDMA busfault Flag" "0,1"
|
|
bitfld.long 0x00 0. " M4BUSFAULT ,M4 busfault Flag" "0,1"
|
|
group.long (d:0x400FE400+0x54)++0x03
|
|
line.long 0x00 "BUSFAULTCLR,BusFault Flag clear register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 2. " EMACBUSFAULT ,EMAC busfault Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " UDMABUSFAULT ,UDMA busfault Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " M4BUSFAULT ,M4 busfault Flag Clear" "0,1"
|
|
rgroup.long (d:0x400FE400+0x58)++0x03
|
|
line.long 0x00 "M4BUSFAULTADDR,M4 busfault address"
|
|
rgroup.long (d:0x400FE400+0x5C)++0x03
|
|
line.long 0x00 "uDMABUSFAULTADDR,uDMA busfault address"
|
|
rgroup.long (d:0x400FE400+0x60)++0x03
|
|
line.long 0x00 "EMACBUSFAULTADDR,EMAC busfault address"
|
|
rgroup.long (d:0x400FE400+0x80)++0x03
|
|
line.long 0x00 "CERRFLG,Correctable Error Flag Register"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Correctable Write Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Correctable Read Error Flag" "0,1"
|
|
group.long (d:0x400FE400+0x84)++0x03
|
|
line.long 0x00 "CERRSET,Correctable Error Flag Set Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Correctable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Correctable Read Error Flag Set" "0,1"
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Correctable Read Error Flag Set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Correctable Write Error Flag Set" "0,1"
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Correctable Read Error Flag Set" "0,1"
|
|
group.long (d:0x400FE400+0x88)++0x03
|
|
line.long 0x00 "CERRCLR,Correctable Error Flag Clear Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 5. " uDMAWRERR ,uDMA Correctable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 4. " uDMARDERR ,uDMA Correctable Read Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 2. " EMACRDERR ,EMAC Correctable Read Error Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " M4WRERR ,M4 Correctable Write Error Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " M4RDERR ,M4 Correctable Read Error Flag Clear" "0,1"
|
|
rgroup.long (d:0x400FE400+0x8C)++0x03
|
|
line.long 0x00 "CM4EADDR,Correctable M4 Error Address"
|
|
rgroup.long (d:0x400FE400+0x90)++0x03
|
|
line.long 0x00 "CEMACEADDR,Correctable EMAC Error Address"
|
|
rgroup.long (d:0x400FE400+0x94)++0x03
|
|
line.long 0x00 "CuDMAEADDR,Correctable uDMA Error Address"
|
|
group.long (d:0x400FE400+0xC0)++0x03
|
|
line.long 0x00 "CERRCNT,Correctable Error Count Register"
|
|
group.long (d:0x400FE400+0xC4)++0x03
|
|
line.long 0x00 "CERRTHRES,Correctable Error Threshold Value Register"
|
|
rgroup.long (d:0x400FE400+0xC8)++0x03
|
|
line.long 0x00 "CEINTFLG,Correctable Error Interrupt Flag Status Register"
|
|
bitfld.long 0x00 0. " CEINTFLAG ,Total corrected error count exceeded threshold flag." "0,1"
|
|
group.long (d:0x400FE400+0xCC)++0x03
|
|
line.long 0x00 "CEINTSET,Correctable Error Interrupt Flag Set Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 0. " CEINTSET ,Total corrected error count exceeded flag set." "0,1"
|
|
group.long (d:0x400FE400+0xD0)++0x03
|
|
line.long 0x00 "CEINTCLR,Correctable Error Interrupt Flag Clear Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 0. " CEINTCLR ,M4 Corrected Error Threshold Exceeded Error Clear." "0,1"
|
|
group.long (d:0x400FE400+0xD4)++0x03
|
|
line.long 0x00 "CEINTEN,Correctable Error Interrupt Enable Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY to allow write access"
|
|
bitfld.long 0x00 0. " CEINTEN ,M4 Correctable Error Interrupt Enable." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DIAGERRORLOG"
|
|
width 13.
|
|
rgroup.long (d:0x400FE800+0x00)++0x03
|
|
line.long 0x00 "DIAGERRFLG,Error Flag Register"
|
|
bitfld.long 0x00 3. " CWRERROR ,Diagnostics Correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 2. " CRDERROR ,Diagnostics Correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " UCWRERROR ,Diagnostics Uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 0. " UCRDERROR ,Diagnostics Uncorrectable Read Error Flag" "0,1"
|
|
group.long (d:0x400FE800+0x08)++0x03
|
|
line.long 0x00 "DIAGERRCLR,Error Flag Clear Register"
|
|
bitfld.long 0x00 3. " CWRERROR ,Clear diagnostics correctable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 2. " CRDERROR ,Clear diagnostics correctable Read Error Flag" "0,1"
|
|
bitfld.long 0x00 1. " UCWRERROR ,Clear diagnostics uncorrectable Write Error Flag" "0,1"
|
|
bitfld.long 0x00 0. " UCRDERROR ,Clear diagnostics uncorrectable Read Error Flag" "0,1"
|
|
rgroup.long (d:0x400FE800+0x0C)++0x03
|
|
line.long 0x00 "DIAGERRADDR,Read Error Address"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSFR"
|
|
width 6.
|
|
group.byte (d:0xE000E000+0xD28)++0x00
|
|
line.byte 0x00 "MMSR,MemManage Fault Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,MemManage Fault Address Register (MMFAR) valid flag" "0,1"
|
|
bitfld.byte 0x00 4. " MSTKERR ,MemManage fault on stacking for exception entry" "0,1"
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,MemManage fault on unstacking for a return from exception" "0,1"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data access violation flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction access violation flag" "0,1"
|
|
group.byte (d:0xE000E000+0xD29)++0x00
|
|
line.byte 0x00 "BFSR,BusFault Status Register"
|
|
bitfld.byte 0x00 7. " BFARVALID ,BusFault Address Register (BFAR) valid flag" "0,1"
|
|
bitfld.byte 0x00 4. " STKERR ,BusFault on stacking for exception entry" "0,1"
|
|
bitfld.byte 0x00 3. " UNSTKERR ,BusFault on unstacking for a return from exception" "0,1"
|
|
bitfld.byte 0x00 2. " IMPRECISERR ,Imprecise data bus error" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. " PRECISERR ,Precise data bus error" "0,1"
|
|
bitfld.byte 0x00 0. " IBUSERR ,Instruction bus error" "0,1"
|
|
group.word (d:0xE000E000+0xD2A)++0x01
|
|
line.word 0x00 "UFSR,UsageFault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero UsageFault" "0,1"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access UsageFault" "0,1"
|
|
bitfld.word 0x00 3. " NOCP ,No coprocessor UsageFault" "0,1"
|
|
bitfld.word 0x00 2. " INVPC ,Invalid PC load UsageFault" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid state UsageFault" "0,1"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction UsageFault" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MEMINITANDTEST"
|
|
width 23.
|
|
group.long (d:0x400FE000+0x00)++0x03
|
|
line.long 0x00 "CxLOCK,C RAM Config Lock Register"
|
|
bitfld.long 0x00 1. " LOCK_C1 ,C1 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_C0 ,C0 RAM Lock bits" "0,1"
|
|
group.long (d:0x400FE000+0x04)++0x03
|
|
line.long 0x00 "CxTEST,C RAM TEST Register"
|
|
bitfld.long 0x00 2.--3. " TEST_C1 ,Selects the different modes for C1 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_C0 ,Selects the different modes for C0 RAM" "0,1,2,3"
|
|
group.long (d:0x400FE000+0x08)++0x03
|
|
line.long 0x00 "CxINIT,C RAM Init Register"
|
|
bitfld.long 0x00 1. " INIT_C1 ,RAM Initialization control for C1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INIT_C0 ,RAM Initialization control for C0 RAM." "0,1"
|
|
rgroup.long (d:0x400FE000+0x0C)++0x03
|
|
line.long 0x00 "CxINITDONE,C RAM Initialization Status Register"
|
|
bitfld.long 0x00 1. " INITDONE_C1 ,RAM Initialization status for C1 RAM." "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_C0 ,RAM Initialization status for C0 RAM." "0,1"
|
|
group.long (d:0x400FE000+0x20)++0x03
|
|
line.long 0x00 "CMMSGxLOCK,CM Messae RAM Config Lock Register"
|
|
bitfld.long 0x00 3. " LOCK_CMTOCPU2MSGRAM1 ,Message RAM CMTOCPU2MSGRAM1 Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_CMTOCPU2MSGRAM0 ,Message RAM CMTOCPU2MSGRAM0 Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_CMTOCPU1MSGRAM1 ,Message RAM CMTOCPU1MSGRAM1 Lock bits" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_CMTOCPU1MSGRAM0 ,Message RAM CMTOCPU1MSGRAM0 Lock bits" "0,1"
|
|
group.long (d:0x400FE000+0x24)++0x03
|
|
line.long 0x00 "CMMSGxTEST,CM Messae RAM TEST Register"
|
|
bitfld.long 0x00 6.--7. " TEST_CMTOCPU2MSGRAM1 ,Selects the different modes for Message RAM CMTOCPU2MSGRAM1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_CMTOCPU2MSGRAM0 ,Selects the different modes for Message RAM CMTOCPU2MSGRAM0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_CMTOCPU1MSGRAM1 ,Selects the different modes for Message RAM CMTOCPU1MSGRAM1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TEST_CMTOCPU1MSGRAM0 ,Selects the different modes for Message RAM CMTOCPU1MSGRAM0" "0,1,2,3"
|
|
group.long (d:0x400FE000+0x28)++0x03
|
|
line.long 0x00 "CMMSGxINIT,CM Messae RAM Init Register"
|
|
bitfld.long 0x00 3. " INIT_CMTOCPU2MSGRAM1 ,RAM Initialization control for Message RAM CMTOCPU2MSGRAM1" "0,1"
|
|
bitfld.long 0x00 2. " INIT_CMTOCPU2MSGRAM0 ,RAM Initialization control for Message RAM CMTOCPU2MSGRAM0" "0,1"
|
|
bitfld.long 0x00 1. " INIT_CMTOCPU1MSGRAM1 ,RAM Initialization control for Message RAM CMTOCPU1MSGRAM1" "0,1"
|
|
bitfld.long 0x00 0. " INIT_CMTOCPU1MSGRAM0 ,RAM Initialization control for Message RAM CMTOCPU1MSGRAM0" "0,1"
|
|
rgroup.long (d:0x400FE000+0x2C)++0x03
|
|
line.long 0x00 "CMMSGxINITDONE,CM Messae RAM Initialization Status Register"
|
|
bitfld.long 0x00 3. " INITDONE_CMTOCPU2MSGRAM1 ,RAM Initialization status for Message RAM CMTOCPU2MSGRAM1" "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_CMTOCPU2MSGRAM0 ,RAM Initialization status for Message RAM CMTOCPU2MSGRAM0" "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_CMTOCPU1MSGRAM1 ,RAM Initialization status for Message RAM CMTOCPU1MSGRAM1" "0,1"
|
|
bitfld.long 0x00 0. " INITDONE_CMTOCPU1MSGRAM0 ,RAM Initialization status for Message RAM CMTOCPU1MSGRAM0" "0,1"
|
|
group.long (d:0x400FE000+0x40)++0x03
|
|
line.long 0x00 "SxGROUP1_LOCK,Group1 S and E RAM Config Lock Register"
|
|
bitfld.long 0x00 4. " LOCK_E0 ,E0 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 3. " LOCK_S3 ,S3 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 2. " LOCK_S2 ,S2 RAM Lock bits" "0,1"
|
|
bitfld.long 0x00 1. " LOCK_S1 ,S1 RAM Lock bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " LOCK_S0 ,S0 RAM Lock bits" "0,1"
|
|
group.long (d:0x400FE000+0x44)++0x03
|
|
line.long 0x00 "SxGROUP1_TEST,Group1 S and E RAM TEST Register"
|
|
bitfld.long 0x00 8.--9. " TEST_E0 ,Selects the different modes for E0 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " TEST_S3 ,Selects the different modes for S3 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TEST_S2 ,Selects the different modes for S2 RAM" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TEST_S1 ,Selects the different modes for S1 RAM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TEST_S0 ,Selects the different modes for S0 RAM" "0,1,2,3"
|
|
group.long (d:0x400FE000+0x48)++0x03
|
|
line.long 0x00 "SxGROUP1_INIT,Group1 S and E RAM Init Register"
|
|
bitfld.long 0x00 4. " INIT_E0 ,RAM Initialization control for E0 RAM." "0,1"
|
|
bitfld.long 0x00 3. " INIT_S3 ,RAM Initialization control for S3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INIT_S2 ,RAM Initialization control for S2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INIT_S1 ,RAM Initialization control for S1 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " INIT_S0 ,RAM Initialization control for S0 RAM." "0,1"
|
|
rgroup.long (d:0x400FE000+0x4C)++0x03
|
|
line.long 0x00 "SxGROUP1_INITDONE,Group1 S and E RAM Initialization Status Register"
|
|
bitfld.long 0x00 4. " INITDONE_E0 ,RAM Initialization status for E0 RAM." "0,1"
|
|
bitfld.long 0x00 3. " INITDONE_S3 ,RAM Initialization status for S3 RAM." "0,1"
|
|
bitfld.long 0x00 2. " INITDONE_S2 ,RAM Initialization status for S2 RAM." "0,1"
|
|
bitfld.long 0x00 1. " INITDONE_S1 ,RAM Initialization status for S1 RAM." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " INITDONE_S0 ,RAM Initialization status for S0 RAM." "0,1"
|
|
group.long (d:0x400FE000+0x80)++0x03
|
|
line.long 0x00 "ROM_LOCK,ROM Config Lock Register"
|
|
bitfld.long 0x00 0. " LOCK_BOOTROM ,BOOTROM Lock bits" "0,1"
|
|
group.long (d:0x400FE000+0x84)++0x03
|
|
line.long 0x00 "ROM_TEST,ROM TEST Register"
|
|
bitfld.long 0x00 0.--1. " TEST_BOOTROM ,Selects the different modes for BOOTROM" "0,1,2,3"
|
|
group.long (d:0x400FE000+0x88)++0x03
|
|
line.long 0x00 "ROM_FORCE_ERROR,ROM Force Error register"
|
|
bitfld.long 0x00 0. " FORCE_BOOTROM_ERROR ,Force Bootrom Parity Error" "0,1"
|
|
group.long (d:0x400FE000+0xA0)++0x03
|
|
line.long 0x00 "PERI_MEM_TEST_LOCK,Peripheral Memory Test Lock Register"
|
|
bitfld.long 0x00 0. " LOCK_PERI_MEM_TEST_CONTROL ,PERI_MEM_TEST_CONTROL Lock bit" "0,1"
|
|
group.long (d:0x400FE000+0xA4)++0x03
|
|
line.long 0x00 "PERI_MEM_TEST_CONTROL,Peripheral Memory Test control Register"
|
|
bitfld.long 0x00 5. " EtherCAT_MEM_FORCE_ERROR ,Force Parity Error on EtherCAT RAM" "0,1"
|
|
bitfld.long 0x00 4. " EtherCAT_TEST_ENABLE ,EtherCAT Test mode enable" "0,1"
|
|
bitfld.long 0x00 1. " EMAC_MEM_FORCE_ERROR ,Force Parity Error on EMAC RAM" "0,1"
|
|
bitfld.long 0x00 0. " EMAC_TEST_ENABLE ,EMAC Test mode enable" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
width 13.
|
|
rgroup.long (d:0xE000E000+0xD90)++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
hexmask.long 0x00 16.--23. 1. "IREGION,Indicates the number of supported MPU instruction regions"
|
|
hexmask.long 0x00 8.--15. 1. "DREGION,Indicates the number of supported MPU data regions"
|
|
bitfld.long 0x00 0. " SEPARATE ,unified/separate instruction and date memory maps" "0,1"
|
|
group.long (d:0xE000E000+0xD94)++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables privileged software access to the default memory map" "0,1"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Enables MPU during hard fault, NMI, and FAULTMASK handlers." "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "0,1"
|
|
group.long (d:0xE000E000+0xD98)++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long 0x00 0.--7. 1. "REGION,MPU region referred by the MPU_RBAR and MPU_RASR registers."
|
|
group.long (d:0xE000E000+0xD9C)++0x03
|
|
line.long 0x00 "MPU_RBAR,MPU Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 1. "ADDR,Region base address field"
|
|
bitfld.long 0x00 4. " VALID ,MPU Region Number valid bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " REGION ,MPU region field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0xE000E000+0xDA0)++0x03
|
|
line.long 0x00 "MPU_RASR,MPU Region Attribute and Size Register"
|
|
bitfld.long 0x00 28. " XN ,Instruction access disable bit" "0,1"
|
|
bitfld.long 0x00 24.--26. " AP ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " TEX ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. " S ,Memory access attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " C ,Memory access attribute" "0,1"
|
|
bitfld.long 0x00 16. " B ,Memory access attribute" "0,1"
|
|
hexmask.long 0x00 8.--15. 1. "SRD,Subregion disable bits"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Specifies the size of the MPU protection region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable bit." "0,1"
|
|
group.long (d:0xE000E000+0xDA4)++0x03
|
|
line.long 0x00 "MPU_RBAR_A1,Alias of RBAR"
|
|
hexmask.long 0x00 5.--31. 1. "ADDR,Region base address field"
|
|
bitfld.long 0x00 4. " VALID ,MPU Region Number valid bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " REGION ,MPU region field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0xE000E000+0xDA8)++0x03
|
|
line.long 0x00 "MPU_RASR_A1,Alias of RASR"
|
|
bitfld.long 0x00 28. " XN ,Instruction access disable bit" "0,1"
|
|
bitfld.long 0x00 24.--26. " AP ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " TEX ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. " S ,Memory access attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " C ,Memory access attribute" "0,1"
|
|
bitfld.long 0x00 16. " B ,Memory access attribute" "0,1"
|
|
hexmask.long 0x00 8.--15. 1. "SRD,Subregion disable bits"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Specifies the size of the MPU protection region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable bit." "0,1"
|
|
group.long (d:0xE000E000+0xDAC)++0x03
|
|
line.long 0x00 "MPU_RBAR_A2,Alias of RBAR"
|
|
hexmask.long 0x00 5.--31. 1. "ADDR,Region base address field"
|
|
bitfld.long 0x00 4. " VALID ,MPU Region Number valid bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " REGION ,MPU region field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0xE000E000+0xDB0)++0x03
|
|
line.long 0x00 "MPU_RASR_A2,Alias of RASR"
|
|
bitfld.long 0x00 28. " XN ,Instruction access disable bit" "0,1"
|
|
bitfld.long 0x00 24.--26. " AP ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " TEX ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. " S ,Memory access attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " C ,Memory access attribute" "0,1"
|
|
bitfld.long 0x00 16. " B ,Memory access attribute" "0,1"
|
|
hexmask.long 0x00 8.--15. 1. "SRD,Subregion disable bits"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Specifies the size of the MPU protection region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable bit." "0,1"
|
|
group.long (d:0xE000E000+0xDB4)++0x03
|
|
line.long 0x00 "MPU_RBAR_A3,Alias of RBAR"
|
|
hexmask.long 0x00 5.--31. 1. "ADDR,Region base address field"
|
|
bitfld.long 0x00 4. " VALID ,MPU Region Number valid bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " REGION ,MPU region field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0xE000E000+0xDB8)++0x03
|
|
line.long 0x00 "MPU_RASR_A3,Alias of RASR"
|
|
bitfld.long 0x00 28. " XN ,Instruction access disable bit" "0,1"
|
|
bitfld.long 0x00 24.--26. " AP ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " TEX ,Memory access attribute" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. " S ,Memory access attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " C ,Memory access attribute" "0,1"
|
|
bitfld.long 0x00 16. " B ,Memory access attribute" "0,1"
|
|
hexmask.long 0x00 8.--15. 1. "SRD,Subregion disable bits"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Specifies the size of the MPU protection region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable bit." "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Non-Maskable Interrupt (NMI)"
|
|
width 14.
|
|
group.long (d:0x40081000+0x00)++0x03
|
|
line.long 0x00 "CMNMICFG,CM NMI Configuration Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x00 0. " NMIE ,Global NMI Enable" "0,1"
|
|
rgroup.long (d:0x40081000+0x04)++0x03
|
|
line.long 0x00 "CMNMIFLG,CM NMI Flag Register"
|
|
bitfld.long 0x00 6. " ECATNMI ,NMI from EtherCAT reset out" "0,1"
|
|
bitfld.long 0x00 5. " WWDNMI ,CM WWD NMI flag" "0,1"
|
|
bitfld.long 0x00 4. " MCANUNCERR ,MCAN Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.long 0x00 3. " FLUNCERR ,Flash Uncorrectable Error NMI Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " MEMUNCERR ,RAM, ROM Uncorrectable Error NMI Flag" "0,1"
|
|
bitfld.long 0x00 1. " CLOCKFAIL ,Clock Fail Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 0. " NMIINT ,NMI Interrupt Flag" "0,1"
|
|
group.long (d:0x40081000+0x08)++0x03
|
|
line.long 0x00 "CMNMIFLGCLR,CMNMI Flag Clear Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x00 6. " ECATNMI ,ECATNMI Flag Clear" "0,1"
|
|
bitfld.long 0x00 5. " WWDNMI ,WWDNMI Flag Clear" "0,1"
|
|
bitfld.long 0x00 4. " MCANUNCERR ,MCANUNCERR Flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FLUNCERR ,FLUNCERR Flag Clear" "0,1"
|
|
bitfld.long 0x00 2. " MEMUNCERR ,MEMUNCERR Flag Clear" "0,1"
|
|
bitfld.long 0x00 1. " CLOCKFAIL ,CLOCKFAIL Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " NMIINT ,NMIINT Flag Clear" "0,1"
|
|
group.long (d:0x40081000+0x0C)++0x03
|
|
line.long 0x00 "CMNMIFLGFRC,CMNMI Flag Force Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key protection"
|
|
bitfld.long 0x00 6. " ECATNMI ,ECATNMI Flag Force" "0,1"
|
|
bitfld.long 0x00 5. " WWDNMI ,WWDNMI Flag Force" "0,1"
|
|
bitfld.long 0x00 4. " MCANUNCERR ,MCANUNCERR Flag Force" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FLUNCERR ,FLUNCERR Flag Force" "0,1"
|
|
bitfld.long 0x00 2. " MEMUNCERR ,MEMUNCERR Flag Force" "0,1"
|
|
bitfld.long 0x00 1. " CLOCKFAIL ,CLOCKFAIL Flag Force" "0,1"
|
|
rgroup.long (d:0x40081000+0x10)++0x03
|
|
line.long 0x00 "CMNMIWDCNT,CMNMI Watchdog Counter Register"
|
|
hexmask.long 0x00 0.--15. 1. "NMIWDCNT,NMI Watchdog Counter"
|
|
group.long (d:0x40081000+0x14)++0x03
|
|
line.long 0x00 "CMNMIWDPRD,CMNMI Watchdog Period Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key protection"
|
|
hexmask.long 0x00 0.--15. 1. "NMIWDPRD,NMI Watchdog Period"
|
|
rgroup.long (d:0x40081000+0x18)++0x03
|
|
line.long 0x00 "CMNMISHDWFLG,CMNMI Shadow Flag Register"
|
|
bitfld.long 0x00 6. " ECATNMI ,ECATNMI Shadow flag" "0,1"
|
|
bitfld.long 0x00 5. " WWDNMI ,WWDNMI Shadow flag" "0,1"
|
|
bitfld.long 0x00 4. " MCANUNCERR ,MCANUNCERR Shadow flag" "0,1"
|
|
bitfld.long 0x00 3. " FLUNCERR ,FLUNCERR Shadow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " MEMUNCERR ,MEMUNCERR Shadow flag" "0,1"
|
|
bitfld.long 0x00 1. " CLOCKFAIL ,CLOCKFAIL Shadow flag" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
width 12.
|
|
group.long (d:0xE000E000+0x100)++0x03
|
|
line.long 0x00 "NVIC_ISER0,NVIC Interrupt Set Enable Register 0"
|
|
bitfld.long 0x00 31. " SETENA31 ,Set INTR31 Enable" "0,1"
|
|
bitfld.long 0x00 30. " SETENA30 ,Set INTR30 Enable" "0,1"
|
|
bitfld.long 0x00 29. " SETENA29 ,Set INTR29 Enable" "0,1"
|
|
bitfld.long 0x00 28. " SETENA28 ,Set INTR28 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SETENA27 ,Set INTR27 Enable" "0,1"
|
|
bitfld.long 0x00 26. " SETENA26 ,Set INTR26 Enable" "0,1"
|
|
bitfld.long 0x00 25. " SETENA25 ,Set INTR25 Enable" "0,1"
|
|
bitfld.long 0x00 24. " SETENA24 ,Set INTR24 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SETENA23 ,Set INTR23 Enable" "0,1"
|
|
bitfld.long 0x00 22. " SETENA22 ,Set INTR22 Enable" "0,1"
|
|
bitfld.long 0x00 21. " SETENA21 ,Set INTR21 Enable" "0,1"
|
|
bitfld.long 0x00 20. " SETENA20 ,Set INTR20 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SETENA19 ,Set INTR19 Enable" "0,1"
|
|
bitfld.long 0x00 18. " SETENA18 ,Set INTR18 Enable" "0,1"
|
|
bitfld.long 0x00 17. " SETENA17 ,Set INTR17 Enable" "0,1"
|
|
bitfld.long 0x00 16. " SETENA16 ,Set INTR16 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SETENA15 ,Set INTR15 Enable" "0,1"
|
|
bitfld.long 0x00 14. " SETENA14 ,Set INTR14 Enable" "0,1"
|
|
bitfld.long 0x00 13. " SETENA13 ,Set INTR13 Enable" "0,1"
|
|
bitfld.long 0x00 12. " SETENA12 ,Set INTR12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SETENA11 ,Set INTR11 Enable" "0,1"
|
|
bitfld.long 0x00 10. " SETENA10 ,Set INTR10 Enable" "0,1"
|
|
bitfld.long 0x00 9. " SETENA9 ,Set INTR9 Enable" "0,1"
|
|
bitfld.long 0x00 8. " SETENA8 ,Set INTR8 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SETENA7 ,Set INTR7 Enable" "0,1"
|
|
bitfld.long 0x00 6. " SETENA6 ,Set INTR6 Enable" "0,1"
|
|
bitfld.long 0x00 5. " SETENA5 ,Set INTR5 Enable" "0,1"
|
|
bitfld.long 0x00 4. " SETENA4 ,Set INTR4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SETENA3 ,Set INTR3 Enable" "0,1"
|
|
bitfld.long 0x00 2. " SETENA2 ,Set INTR2 Enable" "0,1"
|
|
bitfld.long 0x00 1. " SETENA1 ,Set INTR1 Enable" "0,1"
|
|
bitfld.long 0x00 0. " SETENA0 ,Set INTR0 Enable" "0,1"
|
|
group.long (d:0xE000E000+0x104)++0x03
|
|
line.long 0x00 "NVIC_ISER1,NVIC Interrupt Set Enable Register 1"
|
|
bitfld.long 0x00 31. " SETENA63 ,Set INTR63 Enable" "0,1"
|
|
bitfld.long 0x00 30. " SETENA62 ,Set INTR62 Enable" "0,1"
|
|
bitfld.long 0x00 29. " SETENA61 ,Set INTR61 Enable" "0,1"
|
|
bitfld.long 0x00 28. " SETENA60 ,Set INTR60 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SETENA59 ,Set INTR59 Enable" "0,1"
|
|
bitfld.long 0x00 26. " SETENA58 ,Set INTR58 Enable" "0,1"
|
|
bitfld.long 0x00 25. " SETENA57 ,Set INTR57 Enable" "0,1"
|
|
bitfld.long 0x00 24. " SETENA56 ,Set INTR56 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SETENA55 ,Set INTR55 Enable" "0,1"
|
|
bitfld.long 0x00 22. " SETENA54 ,Set INTR54 Enable" "0,1"
|
|
bitfld.long 0x00 21. " SETENA53 ,Set INTR53 Enable" "0,1"
|
|
bitfld.long 0x00 20. " SETENA52 ,Set INTR52 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SETENA51 ,Set INTR51 Enable" "0,1"
|
|
bitfld.long 0x00 18. " SETENA50 ,Set INTR50 Enable" "0,1"
|
|
bitfld.long 0x00 17. " SETENA49 ,Set INTR49 Enable" "0,1"
|
|
bitfld.long 0x00 16. " SETENA48 ,Set INTR48 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SETENA47 ,Set INTR47 Enable" "0,1"
|
|
bitfld.long 0x00 14. " SETENA46 ,Set INTR46 Enable" "0,1"
|
|
bitfld.long 0x00 13. " SETENA45 ,Set INTR45 Enable" "0,1"
|
|
bitfld.long 0x00 12. " SETENA44 ,Set INTR44 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SETENA43 ,Set INTR43 Enable" "0,1"
|
|
bitfld.long 0x00 10. " SETENA42 ,Set INTR42 Enable" "0,1"
|
|
bitfld.long 0x00 9. " SETENA41 ,Set INTR41 Enable" "0,1"
|
|
bitfld.long 0x00 8. " SETENA40 ,Set INTR40 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SETENA39 ,Set INTR39 Enable" "0,1"
|
|
bitfld.long 0x00 6. " SETENA38 ,Set INTR38 Enable" "0,1"
|
|
bitfld.long 0x00 5. " SETENA37 ,Set INTR37 Enable" "0,1"
|
|
bitfld.long 0x00 4. " SETENA36 ,Set INTR36 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SETENA35 ,Set INTR35 Enable" "0,1"
|
|
bitfld.long 0x00 2. " SETENA34 ,Set INTR34 Enable" "0,1"
|
|
bitfld.long 0x00 1. " SETENA33 ,Set INTR33 Enable" "0,1"
|
|
bitfld.long 0x00 0. " SETENA32 ,Set INTR32 Enable" "0,1"
|
|
group.long (d:0xE000E000+0x180)++0x03
|
|
line.long 0x00 "NVIC_ICER0,NVIC Interrupt Clear Enable Register 0"
|
|
bitfld.long 0x00 31. " CLRENA31 ,Clear INTR31 Enable" "0,1"
|
|
bitfld.long 0x00 30. " CLRENA30 ,Clear INTR30 Enable" "0,1"
|
|
bitfld.long 0x00 29. " CLRENA29 ,Clear INTR29 Enable" "0,1"
|
|
bitfld.long 0x00 28. " CLRENA28 ,Clear INTR28 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLRENA27 ,Clear INTR27 Enable" "0,1"
|
|
bitfld.long 0x00 26. " CLRENA26 ,Clear INTR26 Enable" "0,1"
|
|
bitfld.long 0x00 25. " CLRENA25 ,Clear INTR25 Enable" "0,1"
|
|
bitfld.long 0x00 24. " CLRENA24 ,Clear INTR24 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLRENA23 ,Clear INTR23 Enable" "0,1"
|
|
bitfld.long 0x00 22. " CLRENA22 ,Clear INTR22 Enable" "0,1"
|
|
bitfld.long 0x00 21. " CLRENA21 ,Clear INTR21 Enable" "0,1"
|
|
bitfld.long 0x00 20. " CLRENA20 ,Clear INTR20 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRENA19 ,Clear INTR19 Enable" "0,1"
|
|
bitfld.long 0x00 18. " CLRENA18 ,Clear INTR18 Enable" "0,1"
|
|
bitfld.long 0x00 17. " CLRENA17 ,Clear INTR17 Enable" "0,1"
|
|
bitfld.long 0x00 16. " CLRENA16 ,Clear INTR16 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLRENA15 ,Clear INTR15 Enable" "0,1"
|
|
bitfld.long 0x00 14. " CLRENA14 ,Clear INTR14 Enable" "0,1"
|
|
bitfld.long 0x00 13. " CLRENA13 ,Clear INTR13 Enable" "0,1"
|
|
bitfld.long 0x00 12. " CLRENA12 ,Clear INTR12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CLRENA11 ,Clear INTR11 Enable" "0,1"
|
|
bitfld.long 0x00 10. " CLRENA10 ,Clear INTR10 Enable" "0,1"
|
|
bitfld.long 0x00 9. " CLRENA9 ,Clear INTR9 Enable" "0,1"
|
|
bitfld.long 0x00 8. " CLRENA8 ,Clear INTR8 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CLRENA7 ,Clear INTR7 Enable" "0,1"
|
|
bitfld.long 0x00 6. " CLRENA6 ,Clear INTR6 Enable" "0,1"
|
|
bitfld.long 0x00 5. " CLRENA5 ,Clear INTR5 Enable" "0,1"
|
|
bitfld.long 0x00 4. " CLRENA4 ,Clear INTR4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRENA3 ,Clear INTR3 Enable" "0,1"
|
|
bitfld.long 0x00 2. " CLRENA2 ,Clear INTR2 Enable" "0,1"
|
|
bitfld.long 0x00 1. " CLRENA1 ,Clear INTR1 Enable" "0,1"
|
|
bitfld.long 0x00 0. " CLRENA0 ,Clear INTR0 Enable" "0,1"
|
|
group.long (d:0xE000E000+0x184)++0x03
|
|
line.long 0x00 "NVIC_ICER1,NVIC Interrupt Clear Enable Register 1"
|
|
bitfld.long 0x00 31. " CLRENA63 ,Clear INTR63 Enable" "0,1"
|
|
bitfld.long 0x00 30. " CLRENA62 ,Clear INTR62 Enable" "0,1"
|
|
bitfld.long 0x00 29. " CLRENA61 ,Clear INTR61 Enable" "0,1"
|
|
bitfld.long 0x00 28. " CLRENA60 ,Clear INTR60 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLRENA59 ,Clear INTR59 Enable" "0,1"
|
|
bitfld.long 0x00 26. " CLRENA58 ,Clear INTR58 Enable" "0,1"
|
|
bitfld.long 0x00 25. " CLRENA57 ,Clear INTR57 Enable" "0,1"
|
|
bitfld.long 0x00 24. " CLRENA56 ,Clear INTR56 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLRENA55 ,Clear INTR55 Enable" "0,1"
|
|
bitfld.long 0x00 22. " CLRENA54 ,Clear INTR54 Enable" "0,1"
|
|
bitfld.long 0x00 21. " CLRENA53 ,Clear INTR53 Enable" "0,1"
|
|
bitfld.long 0x00 20. " CLRENA52 ,Clear INTR52 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRENA51 ,Clear INTR51 Enable" "0,1"
|
|
bitfld.long 0x00 18. " CLRENA50 ,Clear INTR50 Enable" "0,1"
|
|
bitfld.long 0x00 17. " CLRENA49 ,Clear INTR49 Enable" "0,1"
|
|
bitfld.long 0x00 16. " CLRENA48 ,Clear INTR48 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLRENA47 ,Clear INTR47 Enable" "0,1"
|
|
bitfld.long 0x00 14. " CLRENA46 ,Clear INTR46 Enable" "0,1"
|
|
bitfld.long 0x00 13. " CLRENA45 ,Clear INTR45 Enable" "0,1"
|
|
bitfld.long 0x00 12. " CLRENA44 ,Clear INTR44 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CLRENA43 ,Clear INTR43 Enable" "0,1"
|
|
bitfld.long 0x00 10. " CLRENA42 ,Clear INTR42 Enable" "0,1"
|
|
bitfld.long 0x00 9. " CLRENA41 ,Clear INTR41 Enable" "0,1"
|
|
bitfld.long 0x00 8. " CLRENA40 ,Clear INTR40 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CLRENA39 ,Clear INTR39 Enable" "0,1"
|
|
bitfld.long 0x00 6. " CLRENA38 ,Clear INTR38 Enable" "0,1"
|
|
bitfld.long 0x00 5. " CLRENA37 ,Clear INTR37 Enable" "0,1"
|
|
bitfld.long 0x00 4. " CLRENA36 ,Clear INTR36 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRENA35 ,Clear INTR35 Enable" "0,1"
|
|
bitfld.long 0x00 2. " CLRENA34 ,Clear INTR34 Enable" "0,1"
|
|
bitfld.long 0x00 1. " CLRENA33 ,Clear INTR33 Enable" "0,1"
|
|
bitfld.long 0x00 0. " CLRENA32 ,Clear INTR32 Enable" "0,1"
|
|
group.long (d:0xE000E000+0x200)++0x03
|
|
line.long 0x00 "NVIC_ISPR0,NVIC Interrupt Set Pending Register 0"
|
|
bitfld.long 0x00 31. " SETPEND31 ,Set INTR31 Pending" "0,1"
|
|
bitfld.long 0x00 30. " SETPEND30 ,Set INTR30 Pending" "0,1"
|
|
bitfld.long 0x00 29. " SETPEND29 ,Set INTR29 Pending" "0,1"
|
|
bitfld.long 0x00 28. " SETPEND28 ,Set INTR28 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SETPEND27 ,Set INTR27 Pending" "0,1"
|
|
bitfld.long 0x00 26. " SETPEND26 ,Set INTR26 Pending" "0,1"
|
|
bitfld.long 0x00 25. " SETPEND25 ,Set INTR25 Pending" "0,1"
|
|
bitfld.long 0x00 24. " SETPEND24 ,Set INTR24 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SETPEND23 ,Set INTR23 Pending" "0,1"
|
|
bitfld.long 0x00 22. " SETPEND22 ,Set INTR22 Pending" "0,1"
|
|
bitfld.long 0x00 21. " SETPEND21 ,Set INTR21 Pending" "0,1"
|
|
bitfld.long 0x00 20. " SETPEND20 ,Set INTR20 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SETPEND19 ,Set INTR19 Pending" "0,1"
|
|
bitfld.long 0x00 18. " SETPEND18 ,Set INTR18 Pending" "0,1"
|
|
bitfld.long 0x00 17. " SETPEND17 ,Set INTR17 Pending" "0,1"
|
|
bitfld.long 0x00 16. " SETPEND16 ,Set INTR16 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SETPEND15 ,Set INTR15 Pending" "0,1"
|
|
bitfld.long 0x00 14. " SETPEND14 ,Set INTR14 Pending" "0,1"
|
|
bitfld.long 0x00 13. " SETPEND13 ,Set INTR13 Pending" "0,1"
|
|
bitfld.long 0x00 12. " SETPEND12 ,Set INTR12 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SETPEND11 ,Set INTR11 Pending" "0,1"
|
|
bitfld.long 0x00 10. " SETPEND10 ,Set INTR10 Pending" "0,1"
|
|
bitfld.long 0x00 9. " SETPEND9 ,Set INTR9 Pending" "0,1"
|
|
bitfld.long 0x00 8. " SETPEND8 ,Set INTR8 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SETPEND7 ,Set INTR7 Pending" "0,1"
|
|
bitfld.long 0x00 6. " SETPEND6 ,Set INTR6 Pending" "0,1"
|
|
bitfld.long 0x00 5. " SETPEND5 ,Set INTR5 Pending" "0,1"
|
|
bitfld.long 0x00 4. " SETPEND4 ,Set INTR4 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SETPEND3 ,Set INTR3 Pending" "0,1"
|
|
bitfld.long 0x00 2. " SETPEND2 ,Set INTR2 Pending" "0,1"
|
|
bitfld.long 0x00 1. " SETPEND1 ,Set INTR1 Pending" "0,1"
|
|
bitfld.long 0x00 0. " SETPEND0 ,Set INTR0 Pending" "0,1"
|
|
group.long (d:0xE000E000+0x204)++0x03
|
|
line.long 0x00 "NVIC_ISPR1,NVIC Interrupt Set Pending Register 1"
|
|
bitfld.long 0x00 31. " SETPEND63 ,Set INTR63 Pending" "0,1"
|
|
bitfld.long 0x00 30. " SETPEND62 ,Set INTR62 Pending" "0,1"
|
|
bitfld.long 0x00 29. " SETPEND61 ,Set INTR61 Pending" "0,1"
|
|
bitfld.long 0x00 28. " SETPEND60 ,Set INTR60 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SETPEND59 ,Set INTR59 Pending" "0,1"
|
|
bitfld.long 0x00 26. " SETPEND58 ,Set INTR58 Pending" "0,1"
|
|
bitfld.long 0x00 25. " SETPEND57 ,Set INTR57 Pending" "0,1"
|
|
bitfld.long 0x00 24. " SETPEND56 ,Set INTR56 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SETPEND55 ,Set INTR55 Pending" "0,1"
|
|
bitfld.long 0x00 22. " SETPEND54 ,Set INTR54 Pending" "0,1"
|
|
bitfld.long 0x00 21. " SETPEND53 ,Set INTR53 Pending" "0,1"
|
|
bitfld.long 0x00 20. " SETPEND52 ,Set INTR52 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SETPEND51 ,Set INTR51 Pending" "0,1"
|
|
bitfld.long 0x00 18. " SETPEND50 ,Set INTR50 Pending" "0,1"
|
|
bitfld.long 0x00 17. " SETPEND49 ,Set INTR49 Pending" "0,1"
|
|
bitfld.long 0x00 16. " SETPEND48 ,Set INTR48 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SETPEND47 ,Set INTR47 Pending" "0,1"
|
|
bitfld.long 0x00 14. " SETPEND46 ,Set INTR46 Pending" "0,1"
|
|
bitfld.long 0x00 13. " SETPEND45 ,Set INTR45 Pending" "0,1"
|
|
bitfld.long 0x00 12. " SETPEND44 ,Set INTR44 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SETPEND43 ,Set INTR43 Pending" "0,1"
|
|
bitfld.long 0x00 10. " SETPEND42 ,Set INTR42 Pending" "0,1"
|
|
bitfld.long 0x00 9. " SETPEND41 ,Set INTR41 Pending" "0,1"
|
|
bitfld.long 0x00 8. " SETPEND40 ,Set INTR40 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SETPEND39 ,Set INTR39 Pending" "0,1"
|
|
bitfld.long 0x00 6. " SETPEND38 ,Set INTR38 Pending" "0,1"
|
|
bitfld.long 0x00 5. " SETPEND37 ,Set INTR37 Pending" "0,1"
|
|
bitfld.long 0x00 4. " SETPEND36 ,Set INTR36 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SETPEND35 ,Set INTR35 Pending" "0,1"
|
|
bitfld.long 0x00 2. " SETPEND34 ,Set INTR34 Pending" "0,1"
|
|
bitfld.long 0x00 1. " SETPEND33 ,Set INTR33 Pending" "0,1"
|
|
bitfld.long 0x00 0. " SETPEND32 ,Set INTR32 Pending" "0,1"
|
|
group.long (d:0xE000E000+0x208)++0x03
|
|
line.long 0x00 "NVIC_ISPR2,NVIC Interrupt Set Pending Register 2"
|
|
bitfld.long 0x00 31. " SETPEND95 ,Set INTR95 Pending" "0,1"
|
|
bitfld.long 0x00 30. " SETPEND94 ,Set INTR94 Pending" "0,1"
|
|
bitfld.long 0x00 29. " SETPEND93 ,Set INTR93 Pending" "0,1"
|
|
bitfld.long 0x00 28. " SETPEND92 ,Set INTR92 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " SETPEND91 ,Set INTR91 Pending" "0,1"
|
|
bitfld.long 0x00 26. " SETPEND90 ,Set INTR90 Pending" "0,1"
|
|
bitfld.long 0x00 25. " SETPEND89 ,Set INTR89 Pending" "0,1"
|
|
bitfld.long 0x00 24. " SETPEND88 ,Set INTR88 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " SETPEND87 ,Set INTR87 Pending" "0,1"
|
|
bitfld.long 0x00 22. " SETPEND86 ,Set INTR86 Pending" "0,1"
|
|
bitfld.long 0x00 21. " SETPEND85 ,Set INTR85 Pending" "0,1"
|
|
bitfld.long 0x00 20. " SETPEND84 ,Set INTR84 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " SETPEND83 ,Set INTR83 Pending" "0,1"
|
|
bitfld.long 0x00 18. " SETPEND82 ,Set INTR82 Pending" "0,1"
|
|
bitfld.long 0x00 17. " SETPEND81 ,Set INTR81 Pending" "0,1"
|
|
bitfld.long 0x00 16. " SETPEND80 ,Set INTR80 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " SETPEND79 ,Set INTR79 Pending" "0,1"
|
|
bitfld.long 0x00 14. " SETPEND78 ,Set INTR78 Pending" "0,1"
|
|
bitfld.long 0x00 13. " SETPEND77 ,Set INTR77 Pending" "0,1"
|
|
bitfld.long 0x00 12. " SETPEND76 ,Set INTR76 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " SETPEND75 ,Set INTR75 Pending" "0,1"
|
|
bitfld.long 0x00 10. " SETPEND74 ,Set INTR74 Pending" "0,1"
|
|
bitfld.long 0x00 9. " SETPEND73 ,Set INTR73 Pending" "0,1"
|
|
bitfld.long 0x00 8. " SETPEND72 ,Set INTR72 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SETPEND71 ,Set INTR71 Pending" "0,1"
|
|
bitfld.long 0x00 6. " SETPEND70 ,Set INTR70 Pending" "0,1"
|
|
bitfld.long 0x00 5. " SETPEND69 ,Set INTR69 Pending" "0,1"
|
|
bitfld.long 0x00 4. " SETPEND68 ,Set INTR68 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " SETPEND67 ,Set INTR67 Pending" "0,1"
|
|
bitfld.long 0x00 2. " SETPEND66 ,Set INTR66 Pending" "0,1"
|
|
bitfld.long 0x00 1. " SETPEND65 ,Set INTR65 Pending" "0,1"
|
|
bitfld.long 0x00 0. " SETPEND64 ,Set INTR64 Pending" "0,1"
|
|
group.long (d:0xE000E000+0x280)++0x03
|
|
line.long 0x00 "NVIC_ICPR0,NVIC Interrupt Clear Pending Register 0"
|
|
bitfld.long 0x00 31. " CLRPEND31 ,Clear INTR31 Pending" "0,1"
|
|
bitfld.long 0x00 30. " CLRPEND30 ,Clear INTR30 Pending" "0,1"
|
|
bitfld.long 0x00 29. " CLRPEND29 ,Clear INTR29 Pending" "0,1"
|
|
bitfld.long 0x00 28. " CLRPEND28 ,Clear INTR28 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLRPEND27 ,Clear INTR27 Pending" "0,1"
|
|
bitfld.long 0x00 26. " CLRPEND26 ,Clear INTR26 Pending" "0,1"
|
|
bitfld.long 0x00 25. " CLRPEND25 ,Clear INTR25 Pending" "0,1"
|
|
bitfld.long 0x00 24. " CLRPEND24 ,Clear INTR24 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLRPEND23 ,Clear INTR23 Pending" "0,1"
|
|
bitfld.long 0x00 22. " CLRPEND22 ,Clear INTR22 Pending" "0,1"
|
|
bitfld.long 0x00 21. " CLRPEND21 ,Clear INTR21 Pending" "0,1"
|
|
bitfld.long 0x00 20. " CLRPEND20 ,Clear INTR20 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRPEND19 ,Clear INTR19 Pending" "0,1"
|
|
bitfld.long 0x00 18. " CLRPEND18 ,Clear INTR18 Pending" "0,1"
|
|
bitfld.long 0x00 17. " CLRPEND17 ,Clear INTR17 Pending" "0,1"
|
|
bitfld.long 0x00 16. " CLRPEND16 ,Clear INTR16 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLRPEND15 ,Clear INTR15 Pending" "0,1"
|
|
bitfld.long 0x00 14. " CLRPEND14 ,Clear INTR14 Pending" "0,1"
|
|
bitfld.long 0x00 13. " CLRPEND13 ,Clear INTR13 Pending" "0,1"
|
|
bitfld.long 0x00 12. " CLRPEND12 ,Clear INTR12 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CLRPEND11 ,Clear INTR11 Pending" "0,1"
|
|
bitfld.long 0x00 10. " CLRPEND10 ,Clear INTR10 Pending" "0,1"
|
|
bitfld.long 0x00 9. " CLRPEND9 ,Clear INTR9 Pending" "0,1"
|
|
bitfld.long 0x00 8. " CLRPEND8 ,Clear INTR8 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CLRPEND7 ,Clear INTR7 Pending" "0,1"
|
|
bitfld.long 0x00 6. " CLRPEND6 ,Clear INTR6 Pending" "0,1"
|
|
bitfld.long 0x00 5. " CLRPEND5 ,Clear INTR5 Pending" "0,1"
|
|
bitfld.long 0x00 4. " CLRPEND4 ,Clear INTR4 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRPEND3 ,Clear INTR3 Pending" "0,1"
|
|
bitfld.long 0x00 2. " CLRPEND2 ,Clear INTR2 Pending" "0,1"
|
|
bitfld.long 0x00 1. " CLRPEND1 ,Clear INTR1 Pending" "0,1"
|
|
bitfld.long 0x00 0. " CLRPEND0 ,Clear INTR0 Pending" "0,1"
|
|
group.long (d:0xE000E000+0x284)++0x03
|
|
line.long 0x00 "NVIC_ICPR1,NVIC Interrupt Clear Pending Register 1"
|
|
bitfld.long 0x00 31. " CLRPEND63 ,Clear INTR63 Pending" "0,1"
|
|
bitfld.long 0x00 30. " CLRPEND62 ,Clear INTR62 Pending" "0,1"
|
|
bitfld.long 0x00 29. " CLRPEND61 ,Clear INTR61 Pending" "0,1"
|
|
bitfld.long 0x00 28. " CLRPEND60 ,Clear INTR60 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CLRPEND59 ,Clear INTR59 Pending" "0,1"
|
|
bitfld.long 0x00 26. " CLRPEND58 ,Clear INTR58 Pending" "0,1"
|
|
bitfld.long 0x00 25. " CLRPEND57 ,Clear INTR57 Pending" "0,1"
|
|
bitfld.long 0x00 24. " CLRPEND56 ,Clear INTR56 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CLRPEND55 ,Clear INTR55 Pending" "0,1"
|
|
bitfld.long 0x00 22. " CLRPEND54 ,Clear INTR54 Pending" "0,1"
|
|
bitfld.long 0x00 21. " CLRPEND53 ,Clear INTR53 Pending" "0,1"
|
|
bitfld.long 0x00 20. " CLRPEND52 ,Clear INTR52 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRPEND51 ,Clear INTR51 Pending" "0,1"
|
|
bitfld.long 0x00 18. " CLRPEND50 ,Clear INTR50 Pending" "0,1"
|
|
bitfld.long 0x00 17. " CLRPEND49 ,Clear INTR49 Pending" "0,1"
|
|
bitfld.long 0x00 16. " CLRPEND48 ,Clear INTR48 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CLRPEND47 ,Clear INTR47 Pending" "0,1"
|
|
bitfld.long 0x00 14. " CLRPEND46 ,Clear INTR46 Pending" "0,1"
|
|
bitfld.long 0x00 13. " CLRPEND45 ,Clear INTR45 Pending" "0,1"
|
|
bitfld.long 0x00 12. " CLRPEND44 ,Clear INTR44 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CLRPEND43 ,Clear INTR43 Pending" "0,1"
|
|
bitfld.long 0x00 10. " CLRPEND42 ,Clear INTR42 Pending" "0,1"
|
|
bitfld.long 0x00 9. " CLRPEND41 ,Clear INTR41 Pending" "0,1"
|
|
bitfld.long 0x00 8. " CLRPEND40 ,Clear INTR40 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CLRPEND39 ,Clear INTR39 Pending" "0,1"
|
|
bitfld.long 0x00 6. " CLRPEND38 ,Clear INTR38 Pending" "0,1"
|
|
bitfld.long 0x00 5. " CLRPEND37 ,Clear INTR37 Pending" "0,1"
|
|
bitfld.long 0x00 4. " CLRPEND36 ,Clear INTR36 Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CLRPEND35 ,Clear INTR35 Pending" "0,1"
|
|
bitfld.long 0x00 2. " CLRPEND34 ,Clear INTR34 Pending" "0,1"
|
|
bitfld.long 0x00 1. " CLRPEND33 ,Clear INTR33 Pending" "0,1"
|
|
bitfld.long 0x00 0. " CLRPEND32 ,Clear INTR32 Pending" "0,1"
|
|
rgroup.long (d:0xE000E000+0x300)++0x03
|
|
line.long 0x00 "NVIC_IABR0,NVIC Interrupt Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,INTR31 Active" "0,1"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,INTR30 Active" "0,1"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,INTR29 Active" "0,1"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,INTR28 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ACTIVE27 ,INTR27 Active" "0,1"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,INTR26 Active" "0,1"
|
|
bitfld.long 0x00 25. " ACTIVE25 ,INTR25 Active" "0,1"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,INTR24 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ACTIVE23 ,INTR23 Active" "0,1"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,INTR22 Active" "0,1"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,INTR21 Active" "0,1"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,INTR20 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE19 ,INTR19 Active" "0,1"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,INTR18 Active" "0,1"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,INTR17 Active" "0,1"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,INTR16 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ACTIVE15 ,INTR15 Active" "0,1"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,INTR14 Active" "0,1"
|
|
bitfld.long 0x00 13. " ACTIVE13 ,INTR13 Active" "0,1"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,INTR12 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ACTIVE11 ,INTR11 Active" "0,1"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,INTR10 Active" "0,1"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,INTR9 Active" "0,1"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,INTR8 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE7 ,INTR7 Active" "0,1"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,INTR6 Active" "0,1"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,INTR5 Active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,INTR4 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ACTIVE3 ,INTR3 Active" "0,1"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,INTR2 Active" "0,1"
|
|
bitfld.long 0x00 1. " ACTIVE1 ,INTR1 Active" "0,1"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,INTR0 Active" "0,1"
|
|
rgroup.long (d:0xE000E000+0x304)++0x03
|
|
line.long 0x00 "NVIC_IABR1,NVIC Interrupt Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,INTR63 Active" "0,1"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,INTR62 Active" "0,1"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,INTR61 Active" "0,1"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,INTR60 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ACTIVE59 ,INTR59 Active" "0,1"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,INTR58 Active" "0,1"
|
|
bitfld.long 0x00 25. " ACTIVE57 ,INTR57 Active" "0,1"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,INTR56 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ACTIVE55 ,INTR55 Active" "0,1"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,INTR54 Active" "0,1"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,INTR53 Active" "0,1"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,INTR52 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE51 ,INTR51 Active" "0,1"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,INTR50 Active" "0,1"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,INTR49 Active" "0,1"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,INTR48 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ACTIVE47 ,INTR47 Active" "0,1"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,INTR46 Active" "0,1"
|
|
bitfld.long 0x00 13. " ACTIVE45 ,INTR45 Active" "0,1"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,INTR44 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ACTIVE43 ,INTR43 Active" "0,1"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,INTR42 Active" "0,1"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,INTR41 Active" "0,1"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,INTR40 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE39 ,INTR39 Active" "0,1"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,INTR38 Active" "0,1"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,INTR37 Active" "0,1"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,INTR36 Active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ACTIVE35 ,INTR35 Active" "0,1"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,INTR34 Active" "0,1"
|
|
bitfld.long 0x00 1. " ACTIVE33 ,INTR33 Active" "0,1"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,INTR32 Active" "0,1"
|
|
group.long (d:0xE000E000+0x400)++0x03
|
|
line.long 0x00 "NVIC_IPR0,NVIC Interrupt Priority Register 0"
|
|
bitfld.long 0x00 29.--31. " PRI_3 ,Priority, byte offset 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_2 ,Priority, byte offset 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_1 ,Priority, byte offset 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_0 ,Priority, byte offset 0" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x404)++0x03
|
|
line.long 0x00 "NVIC_IPR1,NVIC Interrupt Priority Register 1"
|
|
bitfld.long 0x00 29.--31. " PRI_7 ,Priority, byte offset 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_6 ,Priority, byte offset 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_5 ,Priority, byte offset 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_4 ,Priority, byte offset 4" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x408)++0x03
|
|
line.long 0x00 "NVIC_IPR2,NVIC Interrupt Priority Register 2"
|
|
bitfld.long 0x00 29.--31. " PRI_11 ,Priority, byte offset 11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_10 ,Priority, byte offset 10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_9 ,Priority, byte offset 9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_8 ,Priority, byte offset 8" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x40C)++0x03
|
|
line.long 0x00 "NVIC_IPR3,NVIC Interrupt Priority Register 3"
|
|
bitfld.long 0x00 29.--31. " PRI_15 ,Priority, byte offset 15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_14 ,Priority, byte offset 14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_13 ,Priority, byte offset 13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_12 ,Priority, byte offset 12" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x410)++0x03
|
|
line.long 0x00 "NVIC_IPR4,NVIC Interrupt Priority Register 4"
|
|
bitfld.long 0x00 29.--31. " PRI_19 ,Priority, byte offset 19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_18 ,Priority, byte offset 18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_17 ,Priority, byte offset 17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_16 ,Priority, byte offset 16" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x414)++0x03
|
|
line.long 0x00 "NVIC_IPR5,NVIC Interrupt Priority Register 5"
|
|
bitfld.long 0x00 29.--31. " PRI_23 ,Priority, byte offset 23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_22 ,Priority, byte offset 22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_21 ,Priority, byte offset 21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_20 ,Priority, byte offset 20" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x418)++0x03
|
|
line.long 0x00 "NVIC_IPR6,NVIC Interrupt Priority Register 6"
|
|
bitfld.long 0x00 29.--31. " PRI_27 ,Priority, byte offset 27" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_26 ,Priority, byte offset 26" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_25 ,Priority, byte offset 25" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_24 ,Priority, byte offset 24" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x41C)++0x03
|
|
line.long 0x00 "NVIC_IPR7,NVIC Interrupt Priority Register 7"
|
|
bitfld.long 0x00 29.--31. " PRI_31 ,Priority, byte offset 31" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_30 ,Priority, byte offset 30" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_29 ,Priority, byte offset 29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_28 ,Priority, byte offset 28" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x420)++0x03
|
|
line.long 0x00 "NVIC_IPR8,NVIC Interrupt Priority Register 8"
|
|
bitfld.long 0x00 29.--31. " PRI_35 ,Priority, byte offset 35" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_34 ,Priority, byte offset 34" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_33 ,Priority, byte offset 33" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_32 ,Priority, byte offset 32" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x424)++0x03
|
|
line.long 0x00 "NVIC_IPR9,NVIC Interrupt Priority Register 9"
|
|
bitfld.long 0x00 29.--31. " PRI_39 ,Priority, byte offset 39" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_38 ,Priority, byte offset 38" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_37 ,Priority, byte offset 37" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_36 ,Priority, byte offset 36" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x428)++0x03
|
|
line.long 0x00 "NVIC_IPR10,NVIC Interrupt Priority Register 10"
|
|
bitfld.long 0x00 29.--31. " PRI_43 ,Priority, byte offset 43" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_42 ,Priority, byte offset 42" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_41 ,Priority, byte offset 41" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_40 ,Priority, byte offset 40" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x42C)++0x03
|
|
line.long 0x00 "NVIC_IPR11,NVIC Interrupt Priority Register 11"
|
|
bitfld.long 0x00 29.--31. " PRI_47 ,Priority, byte offset 47" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_46 ,Priority, byte offset 46" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_45 ,Priority, byte offset 45" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_44 ,Priority, byte offset 44" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x430)++0x03
|
|
line.long 0x00 "NVIC_IPR12,NVIC Interrupt Priority Register 12"
|
|
bitfld.long 0x00 29.--31. " PRI_51 ,Priority, byte offset 51" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_50 ,Priority, byte offset 50" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_49 ,Priority, byte offset 49" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_48 ,Priority, byte offset 48" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x434)++0x03
|
|
line.long 0x00 "NVIC_IPR13,NVIC Interrupt Priority Register 13"
|
|
bitfld.long 0x00 29.--31. " PRI_55 ,Priority, byte offset 55" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_54 ,Priority, byte offset 54" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_53 ,Priority, byte offset 53" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_52 ,Priority, byte offset 52" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x438)++0x03
|
|
line.long 0x00 "NVIC_IPR14,NVIC Interrupt Priority Register 14"
|
|
bitfld.long 0x00 29.--31. " PRI_59 ,Priority, byte offset 59" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_58 ,Priority, byte offset 58" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_57 ,Priority, byte offset 57" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_56 ,Priority, byte offset 56" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0x43C)++0x03
|
|
line.long 0x00 "NVIC_IPR15,NVIC Interrupt Priority Register 15"
|
|
bitfld.long 0x00 29.--31. " PRI_63 ,Priority, byte offset 63" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_62 ,Priority, byte offset 62" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_61 ,Priority, byte offset 61" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_60 ,Priority, byte offset 60" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0xF00)++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long 0x00 0.--8. 1. "INTID,Software Trigger Interrupt Register."
|
|
width 0x0B
|
|
tree.end
|
|
tree "CMSYSCTL"
|
|
width 19.
|
|
group.long (d:0x400FC000+0x00)++0x03
|
|
line.long 0x00 "CMPCLKCR0,CM Peripheral clock gating register 0."
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 12. " USB ,USB Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 8. " I2C0 ,I2C0 Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 4. " SSI0 ,SSI0 Clock gating Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " UART0 ,UART0 Clock gating Bit" "0,1"
|
|
group.long (d:0x400FC000+0x04)++0x03
|
|
line.long 0x00 "CMPCLKCR1,CM Peripheral clock gating register 1."
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 8. " MCAN_A ,MCAN_A Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 5. " CAN_B ,CAN_B Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 4. " CAN_A ,CAN_A Clock gating Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ETHERCAT ,ETHERCAT Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 0. " ETHERNET ,ETHERNET Clock gating Bit" "0,1"
|
|
group.long (d:0x400FC000+0x08)++0x03
|
|
line.long 0x00 "CMPCLKCR2,CM Peripheral clock gating register 2."
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 8. " GCRC ,GCRC Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 6. " AESIP ,AESIP Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 4. " UDMA ,UDMA Clock gating Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " CPUTIMER2 ,CPUTIMER2 Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 1. " CPUTIMER1 ,CPUTIMER1 Clock gating Bit" "0,1"
|
|
bitfld.long 0x00 0. " CPUTIMER0 ,CPUTIMER0 Clock gating Bit" "0,1"
|
|
group.long (d:0x400FC000+0x20)++0x03
|
|
line.long 0x00 "CMSOFTPRESET0,CM Software Peripheral Reset register 0"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 12. " USB ,USB Soft reset bit" "0,1"
|
|
bitfld.long 0x00 8. " I2C0 ,I2C0 Soft reset bit" "0,1"
|
|
bitfld.long 0x00 4. " SSI0 ,SSI0 Soft reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " UART0 ,UART0 Soft reset bit" "0,1"
|
|
group.long (d:0x400FC000+0x24)++0x03
|
|
line.long 0x00 "CMSOFTPRESET1,CM Software Peripheral Reset register 1"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 8. " MCAN_A ,MCAN_A Soft reset bit" "0,1"
|
|
bitfld.long 0x00 5. " CAN_B ,CAN_B Soft reset bit" "0,1"
|
|
bitfld.long 0x00 4. " CAN_A ,CAN_A Soft reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " ETHERCAT ,ETHERCAT Soft reset bit" "0,1"
|
|
bitfld.long 0x00 0. " ETHERNET ,ETHERNET Soft reset bit" "0,1"
|
|
group.long (d:0x400FC000+0x28)++0x03
|
|
line.long 0x00 "CMSOFTPRESET2,CM Software Peripheral Reset register 2"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 8. " GCRC ,GCRC Soft reset bit" "0,1"
|
|
bitfld.long 0x00 6. " AESIP ,AESIP Soft reset bit" "0,1"
|
|
group.long (d:0x400FC000+0x40)++0x03
|
|
line.long 0x00 "CMCLKSTOPREQ0,Peripheral Clock Stop Request Register 0"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
group.long (d:0x400FC000+0x44)++0x03
|
|
line.long 0x00 "CMCLKSTOPREQ1,Peripheral Clock Stop Request Register 1"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
bitfld.long 0x00 8. " MCAN_A ,MCAN_A Clock Stop Request Bit" "0,1"
|
|
group.long (d:0x400FC000+0x48)++0x03
|
|
line.long 0x00 "CMCLKSTOPREQ2,Peripheral Clock Stop Request Register 2"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key field"
|
|
hgroup.long (d:0x400FC000+0x60)++0x03
|
|
hide.long 0x00 "CMCLKSTOPACK0,Peripheral Clock Stop Ackonwledge Register 0"
|
|
rgroup.long (d:0x400FC000+0x64)++0x03
|
|
line.long 0x00 "CMCLKSTOPACK1,Peripheral Clock Stop Ackonwledge Register 1"
|
|
bitfld.long 0x00 8. " MCAN_A ,MCAN_A Clock Stop Ack Bit" "0,1"
|
|
hgroup.long (d:0x400FC000+0x68)++0x03
|
|
hide.long 0x00 "CMCLKSTOPACK2,Peripheral Clock Stop Ackonwledge Register 2"
|
|
rgroup.long (d:0x400FC000+0xE0)++0x03
|
|
line.long 0x00 "MCANWAKESTATUS,MCAN Wake Status Register"
|
|
bitfld.long 0x00 0. " WAKE ,MCAN Wake Status" "0,1"
|
|
group.long (d:0x400FC000+0xE4)++0x03
|
|
line.long 0x00 "MCANWAKESTATUSCLR,MCAN Wake Status Clear Register"
|
|
bitfld.long 0x00 0. " WAKE ,Cear bit for MCANWAKESTATUS.WAKE bit" "0,1"
|
|
group.long (d:0x400FC000+0x100)++0x03
|
|
line.long 0x00 "CMECATCTL,CM etherCAT control register"
|
|
bitfld.long 0x00 0. " I2CLOOPBACK ,Loopback I2C port of etherCAT IP to CM I2C." "0,1"
|
|
rgroup.long (d:0x400FC000+0x1F4)++0x03
|
|
line.long 0x00 "PALLOCATESTS,Status of PALLOCATE register."
|
|
bitfld.long 0x00 4. " MCAN_A ,Status of PALLOCATE.MCAN_A bit" "0,1"
|
|
bitfld.long 0x00 3. " CAN_B ,Status of PALLOCATE.CAN_B bit" "0,1"
|
|
bitfld.long 0x00 2. " CAN_A ,Status of PALLOCATE.CAN_A bit" "0,1"
|
|
bitfld.long 0x00 1. " ETHERCAT ,Status of PALLOCATE.ETHERCAT bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " USB ,Status of PALLOCATE.USB bit" "0,1"
|
|
group.long (d:0x400FC000+0x1F8)++0x03
|
|
line.long 0x00 "CMRESCCLR,CM Reset Cause Status Clear Register"
|
|
bitfld.long 0x00 19. " CMEOLRESETn ,CMEOLRESETn status flag clear" "0,1"
|
|
bitfld.long 0x00 18. " CMNMIWDRSTn ,CMNMIWDRSTn status flag clear" "0,1"
|
|
bitfld.long 0x00 17. " CMSYSRESETREQ ,CMSYSRESETREQ status flag clear" "0,1"
|
|
bitfld.long 0x00 16. " CMVECTRESETn ,CMVECTRESETn status flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CPU1_SIMRESET_XRSn ,CPU1_SIMRESET_XRSn status flag clear" "0,1"
|
|
bitfld.long 0x00 8. " CMRSTCTLRESETREQ ,CMRSTCTLRESETREQ status flag clear" "0,1"
|
|
bitfld.long 0x00 7. " CPU1SIMRESET_CPURSn ,CPU1SIMRESET_CPURSn status flag clear" "0,1"
|
|
bitfld.long 0x00 6. " ECAT_RESET_OUT ,ECAT_RESET_OUT status flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " CPU1SCCRESETn ,CPU1SCCRESETn status flag clear" "0,1"
|
|
bitfld.long 0x00 4. " CPU1SYSRSN ,CPU1SYSRSN status flag clear" "0,1"
|
|
bitfld.long 0x00 3. " CPU1NMIWDRSn ,CPU1NMIWDRSn status flag clear" "0,1"
|
|
bitfld.long 0x00 2. " CPU1WDRSn ,CPU1WDRSn status flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " XRSn ,XRSn status flag clear" "0,1"
|
|
bitfld.long 0x00 0. " PORESETn ,PORESETn status flag clear" "0,1"
|
|
rgroup.long (d:0x400FC000+0x1FC)++0x03
|
|
line.long 0x00 "CMRESC,CM Reset Cause Status Register"
|
|
bitfld.long 0x00 19. " CMEOLRESETn ,CMEOLRESETn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 18. " CMNMIWDRSTn ,CMNMIWDRSTn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 17. " CMSYSRESETREQ ,CMSYSRESETREQ caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 16. " CMVECTRESETn ,CMVECTRESETn caused the reset of CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " CPU1_SIMRESET_XRSn ,CPU1_SIMRESET_XRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 8. " CMRSTCTL_RESETREQ ,CMRSTCTL_RESETREQ caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 7. " CPU1_SIMRESET_CPURSn ,CPU1_SIMRESET_CPURSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 6. " ECAT_RESET_OUT ,ECAT_RESET_OUT caused the reset of CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " CPU1_SCCRESETn ,CPU1_SCCRESETn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 4. " CPU1_SYSRSN ,CPU1_SYSRSN caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 3. " CPU1_NMIWDRSn ,CPU1_NMIWDRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 2. " CPU1_WDRSn ,CPU1_WDRSn caused the reset of CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " XRSn ,XRSn caused the reset of CM" "0,1"
|
|
bitfld.long 0x00 0. " PORESETn ,PORESETn caused the reset of CM" "0,1"
|
|
group.long (d:0x400FC000+0x200)++0x03
|
|
line.long 0x00 "CMSYSCTLLOCK,Locks the configuration registers of CM System control"
|
|
bitfld.long 0x00 0. " LOCK ,Locks the configuration registers of CM System Control" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCB"
|
|
width 8.
|
|
group.long (d:0xE000E000+0x08)++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 8. " DISFPCA ,Disables automatic update of CONTROL.FPCA." "0,1"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables IT folding." "0,1"
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disable write buffer on default memory map." "0,1"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disable interruption of load/store multiple instruction." "0,1"
|
|
rgroup.long (d:0xE000E000+0xD00)++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long 0x00 24.--31. 1. "Implementer,Implementer"
|
|
bitfld.long 0x00 20.--23. " Variant ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " Constant ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long 0x00 4.--15. 1. "PartNo,PartNo"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " Revision ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0xE000E000+0xD04)++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,NMI set-pending bit." "0,1"
|
|
bitfld.long 0x00 28. " PENDSVSET ,PendSV set-pending bit." "0,1"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,PendSV clear-pending bit." "0,1"
|
|
bitfld.long 0x00 26. " PENDSTSET ,SysTick exception set-pending bit." "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " PENDSTCLR ,SysTick exception clear-pending bit" "0,1"
|
|
rbitfld.long 0x00 22. " ISRPENDING ,Interrupt pending flag" "0,1"
|
|
rbitfld.long 0x00 12.--17. " VECTPENDING ,Exception number of highest priority pending exception." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 11. " RETTOBASE ,Indicates presence of preempted active exceptions." "0,1"
|
|
newline
|
|
hexmask.long 0x00 0.--8. 1. "VECTACTIVE,Active exception number"
|
|
group.long (d:0xE000E000+0xD08)++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 1. "TBLOFF,Vector table offset."
|
|
group.long (d:0xE000E000+0xD0C)++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long 0x00 16.--31. 1. "VECTKEY,Vector Key."
|
|
rbitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "0,1"
|
|
bitfld.long 0x00 8.--10. " PRIGROUP ,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset request bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Reserved for Debug use." "0,1"
|
|
bitfld.long 0x00 0. " VECTRESET ,CPU Reset" "0,1"
|
|
group.long (d:0xE000E000+0xD10)++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,sleep-on-exit when returning from Handler mode." "0,1"
|
|
group.long (d:0xE000E000+0xD14)++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates stack alignment on exception entry." "0,1"
|
|
bitfld.long 0x00 8. " BFHFNMIGN ,Ignore data BusFaults caused by load and store instructions." "0,1"
|
|
bitfld.long 0x00 4. " DIV_0_TRP ,faulting/halting on DIV by 0 exception." "0,1"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Enables unaligned access traps." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " USERSETMPEND ,Enables unprivileged software access to the STIR." "0,1"
|
|
bitfld.long 0x00 0. " NONBASETHRDENA ,Indicates how the processor enters Thread mode" "0,1"
|
|
group.long (d:0xE000E000+0xD18)++0x03
|
|
line.long 0x00 "SHPR1,System Handler Priority Register 1"
|
|
bitfld.long 0x00 21.--23. " PRI_6 ,Priority of system handler 6, UsageFault" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " PRI_5 ,Priority of system handler 5, BusFault" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " PRI_4 ,Priority of system handler 4, MemManage" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0xD1C)++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 29.--31. " PRI_11 ,Priority of system handler 11, SVCall" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0xD20)++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 29.--31. " PRI_15 ,Priority of system handler 15, SysTick exception" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " PRI_14 ,Priority of system handler 14, PendSV" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0xE000E000+0xD24)++0x03
|
|
line.long 0x00 "SHCSRS,System Handler Control and State Register"
|
|
bitfld.long 0x00 18. " USGFAULTENA ,UsageFault enable bit" "0,1"
|
|
bitfld.long 0x00 17. " BUSFAULTENA ,BusFault enable bit" "0,1"
|
|
bitfld.long 0x00 16. " MEMFAULTENA ,MemManage enable bit" "0,1"
|
|
bitfld.long 0x00 15. " SVCALLPENDED ,SVCall pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault exception pending bit" "0,1"
|
|
bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage exception pending bit" "0,1"
|
|
bitfld.long 0x00 12. " USGFAULTPENDED ,UsageFault exception pending bit" "0,1"
|
|
rbitfld.long 0x00 11. " SYSTICKACT ,SysTick exception active bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. " PENDSVACT ,PendSV exception active bit" "0,1"
|
|
rbitfld.long 0x00 8. " MONITORACT ,Debug monitor active bit" "0,1"
|
|
rbitfld.long 0x00 7. " SVCALLACT ,SVCall active bit" "0,1"
|
|
rbitfld.long 0x00 3. " USGFAULTACT ,UsageFault exception active bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. " BUSFAULTACT ,BusFault exception active bit" "0,1"
|
|
rbitfld.long 0x00 0. " MEMFAULTACT ,MemManage exception active bit" "0,1"
|
|
group.long (d:0xE000E000+0xD28)++0x03
|
|
line.long 0x00 "CFSR,Configurable Fault Status Register"
|
|
bitfld.long 0x00 25. " DIVBYZERO ,Divide by zero UsageFault" "0,1"
|
|
bitfld.long 0x00 24. " UNALIGNED ,Unaligned access UsageFault" "0,1"
|
|
bitfld.long 0x00 19. " NOCP ,No coprocessor UsageFault" "0,1"
|
|
bitfld.long 0x00 18. " INVPC ,Invalid PC load UsageFault" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " INVSTATE ,Invalid state UsageFault" "0,1"
|
|
bitfld.long 0x00 16. " UNDEFINSTR ,Undefined instruction UsageFault" "0,1"
|
|
bitfld.long 0x00 15. " BFARVALID ,BusFault Address Register (BFAR) valid flag" "0,1"
|
|
bitfld.long 0x00 12. " STKERR ,BusFault on stacking for exception entry" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " UNSTKERR ,BusFault on unstacking for a return from exception" "0,1"
|
|
bitfld.long 0x00 10. " IMPRECISERR ,Imprecise data bus error" "0,1"
|
|
bitfld.long 0x00 9. " PRECISERR ,Precise data bus error" "0,1"
|
|
bitfld.long 0x00 8. " IBUSERR ,Instruction bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " MMARVALID ,MemManage Fault Address Register (MMFAR) valid flag" "0,1"
|
|
bitfld.long 0x00 4. " MSTKERR ,MemManage fault on stacking for exception entry" "0,1"
|
|
bitfld.long 0x00 3. " MUNSTKERR ,MemManage fault on unstacking for a return from exception" "0,1"
|
|
bitfld.long 0x00 1. " DACCVIOL ,Data access violation flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " IACCVIOL ,Instruction access violation flag" "0,1"
|
|
group.long (d:0xE000E000+0xD2C)++0x03
|
|
line.long 0x00 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates a forced DEBUG event fault" "0,1"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates a forced hard fault" "0,1"
|
|
bitfld.long 0x00 1. " VECTTBL ,BusFault on a vector table read." "0,1"
|
|
group.long (d:0xE000E000+0xD34)++0x03
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
group.long (d:0xE000E000+0xD38)++0x03
|
|
line.long 0x00 "BFAR,BusFault Address Register"
|
|
group.long (d:0xE000E000+0xD3C)++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "System Timer (SYSTICK)"
|
|
width 12.
|
|
group.long (d:0xE000E000+0x10)++0x03
|
|
line.long 0x00 "SYST_CSR,Privileged a SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,timer counted to 0 since last read." "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Indicates the clock source" "0,1"
|
|
bitfld.long 0x00 1. " TICKINT ,Enables SysTick exception request" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the counter" "0,1"
|
|
group.long (d:0xE000E000+0x14)++0x03
|
|
line.long 0x00 "SYST_RVR,Privileged Unknown SysTick Reload Value Register"
|
|
hexmask.long 0x00 0.--23. 1. "RELOAD,Counter reload value"
|
|
group.long (d:0xE000E000+0x18)++0x03
|
|
line.long 0x00 "SYST_CVR,Privileged Unknown SysTick Current Value Register"
|
|
hexmask.long 0x00 0.--23. 1. "CURRENT,Current counter value"
|
|
group.long (d:0xE000E000+0x1C)++0x03
|
|
line.long 0x00 "SYST_CALIB,Privileged -a SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Device provides a reference clock to the processor" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the TENMS value is exact" "0,1"
|
|
hexmask.long 0x00 0.--23. 1. "TENMS,Current counter value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Watchdog Timer (WDT)"
|
|
width 8.
|
|
group.long (d:0x40080000+0x00)++0x03
|
|
line.long 0x00 "SCSR,System Control and Status Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
hexmask.long 0x00 3.--15. 1. "rsvd,Reserved"
|
|
rbitfld.long 0x00 1. " WDENINT ,WD Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. " WDOVERRIDE ,WD Override for WDDIS bit" "0,1"
|
|
rgroup.long (d:0x40080000+0x04)++0x03
|
|
line.long 0x00 "WDCNTR,Watchdog Counter Register"
|
|
hexmask.long 0x00 8.--31. 1. "rsvd,Reserved"
|
|
hexmask.long 0x00 0.--7. 1. "WDCNTR,WD Counter"
|
|
group.long (d:0x40080000+0x08)++0x03
|
|
line.long 0x00 "WDKEY,Watchdog Reset Key Register"
|
|
hexmask.long 0x00 8.--31. 1. "rsvd,Reserved"
|
|
hexmask.long 0x00 0.--7. 1. "WDKEY,WD KEY"
|
|
group.long (d:0x40080000+0x0C)++0x03
|
|
line.long 0x00 "WDCR,Watchdog Control Register"
|
|
hexmask.long 0x00 12.--31. 1. "rsvd,Reserved"
|
|
bitfld.long 0x00 8.--11. " WDPRECLKDIV ,WD Pre Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " WDFLG ,WD Reset Status Flag" "0,1"
|
|
bitfld.long 0x00 6. " WDDIS ,WD Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " WDCHK ,WD Check Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " WDPS ,WD Clock Prescalar" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x40080000+0x10)++0x03
|
|
line.long 0x00 "WDWCR,Watchdog Windowed Control Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,KEY field"
|
|
rbitfld.long 0x00 9.--15. " rsvd ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8. " FIRSTKEY ,First Key Detect Flag" "0,1"
|
|
hexmask.long 0x00 0.--7. 1. "MIN,WD Min Threshold setting for Windowed Watchdog functionality"
|
|
width 0x0B
|
|
tree.end
|
|
tree "32-Bit CM CPU Timers 0/1/2"
|
|
tree "Timer 0"
|
|
width 5.
|
|
group.long (d:0x40084000+0x0+0x00)++0x03
|
|
line.long 0x00 "TIM,Timer counter register"
|
|
group.long (d:0x40084000+0x0+0x04)++0x03
|
|
line.long 0x00 "PRD,Timer period register"
|
|
group.long (d:0x40084000+0x0+0x08)++0x03
|
|
line.long 0x00 "TCR,Timer control register"
|
|
bitfld.long 0x00 15. " TIF ,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x00 14. " TIE ,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 11. " FREE ,Free run enable" "0,1"
|
|
bitfld.long 0x00 10. " SOFT ,SOFT stop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " TRB ,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x00 4. " TSS ,Timer Stop Status" "0,1"
|
|
group.long (d:0x40084000+0x0+0x0C)++0x03
|
|
line.long 0x00 "TPR,Timer prescaler register"
|
|
hexmask.long 0x00 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long 0x00 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long 0x00 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long 0x00 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 1"
|
|
width 5.
|
|
group.long (d:0x40084000+0x10+0x00)++0x03
|
|
line.long 0x00 "TIM,Timer counter register"
|
|
group.long (d:0x40084000+0x10+0x04)++0x03
|
|
line.long 0x00 "PRD,Timer period register"
|
|
group.long (d:0x40084000+0x10+0x08)++0x03
|
|
line.long 0x00 "TCR,Timer control register"
|
|
bitfld.long 0x00 15. " TIF ,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x00 14. " TIE ,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 11. " FREE ,Free run enable" "0,1"
|
|
bitfld.long 0x00 10. " SOFT ,SOFT stop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " TRB ,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x00 4. " TSS ,Timer Stop Status" "0,1"
|
|
group.long (d:0x40084000+0x10+0x0C)++0x03
|
|
line.long 0x00 "TPR,Timer prescaler register"
|
|
hexmask.long 0x00 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long 0x00 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long 0x00 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long 0x00 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Timer 2"
|
|
width 5.
|
|
group.long (d:0x40084000+0x20+0x00)++0x03
|
|
line.long 0x00 "TIM,Timer counter register"
|
|
group.long (d:0x40084000+0x20+0x04)++0x03
|
|
line.long 0x00 "PRD,Timer period register"
|
|
group.long (d:0x40084000+0x20+0x08)++0x03
|
|
line.long 0x00 "TCR,Timer control register"
|
|
bitfld.long 0x00 15. " TIF ,Timer Intrerrupt Flag" "0,1"
|
|
bitfld.long 0x00 14. " TIE ,Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 11. " FREE ,Free run enable" "0,1"
|
|
bitfld.long 0x00 10. " SOFT ,SOFT stop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " TRB ,Timer Reload Bit" "0,1"
|
|
bitfld.long 0x00 4. " TSS ,Timer Stop Status" "0,1"
|
|
group.long (d:0x40084000+0x20+0x0C)++0x03
|
|
line.long 0x00 "TPR,Timer prescaler register"
|
|
hexmask.long 0x00 24.--31. 1. "PSCH,Prescaler Counter high"
|
|
hexmask.long 0x00 16.--23. 1. "TDDRH,Timer Divide Down Register High"
|
|
hexmask.long 0x00 8.--15. 1. "PSCL,Prescaler Counter low"
|
|
hexmask.long 0x00 0.--7. 1. "TDDRL,Timer Divide Down Register Low"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "Dual Code Security Module (DCSM)"
|
|
tree "Common"
|
|
width 12.
|
|
group.long (d:0x40085180+0x00)++0x03
|
|
line.long 0x00 "FLSEM,Flash Wrapper Semaphore Register"
|
|
hexmask.long 0x00 8.--15. 1. "KEY,Semaphore Key"
|
|
bitfld.long 0x00 0.--1. " SEM ,Flash Semaphore Bit" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x10)++0x03
|
|
line.long 0x00 "SECTSTAT1,Flash Sectors Status Register 1"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CPU1 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CPU1 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CPU1 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CPU1 BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CPU1 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CPU1 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CPU1 BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CPU1 BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CPU1 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CPU1 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CPU1 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CPU1 BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CPU1 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CPU1 BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x14)++0x03
|
|
line.long 0x00 "SECTSTAT2,Flash Sectors Status Register 2"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CM BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CM BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CM BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CM BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CM BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CM BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CM BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CM BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CM BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CM BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CM BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CM BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CM BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CM BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x18)++0x03
|
|
line.long 0x00 "SECTSTAT3,Flash Sectors Status Register 3"
|
|
bitfld.long 0x00 26.--27. " STATUS_SECT13 ,Zone Status flash CPU2 BANK Sector 13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_SECT12 ,Zone Status flash CPU2 BANK Sector 12" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " STATUS_SECT11 ,Zone Status flash CPU2 BANK Sector 11" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_SECT10 ,Zone Status flash CPU2 BANK Sector 10" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " STATUS_SECT9 ,Zone Status flash CPU2 BANK Sector 9" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_SECT8 ,Zone Status flash CPU2 BANK sector 8" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_SECT7 ,Zone Status flash CPU2 BANK Sector 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_SECT6 ,Zone Status flash CPU2 BANK Sector 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_SECT5 ,Zone Status flash CPU2 BANK Sector 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_SECT4 ,Zone Status flash CPU2 BANK Sector 4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_SECT3 ,Zone Status flash CPU2 BANK Sector 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_SECT2 ,Zone Status flash CPU2 BANK Sector 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_SECT1 ,Zone Status flash CPU2 BANK sector 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_SECT0 ,Zone Status flash CPU2 BANK Sector 0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x20)++0x03
|
|
line.long 0x00 "RAMSTAT1,RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_RAM3 ,Zone Status RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_RAM2 ,Zone Status RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x24)++0x03
|
|
line.long 0x00 "RAMSTAT2,RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " STATUS_RAM15 ,Zone Status RAM CPU2 to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " STATUS_RAM14 ,Zone Status RAM CPU2 to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " STATUS_RAM13 ,Zone Status RAM CPU1 to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " STATUS_RAM12 ,Zone Status RAM CPU1 to CPU2 MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " STATUS_RAM11 ,Zone Status RAM CM to CPU2 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " STATUS_RAM10 ,Zone Status RAM CM to CPU2 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU2 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU2 to CM MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CM to CPU1 MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CM to CPU1 MSG RAM 1" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU1 to CM MSG RAM 2" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU1 to CM MSG RAM 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x28)++0x03
|
|
line.long 0x00 "RAMSTAT3,RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " STATUS_RAM9 ,Zone Status RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " STATUS_RAM8 ,Zone Status RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " STATUS_RAM7 ,Zone Status RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " STATUS_RAM6 ,Zone Status RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " STATUS_RAM5 ,Zone Status RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " STATUS_RAM4 ,Zone Status RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " STATUS_RAM3 ,Zone Status RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " STATUS_RAM2 ,Zone Status RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " STATUS_RAM1 ,Zone Status RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " STATUS_RAM0 ,Zone Status RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085180+0x30)++0x03
|
|
line.long 0x00 "SECERRSTAT,Security Error Status Register"
|
|
bitfld.long 0x00 0. " ERR ,Security Configuration load Error Status" "0,1"
|
|
group.long (d:0x40085180+0x34)++0x03
|
|
line.long 0x00 "SECERRCLR,Security Error Clear Register"
|
|
bitfld.long 0x00 0. " ERR ,Clear Security Configuration Load Error Status Bit" "0,1"
|
|
group.long (d:0x40085180+0x38)++0x03
|
|
line.long 0x00 "SECERRFRC,Security Error Force Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Valid Register Write Key"
|
|
bitfld.long 0x00 0. " ERR ,Set Security Configuration Load Error Status Bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Zone 1"
|
|
width 19.
|
|
rgroup.long (d:0x40085000+0x00)++0x03
|
|
line.long 0x00 "Z1_LINKPOINTER,Zone 1 Link Pointer"
|
|
hexmask.long 0x00 0.--13. 1. "LINKPOINTER,Zone1 LINK Pointer"
|
|
rgroup.long (d:0x40085000+0x04)++0x03
|
|
line.long 0x00 "Z1_OTPSECLOCK,Zone 1 OTP Secure Lock"
|
|
bitfld.long 0x00 8.--11. " CRCLOCK ,Zone1 CRC Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PSWDLOCK ,Zone1 Password Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " JTAGLOCK ,JTAG Lock Status" "0,1"
|
|
rgroup.long (d:0x40085000+0x08)++0x03
|
|
line.long 0x00 "Z1_JLM_ENABLE,Zone 1 JTAGLOCK Enable Register"
|
|
bitfld.long 0x00 0.--3. " Z1_JLM_ENABLE ,Zone1 JLM_ENABLE register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x40085000+0x0C)++0x03
|
|
line.long 0x00 "Z1_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long 0x00 0.--13. 1. "Z1_LINKPOINTERERR,Error to Resolve Z1 Link pointer from OTP loaded values"
|
|
rgroup.long (d:0x40085000+0x10)++0x03
|
|
line.long 0x00 "Z1_GPREG1,Zone 1 General Purpose Register-1"
|
|
rgroup.long (d:0x40085000+0x14)++0x03
|
|
line.long 0x00 "Z1_GPREG2,Zone 1 General Purpose Register-2"
|
|
rgroup.long (d:0x40085000+0x18)++0x03
|
|
line.long 0x00 "Z1_GPREG3,Zone 1 General Purpose Register-3"
|
|
rgroup.long (d:0x40085000+0x1C)++0x03
|
|
line.long 0x00 "Z1_GPREG4,Zone 1 General Purpose Register-4"
|
|
group.long (d:0x40085000+0x20)++0x03
|
|
line.long 0x00 "Z1_CSMKEY0,Zone 1 CSM Key 0"
|
|
group.long (d:0x40085000+0x24)++0x03
|
|
line.long 0x00 "Z1_CSMKEY1,Zone 1 CSM Key 1"
|
|
group.long (d:0x40085000+0x28)++0x03
|
|
line.long 0x00 "Z1_CSMKEY2,Zone 1 CSM Key 2"
|
|
group.long (d:0x40085000+0x2C)++0x03
|
|
line.long 0x00 "Z1_CSMKEY3,Zone 1 CSM Key 3"
|
|
group.long (d:0x40085000+0x30)++0x03
|
|
line.long 0x00 "Z1_CR,Zone 1 CSM Control Register"
|
|
bitfld.long 0x00 31. " FORCESEC ,Force Secure" "0,1"
|
|
rbitfld.long 0x00 22. " ARMED ,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x00 21. " UNSECURE ,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x00 20. " ALLONE ,CSMPSWD All Ones" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. " ALLZERO ,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long (d:0x40085000+0x34)++0x03
|
|
line.long 0x00 "Z1_GRABSECT1R,Zone 1 Grab Flash Status Register 1"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x38)++0x03
|
|
line.long 0x00 "Z1_GRABSECT2R,Zone 1 Grab Flash Status Register 2"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x3C)++0x03
|
|
line.long 0x00 "Z1_GRABSECT3R,Zone 1 Grab Flash Status Register 3"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x40)++0x03
|
|
line.long 0x00 "Z1_GRABRAM1R,Zone 1 Grab RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x44)++0x03
|
|
line.long 0x00 "Z1_GRABRAM2R,Zone 1 Grab RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " GRAB_RAM15 ,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GRAB_RAM14 ,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GRAB_RAM13 ,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_RAM12 ,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GRAB_RAM11 ,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_RAM10 ,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x48)++0x03
|
|
line.long 0x00 "Z1_GRABRAM3R,Zone 1 Grab RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085000+0x4C)++0x03
|
|
line.long 0x00 "Z1_EXEONLYSECT1R,Zone 1 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x00 29. " EXEONLY_CM_SECT13 ,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_CM_SECT12 ,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 27. " EXEONLY_CM_SECT11 ,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_CM_SECT10 ,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " EXEONLY_CM_SECT9 ,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_CM_SECT8 ,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 23. " EXEONLY_CM_SECT7 ,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_CM_SECT6 ,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " EXEONLY_CM_SECT5 ,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 20. " EXEONLY_CM_SECT4 ,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 19. " EXEONLY_CM_SECT3 ,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 18. " EXEONLY_CM_SECT2 ,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " EXEONLY_CM_SECT1 ,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_CM_SECT0 ,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU1_SECT13 ,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU1_SECT12 ,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EXEONLY_CPU1_SECT11 ,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU1_SECT10 ,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 9. " EXEONLY_CPU1_SECT9 ,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU1_SECT8 ,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EXEONLY_CPU1_SECT7 ,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU1_SECT6 ,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 5. " EXEONLY_CPU1_SECT5 ,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU1_SECT4 ,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EXEONLY_CPU1_SECT3 ,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU1_SECT2 ,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 1. " EXEONLY_CPU1_SECT1 ,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU1_SECT0 ,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
rgroup.long (d:0x40085000+0x50)++0x03
|
|
line.long 0x00 "Z1_EXEONLYSECT2R,Zone 1 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU2_SECT13 ,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU2_SECT12 ,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 11. " EXEONLY_CPU2_SECT11 ,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU2_SECT10 ,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_CPU2_SECT9 ,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU2_SECT8 ,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_CPU2_SECT7 ,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU2_SECT6 ,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_CPU2_SECT5 ,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU2_SECT4 ,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_CPU2_SECT3 ,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU2_SECT2 ,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_CPU2_SECT1 ,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU2_SECT0 ,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
rgroup.long (d:0x40085000+0x54)++0x03
|
|
line.long 0x00 "Z1_EXEONLYRAM1R,Zone 1 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x00 31. " EXEONLY_RAM31 ,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x00 30. " EXEONLY_RAM30 ,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x00 29. " EXEONLY_RAM29 ,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_RAM28 ,Execute-Only RAM CPU2.LS3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " EXEONLY_RAM27 ,Execute-Only RAM CPU2.LS4" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_RAM26 ,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x00 25. " EXEONLY_RAM25 ,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_RAM24 ,Execute-Only RAM CPU2.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " EXEONLY_RAM23 ,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_RAM22 ,Execute-Only RAM CPU2.D1" "0,1"
|
|
bitfld.long 0x00 17. " EXEONLY_RAM17 ,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_RAM16 ,Execute-Only RAM on CM.C0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_RAM9 ,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_RAM8 ,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_RAM7 ,Execute-Only RAM CPU1.LS7" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_RAM6 ,Execute-Only RAM CPU1.LS6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_RAM5 ,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_RAM4 ,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_RAM3 ,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_RAM2 ,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_RAM1 ,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_RAM0 ,Execute-Only RAM CPU1.LS0" "0,1"
|
|
rgroup.long (d:0x40085000+0x5C)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY0,JTAG Unlock Key Register 0"
|
|
rgroup.long (d:0x40085000+0x60)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY1,JTAG Unlock Key Register 1"
|
|
rgroup.long (d:0x40085000+0x64)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY2,JTAG Unlock Key Register 2"
|
|
rgroup.long (d:0x40085000+0x68)++0x03
|
|
line.long 0x00 "Z1_JTAGKEY3,JTAG Unlock Key Register 3"
|
|
rgroup.long (d:0x40085000+0x6C)++0x03
|
|
line.long 0x00 "Z1_CMACKEY0,Secure Boot CMAC Key Status Register 0"
|
|
rgroup.long (d:0x40085000+0x70)++0x03
|
|
line.long 0x00 "Z1_CMACKEY1,Secure Boot CMAC Key Status Register 1"
|
|
rgroup.long (d:0x40085000+0x74)++0x03
|
|
line.long 0x00 "Z1_CMACKEY2,Secure Boot CMAC Key Status Register 2"
|
|
rgroup.long (d:0x40085000+0x78)++0x03
|
|
line.long 0x00 "Z1_CMACKEY3,Secure Boot CMAC Key Status Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Zone 2"
|
|
width 19.
|
|
rgroup.long (d:0x40085100+0x00)++0x03
|
|
line.long 0x00 "Z2_LINKPOINTER,Zone 2 Link Pointer"
|
|
hexmask.long 0x00 0.--13. 1. "LINKPOINTER,Zone2 LINK Pointer"
|
|
rgroup.long (d:0x40085100+0x04)++0x03
|
|
line.long 0x00 "Z2_OTPSECLOCK,Zone 2 OTP Secure Lock"
|
|
bitfld.long 0x00 8.--11. " CRCLOCK ,Zone2 CRC Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PSWDLOCK ,Zone2 Password Lock." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " JTAGLOCK ,JTAG Lock Status" "0,1"
|
|
rgroup.long (d:0x40085100+0x0C)++0x03
|
|
line.long 0x00 "Z2_LINKPOINTERERR,Link Pointer Error"
|
|
hexmask.long 0x00 0.--13. 1. "Z2_LINKPOINTERERR,Error to Resolve Z2 Link pointer from OTP loaded values"
|
|
rgroup.long (d:0x40085100+0x10)++0x03
|
|
line.long 0x00 "Z2_GPREG1,Zone 2 General Purpose Register-1"
|
|
rgroup.long (d:0x40085100+0x14)++0x03
|
|
line.long 0x00 "Z2_GPREG2,Zone 2 General Purpose Register-2"
|
|
rgroup.long (d:0x40085100+0x18)++0x03
|
|
line.long 0x00 "Z2_GPREG3,Zone 2 General Purpose Register-3"
|
|
rgroup.long (d:0x40085100+0x1C)++0x03
|
|
line.long 0x00 "Z2_GPREG4,Zone 2 General Purpose Register-4"
|
|
group.long (d:0x40085100+0x20)++0x03
|
|
line.long 0x00 "Z2_CSMKEY0,Zone 2 CSM Key 0"
|
|
group.long (d:0x40085100+0x24)++0x03
|
|
line.long 0x00 "Z2_CSMKEY1,Zone 2 CSM Key 1"
|
|
group.long (d:0x40085100+0x28)++0x03
|
|
line.long 0x00 "Z2_CSMKEY2,Zone 2 CSM Key 2"
|
|
group.long (d:0x40085100+0x2C)++0x03
|
|
line.long 0x00 "Z2_CSMKEY3,Zone 2 CSM Key 3"
|
|
group.long (d:0x40085100+0x30)++0x03
|
|
line.long 0x00 "Z2_CR,Zone 2 CSM Control Register"
|
|
bitfld.long 0x00 31. " FORCESEC ,Force Secure" "0,1"
|
|
rbitfld.long 0x00 22. " ARMED ,CSM Passwords Read Status" "0,1"
|
|
rbitfld.long 0x00 21. " UNSECURE ,CSMPSWD Match CSMKEY" "0,1"
|
|
rbitfld.long 0x00 20. " ALLONE ,CSMPSWD All Ones" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. " ALLZERO ,CSMPSWD All Zeros" "0,1"
|
|
rgroup.long (d:0x40085100+0x34)++0x03
|
|
line.long 0x00 "Z2_GRABSECT1R,Zone 2 Grab Flash Status Register 1"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU1 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU1 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU1 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x38)++0x03
|
|
line.long 0x00 "Z2_GRABSECT2R,Zone 2 Grab Flash Status Register 2"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CM BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CM BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CM BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x3C)++0x03
|
|
line.long 0x00 "Z2_GRABSECT3R,Zone 2 Grab Flash Status Register 3"
|
|
bitfld.long 0x00 26.--27. " GRAB_SECT13 ,Grab Flash Sector 13 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_SECT12 ,Grab Flash Sector 12 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " GRAB_SECT11 ,Grab Flash Sector 11 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_SECT10 ,Grab Flash Sector 10 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " GRAB_SECT9 ,Grab Flash Sector 9 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_SECT8 ,Grab Flash Sector 8 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_SECT7 ,Grab Flash Sector 7 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_SECT6 ,Grab Flash Sector 6 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_SECT5 ,Grab Flash Sector 5 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_SECT4 ,Grab Flash Sector 4 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_SECT3 ,Grab Flash Sector 3 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_SECT2 ,Grab Flash Sector 2 in CPU2 BANK" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_SECT1 ,Grab Flash Sector 1 in CPU2 BANK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_SECT0 ,Grab Flash Sector 0 in CPU2 BANK" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x40)++0x03
|
|
line.long 0x00 "Z2_GRABRAM1R,Zone 2 Grab RAM Status Register 1"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU1.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU1.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU1.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU1.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU1.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU1.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU1.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU1.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x44)++0x03
|
|
line.long 0x00 "Z2_GRABRAM2R,Zone 2 Grab RAM Status Register 2"
|
|
bitfld.long 0x00 30.--31. " GRAB_RAM15 ,Grab RAM CPU2TOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " GRAB_RAM14 ,Grab RAM CPU2TOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. " GRAB_RAM13 ,Grab RAM CPU1TOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " GRAB_RAM12 ,Grab RAM CPU1TOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " GRAB_RAM11 ,Grab RAM CMTOCPU2 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " GRAB_RAM10 ,Grab RAM CMTOCPU2 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CMTOCPU1 MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CMTOCPU1 MSGRAM0_L" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU1TOCM MSGRAM0_H" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU1TOCM MSGRAM0_L" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CM.C1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CM.C0" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x48)++0x03
|
|
line.long 0x00 "Z2_GRABRAM3R,Zone 2 Grab RAM Status Register 3"
|
|
bitfld.long 0x00 18.--19. " GRAB_RAM9 ,Grab RAM CPU2.D1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " GRAB_RAM8 ,Grab RAM CPU2.D0" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " GRAB_RAM7 ,Grab RAM CPU2.LS7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " GRAB_RAM6 ,Grab RAM CPU2.LS6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " GRAB_RAM5 ,Grab RAM CPU2.LS5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GRAB_RAM4 ,Grab RAM CPU2.LS4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " GRAB_RAM3 ,Grab RAM CPU2.LS3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GRAB_RAM2 ,Grab RAM CPU2.LS2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " GRAB_RAM1 ,Grab RAM CPU2.LS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GRAB_RAM0 ,Grab RAM CPU2.LS0" "0,1,2,3"
|
|
rgroup.long (d:0x40085100+0x4C)++0x03
|
|
line.long 0x00 "Z2_EXEONLYSECT1R,Zone 2 Execute Only Flash Status Register 1"
|
|
bitfld.long 0x00 29. " EXEONLY_CM_SECT13 ,Execute-Only Flash Sector 13 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_CM_SECT12 ,Execute-Only Flash Sector 12 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 27. " EXEONLY_CM_SECT11 ,Execute-Only Flash Sector 11 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_CM_SECT10 ,Execute-Only Flash Sector 10 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " EXEONLY_CM_SECT9 ,Execute-Only Flash Sector 9 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_CM_SECT8 ,Execute-Only Flash Sector 8 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 23. " EXEONLY_CM_SECT7 ,Execute-Only Flash Sector 7 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_CM_SECT6 ,Execute-Only Flash Sector 6 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " EXEONLY_CM_SECT5 ,Execute-Only Flash Sector 5 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 20. " EXEONLY_CM_SECT4 ,Execute-Only Flash Sector 4 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 19. " EXEONLY_CM_SECT3 ,Execute-Only Flash Sector 3 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 18. " EXEONLY_CM_SECT2 ,Execute-Only Flash Sector 2 in flash CM BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " EXEONLY_CM_SECT1 ,Execute-Only Flash Sector 1 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_CM_SECT0 ,Execute-Only Flash Sector 0 in flash CM BANK" "0,1"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU1_SECT13 ,Execute-Only Flash Sector 13 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU1_SECT12 ,Execute-Only Flash Sector 12 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EXEONLY_CPU1_SECT11 ,Execute-Only Flash Sector 11 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU1_SECT10 ,Execute-Only Flash Sector 10 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 9. " EXEONLY_CPU1_SECT9 ,Execute-Only Flash Sector 9 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU1_SECT8 ,Execute-Only Flash Sector 8 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EXEONLY_CPU1_SECT7 ,Execute-Only Flash Sector 7 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU1_SECT6 ,Execute-Only Flash Sector 6 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 5. " EXEONLY_CPU1_SECT5 ,Execute-Only Flash Sector 5 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU1_SECT4 ,Execute-Only Flash Sector 4 in flash CPU1 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EXEONLY_CPU1_SECT3 ,Execute-Only Flash Sector 3 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU1_SECT2 ,Execute-Only Flash Sector 2 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 1. " EXEONLY_CPU1_SECT1 ,Execute-Only Flash Sector 1 in flash CPU1 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU1_SECT0 ,Execute-Only Flash Sector 0 in flash CPU1 BANK" "0,1"
|
|
rgroup.long (d:0x40085100+0x50)++0x03
|
|
line.long 0x00 "Z2_EXEONLYSECT2R,Zone 2 Execute Only Flash Status Register 2"
|
|
bitfld.long 0x00 13. " EXEONLY_CPU2_SECT13 ,Execute-Only Flash Sector 13 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 12. " EXEONLY_CPU2_SECT12 ,Execute-Only Flash Sector 12 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 11. " EXEONLY_CPU2_SECT11 ,Execute-Only Flash Sector 11 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 10. " EXEONLY_CPU2_SECT10 ,Execute-Only Flash Sector 10 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_CPU2_SECT9 ,Execute-Only Flash Sector 9 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_CPU2_SECT8 ,Execute-Only Flash Sector 8 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_CPU2_SECT7 ,Execute-Only Flash Sector 7 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_CPU2_SECT6 ,Execute-Only Flash Sector 6 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_CPU2_SECT5 ,Execute-Only Flash Sector 5 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_CPU2_SECT4 ,Execute-Only Flash Sector 4 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_CPU2_SECT3 ,Execute-Only Flash Sector 3 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_CPU2_SECT2 ,Execute-Only Flash Sector 2 in flash CPU2 BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_CPU2_SECT1 ,Execute-Only Flash Sector 1 in flash CPU2 BANK" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_CPU2_SECT0 ,Execute-Only Flash Sector 0 in flash CPU2 BANK" "0,1"
|
|
rgroup.long (d:0x40085100+0x54)++0x03
|
|
line.long 0x00 "Z2_EXEONLYRAM1R,Zone 2 Execute Only RAM Status Register 1"
|
|
bitfld.long 0x00 31. " EXEONLY_RAM31 ,Execute-Only RAM CPU2.LS0" "0,1"
|
|
bitfld.long 0x00 30. " EXEONLY_RAM30 ,Execute-Only RAM CPU2.LS1" "0,1"
|
|
bitfld.long 0x00 29. " EXEONLY_RAM29 ,Execute-Only RAM CPU2.LS2" "0,1"
|
|
bitfld.long 0x00 28. " EXEONLY_RAM28 ,Execute-Only RAM CPU2.LS3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " EXEONLY_RAM27 ,Execute-Only RAM CPU2.LS4" "0,1"
|
|
bitfld.long 0x00 26. " EXEONLY_RAM26 ,Execute-Only RAM CPU2.LS5" "0,1"
|
|
bitfld.long 0x00 25. " EXEONLY_RAM25 ,Execute-Only RAM CPU2.LS6" "0,1"
|
|
bitfld.long 0x00 24. " EXEONLY_RAM24 ,Execute-Only RAM CPU2.LS7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " EXEONLY_RAM23 ,Execute-Only RAM CPU2.D0" "0,1"
|
|
bitfld.long 0x00 22. " EXEONLY_RAM22 ,Execute-Only RAM CPU2.D1" "0,1"
|
|
bitfld.long 0x00 17. " EXEONLY_RAM17 ,Execute-Only RAM on CM.C1" "0,1"
|
|
bitfld.long 0x00 16. " EXEONLY_RAM16 ,Execute-Only RAM on CM.C0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " EXEONLY_RAM9 ,Execute-Only RAM CPU1.D1" "0,1"
|
|
bitfld.long 0x00 8. " EXEONLY_RAM8 ,Execute-Only RAM CPU1.D0" "0,1"
|
|
bitfld.long 0x00 7. " EXEONLY_RAM7 ,Execute-Only RAM CPU1.LS7" "0,1"
|
|
bitfld.long 0x00 6. " EXEONLY_RAM6 ,Execute-Only RAM CPU1.LS6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EXEONLY_RAM5 ,Execute-Only RAM CPU1.LS5" "0,1"
|
|
bitfld.long 0x00 4. " EXEONLY_RAM4 ,Execute-Only RAM CPU1.LS4" "0,1"
|
|
bitfld.long 0x00 3. " EXEONLY_RAM3 ,Execute-Only RAM CPU1.LS3" "0,1"
|
|
bitfld.long 0x00 2. " EXEONLY_RAM2 ,Execute-Only RAM CPU1.LS2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " EXEONLY_RAM1 ,Execute-Only RAM CPU1.LS1" "0,1"
|
|
bitfld.long 0x00 0. " EXEONLY_RAM0 ,Execute-Only RAM CPU1.LS0" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("F28388?-CM")
|
|
tree "EtherCAT Slave Controller (ESC)"
|
|
tree "ESCSS"
|
|
width 25.
|
|
rgroup.long (d:0x400AFC00+0x00)++0x03
|
|
line.long 0x00 "ESCSS_IPREVNUM,IP Revision Number"
|
|
bitfld.long 0x00 4.--7. " IP_REV_MAJOR ,Major IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IP_REV_MINOR ,Minor IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x400AFC00+0x04)++0x03
|
|
line.long 0x00 "ESCSS_INTR_RIS,EtherCATSS Interrupt Raw Status"
|
|
bitfld.long 0x00 5. " MASTER_RESET_RIS ,ECAT RESET RIS" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_RIS ,PDI bus Timeout Error RIS" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_RIS ,DMA Done RIS" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_RIS ,EtherCATSS IRQ RIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_RIS ,SYNC1 feature RIS" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_RIS ,SYNC0 feature RIS" "0,1"
|
|
group.long (d:0x400AFC00+0x08)++0x03
|
|
line.long 0x00 "ESCSS_INTR_MASK,EtherCATSS Interrupt Mask"
|
|
bitfld.long 0x00 5. " MASTER_RESET_MASK ,EtherCAT Master Reset Mask" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_MASK ,PDI Access Timeout Error Mask" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_MASK ,DMA Done Mask" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_MASK ,EtherCATSS IRQ Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_MASK ,SYNC1 feature Mask" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_MASK ,SYNC0 feature Mask" "0,1"
|
|
rgroup.long (d:0x400AFC00+0x0C)++0x03
|
|
line.long 0x00 "ESCSS_INTR_MIS,EtherCATSS Masked Interrupt Status"
|
|
bitfld.long 0x00 5. " MASTER_RESET_MIS ,EtherCAT Master Reset MIS" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_MIS ,PDI bus Timeout Error MIS" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_MIS ,DMA Done MIS" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_MIS ,EtherCATSS IRQ MIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_MIS ,SYNC1 feature MIS" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_MIS ,SYNC0 feature MIS" "0,1"
|
|
group.long (d:0x400AFC00+0x10)++0x03
|
|
line.long 0x00 "ESCSS_INTR_CLR,EtherCATSS Interrupt Clear"
|
|
bitfld.long 0x00 5. " MASTER_RESET_CLR ,EtherCAT Master Reset Clear" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_CLR ,PDI Access Timeout Error Clear" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_CLR ,DMA Done Clear" "0,1"
|
|
bitfld.long 0x00 2. " IRQ_CLR ,EtherCATSS IRQ Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " SYNC1_CLR ,SYNC1 feature Clear" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_CLR ,SYNC0 feature Clear" "0,1"
|
|
group.long (d:0x400AFC00+0x14)++0x03
|
|
line.long 0x00 "ESCSS_INTR_SET,EtherCATSS Interrupt Set to emulate"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 5. " MASTER_RESET_SET ,EtherCAT Master Reset Emulate" "0,1"
|
|
bitfld.long 0x00 4. " TIMEOUT_ERR_SET ,PDI Access Timeout Error Set Emulate" "0,1"
|
|
bitfld.long 0x00 3. " DMA_DONE_SET ,DMA Done Set Emulate" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " IRQ_SET ,EtherCATSS IRQ Set Emulate" "0,1"
|
|
bitfld.long 0x00 1. " SYNC1_SET ,SYNC1 Set Emulate" "0,1"
|
|
bitfld.long 0x00 0. " SYNC0_SET ,SYNC0 Set Emulate" "0,1"
|
|
group.long (d:0x400AFC00+0x18)++0x03
|
|
line.long 0x00 "ESCSS_LATCH_SEL,Select for Latch0/1 inputs and LATCHIN input"
|
|
bitfld.long 0x00 8.--12. " LATCH1_SELECT ,LATCH1 Inputs mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " LATCH0_SELECT ,LATCH0 Inputs mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x400AFC00+0x1C)++0x03
|
|
line.long 0x00 "ESCSS_ACCESS_CTRL,PDI interface access control config."
|
|
hexmask.long 0x00 16.--27. 1. "TIMEOUT_COUNT,Max timecount programmed and count while enabled."
|
|
bitfld.long 0x00 10. " ENABLE_PARALLEL_PORT_ACCESS ,Parallel port access enable" "0,1"
|
|
bitfld.long 0x00 9. " ENABLE_DEBUG_ACCESS ,Debug access enable" "0,1"
|
|
bitfld.long 0x00 7. " EN_TIMEOUT ,PDI Timeout enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--6. " WAIT_STATES ,Minimum Wait States for VBUS Bridge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x400AFC00+0x20)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_DAT,GPIN data capture for debug and override"
|
|
group.long (d:0x400AFC00+0x24)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_PIPE,GPIN pipeline select"
|
|
group.long (d:0x400AFC00+0x28)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_GRP_CAP_SEL,GPIN pipe group capture trigger"
|
|
bitfld.long 0x00 12.--14. " GPI_GRP_CAP_SEL3 ,GPI31-24 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " GPI_GRP_CAP_SEL2 ,GPI23-16 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " GPI_GRP_CAP_SEL1 ,GPI15-8 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " GPI_GRP_CAP_SEL0 ,GPI7-0 capture trigger select" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x400AFC00+0x2C)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_DAT,GPOUT data capture for debug and override"
|
|
group.long (d:0x400AFC00+0x30)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_PIPE,GPOUT pipeline select"
|
|
group.long (d:0x400AFC00+0x34)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_GRP_CAP_SEL,GPOUT pipe group capture trigger"
|
|
bitfld.long 0x00 12.--13. " GPO_GRP_CAP_SEL3 ,GPO31-24 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " GPO_GRP_CAP_SEL2 ,GPO23-16 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " GPO_GRP_CAP_SEL1 ,GPO15-8 capture trigger select" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " GPO_GRP_CAP_SEL0 ,GPO7-0 capture trigger select" "0,1,2,3"
|
|
group.long (d:0x400AFC00+0x38)++0x03
|
|
line.long 0x00 "ESCSS_MEM_TEST,Memory Test Control"
|
|
rbitfld.long 0x00 1. " MEM_INIT_DONE ,Memory Init done status" "0,1"
|
|
bitfld.long 0x00 0. " INITIATE_MEM_INIT ,Initialize memory init" "0,1"
|
|
group.long (d:0x400AFC00+0x3C)++0x03
|
|
line.long 0x00 "ESCSS_RESET_DEST_CONFIG,ResetOut impact or destination config"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " DEVICE_RESET_EN ,Enables RESET_OUT to impact the device reset" "0,1"
|
|
bitfld.long 0x00 2. " CPU_INT_EN ,CPU Interrupt enable for ResetOut" "0,1"
|
|
bitfld.long 0x00 1. " CPU_NMI_EN ,CPU NMI enable for ResetOut" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " CPU_RESET_EN ,CPU reset enable for ResetOut" "0,1"
|
|
group.long (d:0x400AFC00+0x40)++0x03
|
|
line.long 0x00 "ESCSS_SYNC0_CONFIG,SYNC0 Configuration for various triggers"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " uDMA_TRIG_EN ,Connects the SYNC0 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x00 3. " CM4_NVIC_EN ,Connects the SYNC0 to CM4 NVIC Interrupt" "0,1"
|
|
bitfld.long 0x00 2. " C28x_DMA_EN ,Connects the SYNC0 to C28x DMA Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CLA_INT_EN ,Connects the SYNC0 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x00 0. " C28x_PIE_EN ,Connects the SYNC0 to C28x PIE Interrupt" "0,1"
|
|
group.long (d:0x400AFC00+0x44)++0x03
|
|
line.long 0x00 "ESCSS_SYNC1_CONFIG,SYNC1 Configuration for various triggers"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " uDMA_TRIG_EN ,Connects the SYNC1 to uDMA Trigger" "0,1"
|
|
bitfld.long 0x00 3. " CM4_NVIC_EN ,Connects the SYNC1 to CM4 NVIC Interrupt" "0,1"
|
|
bitfld.long 0x00 2. " C28x_DMA_EN ,Connects the SYNC1 to C28x DMA Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CLA_INT_EN ,Connects the SYNC1 to CLA Interrupt" "0,1"
|
|
bitfld.long 0x00 0. " C28x_PIE_EN ,Connects the SYNC1 to C28x PIE Interrupt" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ESCSSCONFIG"
|
|
width 23.
|
|
group.long (d:0x400AFE00+0x00)++0x03
|
|
line.long 0x00 "ESCSS_CONFIG_LOCK,EtherCATSS Configuration Lock"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 4. " IO_CONFIG_ENABLE ,Locking the IO Configuration" "0,1"
|
|
bitfld.long 0x00 0. " LOCK_ENABLE ,Locking writes to ECATSS" "0,1"
|
|
group.long (d:0x400AFE00+0x04)++0x03
|
|
line.long 0x00 "ESCSS_MISC_IO_CONFIG,RESET_IN, EEPROM IO connections select"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 1. " EEPROM_I2C_IO_EN ,Enables the EEPROM I2C IOPAD connection" "0,1"
|
|
bitfld.long 0x00 0. " RESETIN_GPIO_EN ,Enabled ResetIN from GPIO" "0,1"
|
|
group.long (d:0x400AFE00+0x08)++0x03
|
|
line.long 0x00 "ESCSS_PHY_IO_CONFIG,Control Register of ESCSS"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 6. " TX_CLK_AUTO_COMP ,Selects TX_CLK IO to do Auto compensation" "0,1"
|
|
bitfld.long 0x00 4.--5. " PHY_INTF_IOPAD_SEL ,IO Combination select for PHY Interface" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " PHY_PORT_CNT ,Number of PHY port counts" "0,1,2,3"
|
|
group.long (d:0x400AFE00+0x0C)++0x03
|
|
line.long 0x00 "ESCSS_SYNC_IO_CONFIG,SYNC Signals IO configurations"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " SYNC1_GPIO_EN ,SYNC1 connection to OUT pad enabled" "0,1"
|
|
bitfld.long 0x00 4.--5. " SYNC1_IOPAD_SEL ,SYNC1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SYNC0_GPIO_EN ,SYNC0 connection to OUT pad enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SYNC0_IOPAD_SEL ,SYNC0 IO PAD select option" "0,1,2,3"
|
|
group.long (d:0x400AFE00+0x10)++0x03
|
|
line.long 0x00 "ESCSS_LATCH_IO_CONFIG,LATCH inputs IO pad select"
|
|
hexmask.long 0x00 8.--15. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 7. " LATCH1_GPIO_EN ,LATCH1 connection to IN pad enabled" "0,1"
|
|
bitfld.long 0x00 4.--5. " LATCH1_IOPAD_SEL ,LATCH1 IO PAD select option" "0,1,2,3"
|
|
bitfld.long 0x00 3. " LATCH0_GPIO_EN ,LATCH0 connection to IN pad enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " LATCH0_IOPAD_SEL ,LATCH0 IO PAD select option" "0,1,2,3"
|
|
group.long (d:0x400AFE00+0x14)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_SEL,GPIN Select between IO PAD and tieoff"
|
|
group.long (d:0x400AFE00+0x18)++0x03
|
|
line.long 0x00 "ESCSS_GPIN_IOPAD_SEL,GPIN IO pad Select"
|
|
group.long (d:0x400AFE00+0x1C)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_SEL,GPOUT IO pad connect select"
|
|
group.long (d:0x400AFE00+0x20)++0x03
|
|
line.long 0x00 "ESCSS_GPOUT_IOPAD_SEL,GPOUT IO pad select"
|
|
group.long (d:0x400AFE00+0x24)++0x03
|
|
line.long 0x00 "ESCSS_LED_CONFIG,Selection of LED o/p connect to IO pad"
|
|
bitfld.long 0x00 14.--15. " RUN_IOPAD_SEL ,RUN LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " ERR_IOPAD_SEL ,ERROR LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " STATE_IOPAD_SEL ,STATE LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " LINKACT1_IOPAD_SEL ,LINKACT1 LED IO PAD select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " LINKACT0_IOPAD_SEL ,LINKACT0 LED IO PAD select" "0,1,2,3"
|
|
bitfld.long 0x00 4. " RUN ,GPIO enable for RUN LED" "0,1"
|
|
bitfld.long 0x00 3. " ERR ,GPIO enable for ERR LED" "0,1"
|
|
bitfld.long 0x00 2. " STATE ,GPIO enable for STATE LED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " LINKACT1 ,GPIO enable for LINKACT1 LED" "0,1"
|
|
bitfld.long 0x00 0. " LINKACT0 ,GPIO enable for LINKACT0 LED" "0,1"
|
|
group.long (d:0x400AFE00+0x28)++0x03
|
|
line.long 0x00 "ESCSS_MISC_CONFIG,Miscelleneous Configuration"
|
|
bitfld.long 0x00 6.--10. " PHY_ADDR ,PHY Address Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " PDI_EMULATION ,PDI Emulation enable" "0,1"
|
|
bitfld.long 0x00 4. " EEPROM_SIZE ,EEPROM Size bound select" "0,1"
|
|
bitfld.long 0x00 2.--3. " TX1_SHIFT_CONFIG ,TX Shift configuration for Port1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TX0_SHIFT_CONFIG ,TX Shift configuration for Port0" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "Ethernet Media Access Controller (EMAC)"
|
|
tree "ETHERNET"
|
|
width 39.
|
|
hgroup.long (d:0x400C0000+0x00)++0x03
|
|
hide.long 0x00 "MAC_Configuration,MAC_Configuration"
|
|
hgroup.long (d:0x400C0000+0x04)++0x03
|
|
hide.long 0x00 "MAC_Ext_Configuration,MAC_Ext_Configuration"
|
|
hgroup.long (d:0x400C0000+0x08)++0x03
|
|
hide.long 0x00 "MAC_Packet_Filter,MAC_Packet_Filter"
|
|
hgroup.long (d:0x400C0000+0x0C)++0x03
|
|
hide.long 0x00 "MAC_Watchdog_Timeout,MAC_Watchdog_Timeout"
|
|
hgroup.long (d:0x400C0000+0x10)++0x03
|
|
hide.long 0x00 "MAC_Hash_Table_Reg0,MAC_Hash_Table_Reg0"
|
|
hgroup.long (d:0x400C0000+0x14)++0x03
|
|
hide.long 0x00 "MAC_Hash_Table_Reg1,MAC_Hash_Table_Reg1"
|
|
hgroup.long (d:0x400C0000+0x50)++0x03
|
|
hide.long 0x00 "MAC_VLAN_Tag_Ctrl,MAC_VLAN_Tag_Ctrl"
|
|
hgroup.long (d:0x400C0000+0x54)++0x03
|
|
hide.long 0x00 "MAC_VLAN_Tag_Data,MAC_VLAN_Tag_Data"
|
|
hgroup.long (d:0x400C0000+0x58)++0x03
|
|
hide.long 0x00 "MAC_VLAN_Hash_Table,MAC_VLAN_Hash_Table"
|
|
hgroup.long (d:0x400C0000+0x60)++0x03
|
|
hide.long 0x00 "MAC_VLAN_Incl,MAC_VLAN_Incl"
|
|
hgroup.long (d:0x400C0000+0x64)++0x03
|
|
hide.long 0x00 "MAC_Inner_VLAN_Incl,MAC_Inner_VLAN_Incl"
|
|
hgroup.long (d:0x400C0000+0x70)++0x03
|
|
hide.long 0x00 "MAC_Q0_Tx_Flow_Ctrl,MAC_Q0_Tx_Flow_Ctrl"
|
|
hgroup.long (d:0x400C0000+0x90)++0x03
|
|
hide.long 0x00 "MAC_Rx_Flow_Ctrl,MAC_Rx_Flow_Ctrl"
|
|
hgroup.long (d:0x400C0000+0x94)++0x03
|
|
hide.long 0x00 "MAC_RxQ_Ctrl4,MAC_RxQ_Ctrl4"
|
|
hgroup.long (d:0x400C0000+0xA0)++0x03
|
|
hide.long 0x00 "MAC_RxQ_Ctrl0,MAC_RxQ_Ctrl0"
|
|
hgroup.long (d:0x400C0000+0xA4)++0x03
|
|
hide.long 0x00 "MAC_RxQ_Ctrl1,MAC_RxQ_Ctrl1"
|
|
hgroup.long (d:0x400C0000+0xA8)++0x03
|
|
hide.long 0x00 "MAC_RxQ_Ctrl2,MAC_RxQ_Ctrl2"
|
|
hgroup.long (d:0x400C0000+0xB0)++0x03
|
|
hide.long 0x00 "MAC_Interrupt_Status,MAC_Interrupt_Status"
|
|
hgroup.long (d:0x400C0000+0xB4)++0x03
|
|
hide.long 0x00 "MAC_Interrupt_Enable,MAC_Interrupt_Enable"
|
|
hgroup.long (d:0x400C0000+0xB8)++0x03
|
|
hide.long 0x00 "MAC_Rx_Tx_Status,MAC_Rx_Tx_Status"
|
|
hgroup.long (d:0x400C0000+0xC0)++0x03
|
|
hide.long 0x00 "MAC_PMT_Control_Status,MAC_PMT_Control_Status"
|
|
hgroup.long (d:0x400C0000+0xC4)++0x03
|
|
hide.long 0x00 "MAC_RWK_Packet_Filter,MAC_RWK_Packet_Filter"
|
|
hgroup.long (d:0x400C0000+0xD0)++0x03
|
|
hide.long 0x00 "MAC_LPI_Control_Status,MAC_LPI_Control_Status"
|
|
hgroup.long (d:0x400C0000+0xD4)++0x03
|
|
hide.long 0x00 "MAC_LPI_Timers_Control,MAC_LPI_Timers_Control"
|
|
hgroup.long (d:0x400C0000+0xD8)++0x03
|
|
hide.long 0x00 "MAC_LPI_Entry_Timer,MAC_LPI_Entry_Timer"
|
|
hgroup.long (d:0x400C0000+0xDC)++0x03
|
|
hide.long 0x00 "MAC_1US_Tic_Counter,MAC_1US_Tic_Counter"
|
|
hgroup.long (d:0x400C0000+0x110)++0x03
|
|
hide.long 0x00 "MAC_Version,MAC_Version"
|
|
hgroup.long (d:0x400C0000+0x114)++0x03
|
|
hide.long 0x00 "MAC_Debug,MAC_Debug"
|
|
hgroup.long (d:0x400C0000+0x11C)++0x03
|
|
hide.long 0x00 "MAC_HW_Feature0,MAC_HW_Feature0"
|
|
hgroup.long (d:0x400C0000+0x120)++0x03
|
|
hide.long 0x00 "MAC_HW_Feature1,MAC_HW_Feature1"
|
|
hgroup.long (d:0x400C0000+0x124)++0x03
|
|
hide.long 0x00 "MAC_HW_Feature2,MAC_HW_Feature2"
|
|
hgroup.long (d:0x400C0000+0x128)++0x03
|
|
hide.long 0x00 "MAC_HW_Feature3,MAC_HW_Feature3"
|
|
hgroup.long (d:0x400C0000+0x200)++0x03
|
|
hide.long 0x00 "MAC_MDIO_Address,MAC_MDIO_Address"
|
|
hgroup.long (d:0x400C0000+0x204)++0x03
|
|
hide.long 0x00 "MAC_MDIO_Data,MAC_MDIO_Data"
|
|
hgroup.long (d:0x400C0000+0x210)++0x03
|
|
hide.long 0x00 "MAC_ARP_Address,MAC_ARP_Address"
|
|
hgroup.long (d:0x400C0000+0x230)++0x03
|
|
hide.long 0x00 "MAC_CSR_SW_Ctrl,MAC_CSR_SW_Ctrl"
|
|
hgroup.long (d:0x400C0000+0x238)++0x03
|
|
hide.long 0x00 "MAC_Ext_Cfg1,MAC_Ext_Cfg1"
|
|
hgroup.long (d:0x400C0000+0x300)++0x03
|
|
hide.long 0x00 "MAC_Address0_High,MAC_Address0_High"
|
|
hgroup.long (d:0x400C0000+0x304)++0x03
|
|
hide.long 0x00 "MAC_Address0_Low,MAC_Address0_Low"
|
|
hgroup.long (d:0x400C0000+0x308)++0x03
|
|
hide.long 0x00 "MAC_Address1_High,MAC_Address1_High"
|
|
hgroup.long (d:0x400C0000+0x30C)++0x03
|
|
hide.long 0x00 "MAC_Address1_Low,MAC_Address1_Low"
|
|
hgroup.long (d:0x400C0000+0x310)++0x03
|
|
hide.long 0x00 "MAC_Address2_High,MAC_Address2_High"
|
|
hgroup.long (d:0x400C0000+0x314)++0x03
|
|
hide.long 0x00 "MAC_Address2_Low,MAC_Address2_Low"
|
|
hgroup.long (d:0x400C0000+0x318)++0x03
|
|
hide.long 0x00 "MAC_Address3_High,MAC_Address3_High"
|
|
hgroup.long (d:0x400C0000+0x31C)++0x03
|
|
hide.long 0x00 "MAC_Address3_Low,MAC_Address3_Low"
|
|
hgroup.long (d:0x400C0000+0x320)++0x03
|
|
hide.long 0x00 "MAC_Address4_High,MAC_Address4_High"
|
|
hgroup.long (d:0x400C0000+0x324)++0x03
|
|
hide.long 0x00 "MAC_Address4_Low,MAC_Address4_Low"
|
|
hgroup.long (d:0x400C0000+0x328)++0x03
|
|
hide.long 0x00 "MAC_Address5_High,MAC_Address5_High"
|
|
hgroup.long (d:0x400C0000+0x32C)++0x03
|
|
hide.long 0x00 "MAC_Address5_Low,MAC_Address5_Low"
|
|
hgroup.long (d:0x400C0000+0x330)++0x03
|
|
hide.long 0x00 "MAC_Address6_High,MAC_Address6_High"
|
|
hgroup.long (d:0x400C0000+0x334)++0x03
|
|
hide.long 0x00 "MAC_Address6_Low,MAC_Address6_Low"
|
|
hgroup.long (d:0x400C0000+0x338)++0x03
|
|
hide.long 0x00 "MAC_Address7_High,MAC_Address7_High"
|
|
hgroup.long (d:0x400C0000+0x33C)++0x03
|
|
hide.long 0x00 "MAC_Address7_Low,MAC_Address7_Low"
|
|
hgroup.long (d:0x400C0000+0x700)++0x03
|
|
hide.long 0x00 "MMC_Control,MMC_Control"
|
|
hgroup.long (d:0x400C0000+0x704)++0x03
|
|
hide.long 0x00 "MMC_Rx_Interrupt,MMC_Rx_Interrupt"
|
|
hgroup.long (d:0x400C0000+0x708)++0x03
|
|
hide.long 0x00 "MMC_Tx_Interrupt,MMC_Tx_Interrupt"
|
|
hgroup.long (d:0x400C0000+0x70C)++0x03
|
|
hide.long 0x00 "MMC_Rx_Interrupt_Mask,MMC_Rx_Interrupt_Mask"
|
|
hgroup.long (d:0x400C0000+0x710)++0x03
|
|
hide.long 0x00 "MMC_Tx_Interrupt_Mask,MMC_Tx_Interrupt_Mask"
|
|
hgroup.long (d:0x400C0000+0x714)++0x03
|
|
hide.long 0x00 "Tx_Octet_Count_Good_Bad,Tx_Octet_Count_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x718)++0x03
|
|
hide.long 0x00 "Tx_Packet_Count_Good_Bad,Tx_Packet_Count_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x71C)++0x03
|
|
hide.long 0x00 "Tx_Broadcast_Packets_Good,Tx_Broadcast_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x720)++0x03
|
|
hide.long 0x00 "Tx_Multicast_Packets_Good,Tx_Multicast_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x724)++0x03
|
|
hide.long 0x00 "Tx_64Octets_Packets_Good_Bad,Tx_64Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x728)++0x03
|
|
hide.long 0x00 "Tx_65To127Octets_Packets_Good_Bad,Tx_65To127Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x72C)++0x03
|
|
hide.long 0x00 "Tx_128To255Octets_Packets_Good_Bad,Tx_128To255Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x730)++0x03
|
|
hide.long 0x00 "Tx_256To511Octets_Packets_Good_Bad,Tx_256To511Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x734)++0x03
|
|
hide.long 0x00 "Tx_512To1023Octets_Packets_Good_Bad,Tx_512To1023Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x738)++0x03
|
|
hide.long 0x00 "Tx_1024ToMaxOctets_Packets_Good_Bad,Tx_1024ToMaxOctets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x73C)++0x03
|
|
hide.long 0x00 "Tx_Unicast_Packets_Good_Bad,Tx_Unicast_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x740)++0x03
|
|
hide.long 0x00 "Tx_Multicast_Packets_Good_Bad,Tx_Multicast_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x744)++0x03
|
|
hide.long 0x00 "Tx_Broadcast_Packets_Good_Bad,Tx_Broadcast_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x748)++0x03
|
|
hide.long 0x00 "Tx_Underflow_Error_Packets,Tx_Underflow_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x74C)++0x03
|
|
hide.long 0x00 "Tx_Single_Collision_Good_Packets,Tx_Single_Collision_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x750)++0x03
|
|
hide.long 0x00 "Tx_Multiple_Collision_Good_Packets,Tx_Multiple_Collision_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x754)++0x03
|
|
hide.long 0x00 "Tx_Deferred_Packets,Tx_Deferred_Packets"
|
|
hgroup.long (d:0x400C0000+0x758)++0x03
|
|
hide.long 0x00 "Tx_Late_Collision_Packets,Tx_Late_Collision_Packets"
|
|
hgroup.long (d:0x400C0000+0x75C)++0x03
|
|
hide.long 0x00 "Tx_Excessive_Collision_Packets,Tx_Excessive_Collision_Packets"
|
|
hgroup.long (d:0x400C0000+0x760)++0x03
|
|
hide.long 0x00 "Tx_Carrier_Error_Packets,Tx_Carrier_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x764)++0x03
|
|
hide.long 0x00 "Tx_Octet_Count_Good,Tx_Octet_Count_Good"
|
|
hgroup.long (d:0x400C0000+0x768)++0x03
|
|
hide.long 0x00 "Tx_Packet_Count_Good,Tx_Packet_Count_Good"
|
|
hgroup.long (d:0x400C0000+0x76C)++0x03
|
|
hide.long 0x00 "Tx_Excessive_Deferral_Error,Tx_Excessive_Deferral_Error"
|
|
hgroup.long (d:0x400C0000+0x770)++0x03
|
|
hide.long 0x00 "Tx_Pause_Packets,Tx_Pause_Packets"
|
|
hgroup.long (d:0x400C0000+0x774)++0x03
|
|
hide.long 0x00 "Tx_VLAN_Packets_Good,Tx_VLAN_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x778)++0x03
|
|
hide.long 0x00 "Tx_OSize_Packets_Good,Tx_OSize_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x780)++0x03
|
|
hide.long 0x00 "Rx_Packets_Count_Good_Bad,Rx_Packets_Count_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x784)++0x03
|
|
hide.long 0x00 "Rx_Octet_Count_Good_Bad,Rx_Octet_Count_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x788)++0x03
|
|
hide.long 0x00 "Rx_Octet_Count_Good,Rx_Octet_Count_Good"
|
|
hgroup.long (d:0x400C0000+0x78C)++0x03
|
|
hide.long 0x00 "Rx_Broadcast_Packets_Good,Rx_Broadcast_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x790)++0x03
|
|
hide.long 0x00 "Rx_Multicast_Packets_Good,Rx_Multicast_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x794)++0x03
|
|
hide.long 0x00 "Rx_CRC_Error_Packets,Rx_CRC_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x798)++0x03
|
|
hide.long 0x00 "Rx_Alignment_Error_Packets,Rx_Alignment_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x79C)++0x03
|
|
hide.long 0x00 "Rx_Runt_Error_Packets,Rx_Runt_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x7A0)++0x03
|
|
hide.long 0x00 "Rx_Jabber_Error_Packets,Rx_Jabber_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x7A4)++0x03
|
|
hide.long 0x00 "Rx_Undersize_Packets_Good,Rx_Undersize_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x7A8)++0x03
|
|
hide.long 0x00 "Rx_Oversize_Packets_Good,Rx_Oversize_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x7AC)++0x03
|
|
hide.long 0x00 "Rx_64Octets_Packets_Good_Bad,Rx_64Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7B0)++0x03
|
|
hide.long 0x00 "Rx_65To127Octets_Packets_Good_Bad,Rx_65To127Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7B4)++0x03
|
|
hide.long 0x00 "Rx_128To255Octets_Packets_Good_Bad,Rx_128To255Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7B8)++0x03
|
|
hide.long 0x00 "Rx_256To511Octets_Packets_Good_Bad,Rx_256To511Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7BC)++0x03
|
|
hide.long 0x00 "Rx_512To1023Octets_Packets_Good_Bad,Rx_512To1023Octets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7C0)++0x03
|
|
hide.long 0x00 "Rx_1024ToMaxOctets_Packets_Good_Bad,Rx_1024ToMaxOctets_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7C4)++0x03
|
|
hide.long 0x00 "Rx_Unicast_Packets_Good,Rx_Unicast_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x7C8)++0x03
|
|
hide.long 0x00 "Rx_Length_Error_Packets,Rx_Length_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x7CC)++0x03
|
|
hide.long 0x00 "Rx_Out_Of_Range_Type_Packets,Rx_Out_Of_Range_Type_Packets"
|
|
hgroup.long (d:0x400C0000+0x7D0)++0x03
|
|
hide.long 0x00 "Rx_Pause_Packets,Rx_Pause_Packets"
|
|
hgroup.long (d:0x400C0000+0x7D4)++0x03
|
|
hide.long 0x00 "Rx_FIFO_Overflow_Packets,Rx_FIFO_Overflow_Packets"
|
|
hgroup.long (d:0x400C0000+0x7D8)++0x03
|
|
hide.long 0x00 "Rx_VLAN_Packets_Good_Bad,Rx_VLAN_Packets_Good_Bad"
|
|
hgroup.long (d:0x400C0000+0x7DC)++0x03
|
|
hide.long 0x00 "Rx_Watchdog_Error_Packets,Rx_Watchdog_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x7E0)++0x03
|
|
hide.long 0x00 "Rx_Receive_Error_Packets,Rx_Receive_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x7E4)++0x03
|
|
hide.long 0x00 "Rx_Control_Packets_Good,Rx_Control_Packets_Good"
|
|
hgroup.long (d:0x400C0000+0x7EC)++0x03
|
|
hide.long 0x00 "Tx_LPI_USEC_Cntr,Tx_LPI_USEC_Cntr"
|
|
hgroup.long (d:0x400C0000+0x7F0)++0x03
|
|
hide.long 0x00 "Tx_LPI_Tran_Cntr,Tx_LPI_Tran_Cntr"
|
|
hgroup.long (d:0x400C0000+0x7F4)++0x03
|
|
hide.long 0x00 "Rx_LPI_USEC_Cntr,Rx_LPI_USEC_Cntr"
|
|
hgroup.long (d:0x400C0000+0x7F8)++0x03
|
|
hide.long 0x00 "Rx_LPI_Tran_Cntr,Rx_LPI_Tran_Cntr"
|
|
hgroup.long (d:0x400C0000+0x800)++0x03
|
|
hide.long 0x00 "MMC_IPC_Rx_Interrupt_Mask,MMC_IPC_Rx_Interrupt_Mask"
|
|
hgroup.long (d:0x400C0000+0x808)++0x03
|
|
hide.long 0x00 "MMC_IPC_Rx_Interrupt,MMC_IPC_Rx_Interrupt"
|
|
hgroup.long (d:0x400C0000+0x810)++0x03
|
|
hide.long 0x00 "RxIPv4_Good_Packets,RxIPv4_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x814)++0x03
|
|
hide.long 0x00 "RxIPv4_Header_Error_Packets,RxIPv4_Header_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x818)++0x03
|
|
hide.long 0x00 "RxIPv4_No_Payload_Packets,RxIPv4_No_Payload_Packets"
|
|
hgroup.long (d:0x400C0000+0x81C)++0x03
|
|
hide.long 0x00 "RxIPv4_Fragmented_Packets,RxIPv4_Fragmented_Packets"
|
|
hgroup.long (d:0x400C0000+0x820)++0x03
|
|
hide.long 0x00 "RxIPv4_UDP_Checksum_Disabled_Packets,RxIPv4_UDP_Checksum_Disabled_Packets"
|
|
hgroup.long (d:0x400C0000+0x824)++0x03
|
|
hide.long 0x00 "RxIPv6_Good_Packets,RxIPv6_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x828)++0x03
|
|
hide.long 0x00 "RxIPv6_Header_Error_Packets,RxIPv6_Header_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x82C)++0x03
|
|
hide.long 0x00 "RxIPv6_No_Payload_Packets,RxIPv6_No_Payload_Packets"
|
|
hgroup.long (d:0x400C0000+0x830)++0x03
|
|
hide.long 0x00 "RxUDP_Good_Packets,RxUDP_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x834)++0x03
|
|
hide.long 0x00 "RxUDP_Error_Packets,RxUDP_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x838)++0x03
|
|
hide.long 0x00 "RxTCP_Good_Packets,RxTCP_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x83C)++0x03
|
|
hide.long 0x00 "RxTCP_Error_Packets,RxTCP_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x840)++0x03
|
|
hide.long 0x00 "RxICMP_Good_Packets,RxICMP_Good_Packets"
|
|
hgroup.long (d:0x400C0000+0x844)++0x03
|
|
hide.long 0x00 "RxICMP_Error_Packets,RxICMP_Error_Packets"
|
|
hgroup.long (d:0x400C0000+0x850)++0x03
|
|
hide.long 0x00 "RxIPv4_Good_Octets,RxIPv4_Good_Octets"
|
|
hgroup.long (d:0x400C0000+0x854)++0x03
|
|
hide.long 0x00 "RxIPv4_Header_Error_Octets,RxIPv4_Header_Error_Octets"
|
|
hgroup.long (d:0x400C0000+0x858)++0x03
|
|
hide.long 0x00 "RxIPv4_No_Payload_Octets,RxIPv4_No_Payload_Octets"
|
|
hgroup.long (d:0x400C0000+0x85C)++0x03
|
|
hide.long 0x00 "RxIPv4_Fragmented_Octets,RxIPv4_Fragmented_Octets"
|
|
hgroup.long (d:0x400C0000+0x860)++0x03
|
|
hide.long 0x00 "RxIPv4_UDP_Checksum_Disable_Octets,RxIPv4_UDP_Checksum_Disable_Octets"
|
|
hgroup.long (d:0x400C0000+0x864)++0x03
|
|
hide.long 0x00 "RxIPv6_Good_Octets,RxIPv6_Good_Octets"
|
|
hgroup.long (d:0x400C0000+0x868)++0x03
|
|
hide.long 0x00 "RxIPv6_Header_Error_Octets,RxIPv6_Header_Error_Octets"
|
|
hgroup.long (d:0x400C0000+0x86C)++0x03
|
|
hide.long 0x00 "RxIPv6_No_Payload_Octets,RxIPv6_No_Payload_Octets"
|
|
hgroup.long (d:0x400C0000+0x870)++0x03
|
|
hide.long 0x00 "RxUDP_Good_Octets,RxUDP_Good_Octets"
|
|
hgroup.long (d:0x400C0000+0x874)++0x03
|
|
hide.long 0x00 "RxUDP_Error_Octets,RxUDP_Error_Octets"
|
|
hgroup.long (d:0x400C0000+0x878)++0x03
|
|
hide.long 0x00 "RxTCP_Good_Octets,RxTCP_Good_Octets"
|
|
hgroup.long (d:0x400C0000+0x87C)++0x03
|
|
hide.long 0x00 "RxTCP_Error_Octets,RxTCP_Error_Octets"
|
|
hgroup.long (d:0x400C0000+0x880)++0x03
|
|
hide.long 0x00 "RxICMP_Good_Octets,RxICMP_Good_Octets"
|
|
hgroup.long (d:0x400C0000+0x884)++0x03
|
|
hide.long 0x00 "RxICMP_Error_Octets,RxICMP_Error_Octets"
|
|
hgroup.long (d:0x400C0000+0x900)++0x03
|
|
hide.long 0x00 "MAC_L3_L4_Control0,MAC_L3_L4_Control0"
|
|
hgroup.long (d:0x400C0000+0x904)++0x03
|
|
hide.long 0x00 "MAC_Layer4_Address0,MAC_Layer4_Address0"
|
|
hgroup.long (d:0x400C0000+0x910)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr0_Reg0,MAC_Layer3_Addr0_Reg0"
|
|
hgroup.long (d:0x400C0000+0x914)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr1_Reg0,MAC_Layer3_Addr1_Reg0"
|
|
hgroup.long (d:0x400C0000+0x918)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr2_Reg0,MAC_Layer3_Addr2_Reg0"
|
|
hgroup.long (d:0x400C0000+0x91C)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr3_Reg0,MAC_Layer3_Addr3_Reg0"
|
|
hgroup.long (d:0x400C0000+0x930)++0x03
|
|
hide.long 0x00 "MAC_L3_L4_Control1,MAC_L3_L4_Control1"
|
|
hgroup.long (d:0x400C0000+0x934)++0x03
|
|
hide.long 0x00 "MAC_Layer4_Address1,MAC_Layer4_Address1"
|
|
hgroup.long (d:0x400C0000+0x940)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr0_Reg1,MAC_Layer3_Addr0_Reg1"
|
|
hgroup.long (d:0x400C0000+0x944)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr1_Reg1,MAC_Layer3_Addr1_Reg1"
|
|
hgroup.long (d:0x400C0000+0x948)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr2_Reg1,MAC_Layer3_Addr2_Reg1"
|
|
hgroup.long (d:0x400C0000+0x94C)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr3_Reg1,MAC_Layer3_Addr3_Reg1"
|
|
hgroup.long (d:0x400C0000+0x960)++0x03
|
|
hide.long 0x00 "MAC_L3_L4_Control2,MAC_L3_L4_Control2"
|
|
hgroup.long (d:0x400C0000+0x964)++0x03
|
|
hide.long 0x00 "MAC_Layer4_Address2,MAC_Layer4_Address2"
|
|
hgroup.long (d:0x400C0000+0x970)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr0_Reg2,MAC_Layer3_Addr0_Reg2"
|
|
hgroup.long (d:0x400C0000+0x974)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr1_Reg2,MAC_Layer3_Addr1_Reg2"
|
|
hgroup.long (d:0x400C0000+0x978)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr2_Reg2,MAC_Layer3_Addr2_Reg2"
|
|
hgroup.long (d:0x400C0000+0x97C)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr3_Reg2,MAC_Layer3_Addr3_Reg2"
|
|
hgroup.long (d:0x400C0000+0x990)++0x03
|
|
hide.long 0x00 "MAC_L3_L4_Control3,MAC_L3_L4_Control3"
|
|
hgroup.long (d:0x400C0000+0x994)++0x03
|
|
hide.long 0x00 "MAC_Layer4_Address3,MAC_Layer4_Address3"
|
|
hgroup.long (d:0x400C0000+0x9A0)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr0_Reg3,MAC_Layer3_Addr0_Reg3"
|
|
hgroup.long (d:0x400C0000+0x9A4)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr1_Reg3,MAC_Layer3_Addr1_Reg3"
|
|
hgroup.long (d:0x400C0000+0x9A8)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr2_Reg3,MAC_Layer3_Addr2_Reg3"
|
|
hgroup.long (d:0x400C0000+0x9AC)++0x03
|
|
hide.long 0x00 "MAC_Layer3_Addr3_Reg3,MAC_Layer3_Addr3_Reg3"
|
|
hgroup.long (d:0x400C0000+0xB00)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Control,MAC_Timestamp_Control"
|
|
hgroup.long (d:0x400C0000+0xB04)++0x03
|
|
hide.long 0x00 "MAC_Sub_Second_Increment,MAC_Sub_Second_Increment"
|
|
hgroup.long (d:0x400C0000+0xB08)++0x03
|
|
hide.long 0x00 "MAC_System_Time_Seconds,MAC_System_Time_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB0C)++0x03
|
|
hide.long 0x00 "MAC_System_Time_Nanoseconds,MAC_System_Time_Nanoseconds"
|
|
hgroup.long (d:0x400C0000+0xB10)++0x03
|
|
hide.long 0x00 "MAC_System_Time_Seconds_Update,MAC_System_Time_Seconds_Update"
|
|
hgroup.long (d:0x400C0000+0xB14)++0x03
|
|
hide.long 0x00 "MAC_System_Time_Nanoseconds_Update,MAC_System_Time_Nanoseconds_Update"
|
|
hgroup.long (d:0x400C0000+0xB18)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Addend,MAC_Timestamp_Addend"
|
|
hgroup.long (d:0x400C0000+0xB1C)++0x03
|
|
hide.long 0x00 "MAC_System_Time_Higher_Word_Seconds,MAC_System_Time_Higher_Word_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB20)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Status,MAC_Timestamp_Status"
|
|
hgroup.long (d:0x400C0000+0xB30)++0x03
|
|
hide.long 0x00 "MAC_Tx_Timestamp_Status_Nanoseconds,MAC_Tx_Timestamp_Status_Nanoseconds"
|
|
hgroup.long (d:0x400C0000+0xB34)++0x03
|
|
hide.long 0x00 "MAC_Tx_Timestamp_Status_Seconds,MAC_Tx_Timestamp_Status_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB40)++0x03
|
|
hide.long 0x00 "MAC_Auxiliary_Control,MAC_Auxiliary_Control"
|
|
hgroup.long (d:0x400C0000+0xB48)++0x03
|
|
hide.long 0x00 "MAC_Auxiliary_Timestamp_Nanoseconds,MAC_Auxiliary_Timestamp_Nanoseconds"
|
|
hgroup.long (d:0x400C0000+0xB4C)++0x03
|
|
hide.long 0x00 "MAC_Auxiliary_Timestamp_Seconds,MAC_Auxiliary_Timestamp_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB50)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Ingress_Asym_Corr,MAC_Timestamp_Ingress_Asym_Corr"
|
|
hgroup.long (d:0x400C0000+0xB54)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Egress_Asym_Corr,MAC_Timestamp_Egress_Asym_Corr"
|
|
hgroup.long (d:0x400C0000+0xB58)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Ingress_Corr_Nanosecond,MAC_Timestamp_Ingress_Corr_Nanosecond"
|
|
hgroup.long (d:0x400C0000+0xB5C)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Egress_Corr_Nanosecond,MAC_Timestamp_Egress_Corr_Nanosecond"
|
|
hgroup.long (d:0x400C0000+0xB60)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Ingress_Corr_Subnanosec,MAC_Timestamp_Ingress_Corr_Subnanosec"
|
|
hgroup.long (d:0x400C0000+0xB64)++0x03
|
|
hide.long 0x00 "MAC_Timestamp_Egress_Corr_Subnanosec,MAC_Timestamp_Egress_Corr_Subnanosec"
|
|
hgroup.long (d:0x400C0000+0xB70)++0x03
|
|
hide.long 0x00 "MAC_PPS_Control,MAC_PPS_Control"
|
|
hgroup.long (d:0x400C0000+0xB80)++0x03
|
|
hide.long 0x00 "MAC_PPS0_Target_Time_Seconds,MAC_PPS0_Target_Time_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB84)++0x03
|
|
hide.long 0x00 "MAC_PPS0_Target_Time_Nanoseconds,MAC_PPS0_Target_Time_Nanoseconds"
|
|
hgroup.long (d:0x400C0000+0xB88)++0x03
|
|
hide.long 0x00 "MAC_PPS0_Interval,MAC_PPS0_Interval"
|
|
hgroup.long (d:0x400C0000+0xB8C)++0x03
|
|
hide.long 0x00 "MAC_PPS0_Width,MAC_PPS0_Width"
|
|
hgroup.long (d:0x400C0000+0xB90)++0x03
|
|
hide.long 0x00 "MAC_PPS1_Target_Time_Seconds,MAC_PPS1_Target_Time_Seconds"
|
|
hgroup.long (d:0x400C0000+0xB94)++0x03
|
|
hide.long 0x00 "MAC_PPS1_Target_Time_Nanoseconds,MAC_PPS1_Target_Time_Nanoseconds"
|
|
hgroup.long (d:0x400C0000+0xB98)++0x03
|
|
hide.long 0x00 "MAC_PPS1_Interval,MAC_PPS1_Interval"
|
|
hgroup.long (d:0x400C0000+0xB9C)++0x03
|
|
hide.long 0x00 "MAC_PPS1_Width,MAC_PPS1_Width"
|
|
hgroup.long (d:0x400C0000+0xBC0)++0x03
|
|
hide.long 0x00 "MAC_PTO_Control,MAC_PTO_Control"
|
|
hgroup.long (d:0x400C0000+0xBC4)++0x03
|
|
hide.long 0x00 "MAC_Source_Port_Identity0,MAC_Source_Port_Identity0"
|
|
hgroup.long (d:0x400C0000+0xBC8)++0x03
|
|
hide.long 0x00 "MAC_Source_Port_Identity1,MAC_Source_Port_Identity1"
|
|
hgroup.long (d:0x400C0000+0xBCC)++0x03
|
|
hide.long 0x00 "MAC_Source_Port_Identity2,MAC_Source_Port_Identity2"
|
|
hgroup.long (d:0x400C0000+0xBD0)++0x03
|
|
hide.long 0x00 "MAC_Log_Message_Interval,MAC_Log_Message_Interval"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ETHERNETSS"
|
|
width 26.
|
|
rgroup.long (d:0x400C2000+0x00)++0x03
|
|
line.long 0x00 "ETHERNETSS_IPREVNUM,IP Revision Number"
|
|
bitfld.long 0x00 4.--7. " IP_REV_MAJOR ,Major IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IP_REV_MINOR ,Minor IP Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400C2000+0x04)++0x03
|
|
line.long 0x00 "ETHERNETSS_CTRLSTS,Control Register"
|
|
hexmask.long 0x00 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 8.--9. " FLOW_CTRL_EN ,Back-pressure enable per receive queue." "0,1,2,3"
|
|
bitfld.long 0x00 7. " CLK_SRC_SEL ,Internal Clock Selection" "0,1"
|
|
rbitfld.long 0x00 4. " CLK_LM ,MII Loop-back mode clock select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " PHY_INTF_SEL ,PHY Type Selection" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x400C2000+0x08)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPTSTRIGSEL0,PTP Trigger-0 select"
|
|
hexmask.long 0x00 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 0.--4. " PTP_AUX_TS_TRIG_SEL0 ,Trigger select for Auxillary TS capture - 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x400C2000+0x0C)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPTSTRIGSEL1,PTP Trigger-1 select"
|
|
hexmask.long 0x00 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 0.--4. " PTP_AUX_TS_TRIG_SEL1 ,Trigger select for Auxillary TS capture - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x400C2000+0x10)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPTSSWTRIG0,PTP SW Trigger-0"
|
|
bitfld.long 0x00 0. " PTP_AUX_TS_SW_TRIG0 ,SW trigger for AUX TS capture for trigger-0" "0,1"
|
|
group.long (d:0x400C2000+0x14)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPTSSWTRIG1,PTP SW Trigger-1"
|
|
bitfld.long 0x00 0. " PTP_AUX_TS_SW_TRIG1 ,SW trigger for AUX TS capture for trigger-1" "0,1"
|
|
rgroup.long (d:0x400C2000+0x18)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPPPSR0,PTP PPS-0 Read"
|
|
bitfld.long 0x00 0. " PTP_PPS_R0 ,Registered value of Pulse Per Second-0" "0,1"
|
|
rgroup.long (d:0x400C2000+0x1C)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTPPPSR1,PTP PPS-1 Read"
|
|
bitfld.long 0x00 0. " PTP_PPS_R1 ,Registered value of Pulse Per Second-1" "0,1"
|
|
rgroup.long (d:0x400C2000+0x20)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTP_TSRL,PTP timestamp read lower 32 bits"
|
|
rgroup.long (d:0x400C2000+0x24)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTP_TSRH,PTP timestamp read upper 32 bits"
|
|
group.long (d:0x400C2000+0x28)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTP_TSWL,External Timestamp write lower 32 bits"
|
|
group.long (d:0x400C2000+0x2C)++0x03
|
|
line.long 0x00 "ETHERNETSS_PTP_TSWH,External Timestamp write upper 32 bits"
|
|
group.long (d:0x400C2000+0x30)++0x03
|
|
line.long 0x00 "ETHERNETSS_REVMII_CTRL,RevMII Phy Address controls"
|
|
hexmask.long 0x00 16.--23. 1. "WRITE_KEY,Key to enable writing lock"
|
|
bitfld.long 0x00 8.--12. " REVMII_REMOTE_PHY_ADDR ,RevMII Remote Register Space offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " REVMII_CORE_PHY_ADDR ,RevMII Core Register Space offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Flash Module"
|
|
tree "FLASHCTRL"
|
|
width 20.
|
|
group.long (d:0x400FA000+0x00)++0x03
|
|
line.long 0x00 "FRDCNTL,Flash Read Control Register"
|
|
bitfld.long 0x00 8.--11. " RWAIT ,Random Read Waitstate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400FA000+0x3C)++0x03
|
|
line.long 0x00 "FBAC,Flash Bank Access Control Register"
|
|
hexmask.long 0x00 8.--15. 1. "BAGP,Bank Active Grace Period"
|
|
group.long (d:0x400FA000+0x40)++0x03
|
|
line.long 0x00 "FBFALLBACK,Flash Bank Fallback Power Register"
|
|
bitfld.long 0x00 0.--1. " BNKPWR0 ,Bank Power Mode of BANK0" "0,1,2,3"
|
|
rgroup.long (d:0x400FA000+0x44)++0x03
|
|
line.long 0x00 "FBPRDY,Flash Bank Pump Ready Register"
|
|
bitfld.long 0x00 15. " PUMPRDY ,Flash Pump Active Power Mode" "0,1"
|
|
bitfld.long 0x00 0. " BANKRDY ,Flash Bank Active Power State" "0,1"
|
|
group.long (d:0x400FA000+0x48)++0x03
|
|
line.long 0x00 "FPAC1,Flash Pump Access Control Register 1"
|
|
hexmask.long 0x00 16.--27. 1. "PSLEEP,Pump Sleep Down Count"
|
|
bitfld.long 0x00 0. " PMPPWR ,Charge Pump Fallback Power Mode" "0,1"
|
|
rgroup.long (d:0x400FA000+0x54)++0x03
|
|
line.long 0x00 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x00 14. " ILA ,Illegal Address" "0,1"
|
|
bitfld.long 0x00 12. " PGV ,Program verify" "0,1"
|
|
bitfld.long 0x00 11. " PCV ,Precondition verify" "0,1"
|
|
bitfld.long 0x00 10. " EV ,Erase verify" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " Busy ,Busy Bit." "0,1"
|
|
bitfld.long 0x00 7. " ERS ,Erase Active." "0,1"
|
|
bitfld.long 0x00 6. " PGM ,Program Active." "0,1"
|
|
bitfld.long 0x00 5. " INVDAT ,Invalid Data." "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSTAT ,Command Status." "0,1"
|
|
bitfld.long 0x00 3. " VOLTSTAT ,Core Voltage Status." "0,1"
|
|
group.long (d:0x400FA000+0x2FC)++0x03
|
|
line.long 0x00 "FRD_INTF_CTRL_LOCK,Lock register for FLASH_CTRL_REGS (Not including FRD_INTF_CTRL_LOCK )."
|
|
group.long (d:0x400FA000+0x300)++0x03
|
|
line.long 0x00 "FRD_INTF_CTRL,Flash Read Interface Control Register"
|
|
bitfld.long 0x00 1. " DATA_CACHE_EN ,Data Cache Enable" "0,1"
|
|
bitfld.long 0x00 0. " PROG_CACHE_EN ,Program Cache Enable" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FLASHECC"
|
|
width 22.
|
|
group.long (d:0x400FA600+0x00)++0x03
|
|
line.long 0x00 "ECC_ENABLE,ECC Enable"
|
|
bitfld.long 0x00 0.--3. " ENABLE ,Enable ECC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400FA600+0x04)++0x03
|
|
line.long 0x00 "SINGLE_ERR_ADDR_LOW,Single Error Address Low"
|
|
group.long (d:0x400FA600+0x08)++0x03
|
|
line.long 0x00 "SINGLE_ERR_ADDR_HIGH,Single Error Address High"
|
|
group.long (d:0x400FA600+0x0C)++0x03
|
|
line.long 0x00 "UNC_ERR_ADDR_LOW,Uncorrectable Error Address Low"
|
|
group.long (d:0x400FA600+0x10)++0x03
|
|
line.long 0x00 "UNC_ERR_ADDR_HIGH,Uncorrectable Error Address High"
|
|
rgroup.long (d:0x400FA600+0x14)++0x03
|
|
line.long 0x00 "ERR_STATUS,Error Status"
|
|
bitfld.long 0x00 18. " UNC_ERR_H ,Upper 64 bits Uncorrectable error occurred" "0,1"
|
|
bitfld.long 0x00 17. " FAIL_1_H ,Upper 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x00 16. " FAIL_0_H ,Upper 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
bitfld.long 0x00 2. " UNC_ERR_L ,Lower 64 bits Uncorrectable error occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FAIL_1_L ,Lower 64bits Single Bit Error Corrected Value 1" "0,1"
|
|
bitfld.long 0x00 0. " FAIL_0_L ,Lower 64bits Single Bit Error Corrected Value 0" "0,1"
|
|
group.long (d:0x400FA600+0x18)++0x03
|
|
line.long 0x00 "ERR_POS,Error Position"
|
|
bitfld.long 0x00 24. " ERR_TYPE_H ,Error Type in upper 64 bits" "0,1"
|
|
bitfld.long 0x00 16.--21. " ERR_POS_H ,Bit Position of Single bit Error in upper 64 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " ERR_TYPE_L ,Error Type in lower 64 bits" "0,1"
|
|
bitfld.long 0x00 0.--5. " ERR_POS_L ,Bit Position of Single bit Error in lower 64 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x400FA600+0x1C)++0x03
|
|
line.long 0x00 "ERR_STATUS_CLR,Error Status Clear"
|
|
bitfld.long 0x00 18. " UNC_ERR_H_CLR ,Upper 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
bitfld.long 0x00 17. " FAIL_1_H_CLR ,Upper 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x00 16. " FAIL_0_H_CLR ,Upper 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
bitfld.long 0x00 2. " UNC_ERR_L_CLR ,Lower 64 bits Uncorrectable error occurred Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FAIL_1_L_CLR ,Lower 64bits Single Bit Error Corrected Value 1 Clear" "0,1"
|
|
bitfld.long 0x00 0. " FAIL_0_L_CLR ,Lower 64bits Single Bit Error Corrected Value 0 Clear" "0,1"
|
|
group.long (d:0x400FA600+0x20)++0x03
|
|
line.long 0x00 "ERR_CNT,Error Control"
|
|
hexmask.long 0x00 0.--15. 1. "ERR_CNT,Error counter"
|
|
group.long (d:0x400FA600+0x24)++0x03
|
|
line.long 0x00 "ERR_THRESHOLD,Error Threshold"
|
|
hexmask.long 0x00 0.--15. 1. "ERR_THRESHOLD,Error Threshold"
|
|
rgroup.long (d:0x400FA600+0x28)++0x03
|
|
line.long 0x00 "ERR_INTFLG,Error Interrupt Flag"
|
|
bitfld.long 0x00 1. " UNC_ERR_INTFLG ,Uncorrectable Interrupt Flag" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR_INTFLG ,Single Error Interrupt Flag" "0,1"
|
|
group.long (d:0x400FA600+0x2C)++0x03
|
|
line.long 0x00 "ERR_INTCLR,Error Interrupt Flag Clear"
|
|
bitfld.long 0x00 1. " UNC_ERR_INTCLR ,Uncorrectable Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR_INTCLR ,Single Error Interrupt Flag Clear" "0,1"
|
|
group.long (d:0x400FA600+0x30)++0x03
|
|
line.long 0x00 "FDATAH_TEST,Data High Test"
|
|
group.long (d:0x400FA600+0x34)++0x03
|
|
line.long 0x00 "FDATAL_TEST,Data Low Test"
|
|
group.long (d:0x400FA600+0x38)++0x03
|
|
line.long 0x00 "FADDR_TEST,ECC Test Address"
|
|
bitfld.long 0x00 16.--21. " ADDRH ,ECC Address High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 3.--15. 1. "ADDRL,ECC Address Low"
|
|
group.long (d:0x400FA600+0x3C)++0x03
|
|
line.long 0x00 "FECC_TEST,ECC Test Address"
|
|
hexmask.long 0x00 0.--7. 1. "ECC,ECC Control Bits"
|
|
group.long (d:0x400FA600+0x40)++0x03
|
|
line.long 0x00 "FECC_CTRL,ECC Control"
|
|
bitfld.long 0x00 2. " DO_ECC_CALC ,Enable ECC Calculation" "0,1"
|
|
bitfld.long 0x00 1. " ECC_SELECT ,ECC Bit Select" "0,1"
|
|
bitfld.long 0x00 0. " ECC_TEST_EN ,Enable ECC Test Logic" "0,1"
|
|
rgroup.long (d:0x400FA600+0x44)++0x03
|
|
line.long 0x00 "FOUTH_TEST,Test Data Out High"
|
|
rgroup.long (d:0x400FA600+0x48)++0x03
|
|
line.long 0x00 "FOUTL_TEST,Test Data Out Low"
|
|
rgroup.long (d:0x400FA600+0x4C)++0x03
|
|
line.long 0x00 "FECC_STATUS,ECC Status"
|
|
bitfld.long 0x00 8. " ERR_TYPE ,Holds Bit Position of 8 Check Bits of Error" "0,1"
|
|
bitfld.long 0x00 2.--7. " DATA_ERR_POS ,Holds Bit Position of Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. " UNC_ERR ,Test Result is Uncorrectable Error" "0,1"
|
|
bitfld.long 0x00 0. " SINGLE_ERR ,Test Result is Single Bit Error" "0,1"
|
|
group.long (d:0x400FA600+0x7C)++0x03
|
|
line.long 0x00 "FLASH_ECC_REGS_LOCK,Lock register for FLASH_ECC_REGS (Not including FLASH_ECC_REGS_LOCK )."
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Generic Cyclic Redundancy Check (GCRC)"
|
|
width 14.
|
|
group.long (d:0x40040000+0x00)++0x03
|
|
line.long 0x00 "CRCCTRL,CRC Control Register"
|
|
bitfld.long 0x00 8.--9. " DATATYPE ,Defines the DATATYPE of the element of the data array." "0,1,2,3"
|
|
bitfld.long 0x00 7. " BITREVERSE ,Enables the DATAIN bus to the CRC engine to be bit reversed." "0,1"
|
|
bitfld.long 0x00 6. " ENDIANNESS ,Defines the endianness of the data stream." "0,1"
|
|
bitfld.long 0x00 0.--5. " POLYSIZE ,CRC polynomial order" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x40040000+0x04)++0x03
|
|
line.long 0x00 "CRCPOLY,CRC Polynomial Register"
|
|
group.long (d:0x40040000+0x08)++0x03
|
|
line.long 0x00 "CRCDATAMASK,CRC Data Mask Register"
|
|
bitfld.long 0x00 0.--4. " DATAMASK ,Number of bits to be masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (d:0x40040000+0x0C)++0x03
|
|
line.long 0x00 "CRCDATAIN,CRC Data Input Register"
|
|
group.long (d:0x40040000+0x10)++0x03
|
|
line.long 0x00 "CRCDATAOUT,CRC Data Output Register"
|
|
rgroup.long (d:0x40040000+0x14)++0x03
|
|
line.long 0x00 "CRCDATATRANS,CRC Transformed Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "General-Purpose Input/Output (GPIO)"
|
|
tree "GPIODATA"
|
|
width 11.
|
|
group.long (d:0x40083000+0x00)++0x03
|
|
line.long 0x00 "GPADAT,GPIO A Data Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x04)++0x03
|
|
line.long 0x00 "GPASET,GPIO A Data Set Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x08)++0x03
|
|
line.long 0x00 "GPACLEAR,GPIO A Data Clear Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x0C)++0x03
|
|
line.long 0x00 "GPATOGGLE,GPIO A Data Toggle Register (GPIO0 to 31)"
|
|
bitfld.long 0x00 31. " GPIO31 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO30 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO29 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO28 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO27 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO26 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO25 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO24 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO23 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO22 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO21 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO20 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO19 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO18 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO17 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO16 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO15 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO14 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO13 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO12 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO11 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO10 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO9 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO8 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO7 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO6 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO5 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO4 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO3 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO2 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO1 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO0 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x10)++0x03
|
|
line.long 0x00 "GPBDAT,GPIO B Data Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x14)++0x03
|
|
line.long 0x00 "GPBSET,GPIO B Data Set Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x18)++0x03
|
|
line.long 0x00 "GPBCLEAR,GPIO B Data Clear Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x1C)++0x03
|
|
line.long 0x00 "GPBTOGGLE,GPIO B Data Toggle Register (GPIO32 to 63)"
|
|
bitfld.long 0x00 31. " GPIO63 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO62 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO61 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO60 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO59 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO58 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO57 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO56 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO55 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO54 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO53 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO52 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO51 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO50 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO49 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO48 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO47 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO46 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO45 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO44 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO43 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO42 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO41 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO40 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO39 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO38 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO37 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO36 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO35 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO34 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO33 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO32 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x20)++0x03
|
|
line.long 0x00 "GPCDAT,GPIO C Data Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x24)++0x03
|
|
line.long 0x00 "GPCSET,GPIO C Data Set Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x28)++0x03
|
|
line.long 0x00 "GPCCLEAR,GPIO C Data Clear Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x2C)++0x03
|
|
line.long 0x00 "GPCTOGGLE,GPIO C Data Toggle Register (GPIO64 to 95)"
|
|
bitfld.long 0x00 31. " GPIO95 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO94 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO93 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO92 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO91 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO90 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO89 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO88 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO87 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO86 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO85 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO84 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO83 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO82 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO81 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO80 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO79 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO78 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO77 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO76 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO75 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO74 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO73 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO72 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO71 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO70 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO69 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO68 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO67 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO66 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO65 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO64 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x30)++0x03
|
|
line.long 0x00 "GPDDAT,GPIO D Data Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x34)++0x03
|
|
line.long 0x00 "GPDSET,GPIO D Data Set Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x38)++0x03
|
|
line.long 0x00 "GPDCLEAR,GPIO D Data Clear Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x3C)++0x03
|
|
line.long 0x00 "GPDTOGGLE,GPIO D Data Toggle Register (GPIO96 to 127)"
|
|
bitfld.long 0x00 31. " GPIO127 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO126 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO125 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO124 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO123 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO122 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO121 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO120 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO119 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO118 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO117 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO116 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO115 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO114 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO113 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO112 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO111 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO110 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO109 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO108 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO107 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO106 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO105 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO104 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO103 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO102 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO101 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO100 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO99 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO98 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO97 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO96 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x40)++0x03
|
|
line.long 0x00 "GPEDAT,GPIO E Data Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x44)++0x03
|
|
line.long 0x00 "GPESET,GPIO E Data Set Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x48)++0x03
|
|
line.long 0x00 "GPECLEAR,GPIO E Data Clear Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x4C)++0x03
|
|
line.long 0x00 "GPETOGGLE,GPIO E Data Toggle Register (GPIO128 to 159)"
|
|
bitfld.long 0x00 31. " GPIO159 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 30. " GPIO158 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 29. " GPIO157 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 28. " GPIO156 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " GPIO155 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 26. " GPIO154 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 25. " GPIO153 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 24. " GPIO152 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " GPIO151 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 22. " GPIO150 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 21. " GPIO149 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 20. " GPIO148 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " GPIO147 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 18. " GPIO146 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 17. " GPIO145 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 16. " GPIO144 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " GPIO143 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 14. " GPIO142 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 13. " GPIO141 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 12. " GPIO140 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " GPIO139 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 10. " GPIO138 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 9. " GPIO137 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 8. " GPIO136 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " GPIO135 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO134 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO133 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 4. " GPIO132 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " GPIO131 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO130 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO129 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 0. " GPIO128 ,Output Toggle bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x50)++0x03
|
|
line.long 0x00 "GPFDAT,GPIO F Data Register (GPIO160 to 191)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Data Register for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Data Register for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Data Register for this pin" "0,1"
|
|
group.long (d:0x40083000+0x54)++0x03
|
|
line.long 0x00 "GPFSET,GPIO F Data Set Register (GPIO160 to 191)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Set bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Set bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Set bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x58)++0x03
|
|
line.long 0x00 "GPFCLEAR,GPIO F Data Clear Register (GPIO160 to 191)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Clear bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Clear bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Clear bit for this pin" "0,1"
|
|
group.long (d:0x40083000+0x5C)++0x03
|
|
line.long 0x00 "GPFTOGGLE,GPIO F Data Toggle Register (GPIO160 to 191)"
|
|
bitfld.long 0x00 8. " GPIO168 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 7. " GPIO167 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 6. " GPIO166 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 5. " GPIO165 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " GPIO164 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 3. " GPIO163 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 2. " GPIO162 ,Output Toggle bit for this pin" "0,1"
|
|
bitfld.long 0x00 1. " GPIO161 ,Output Toggle bit for this pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIO160 ,Output Toggle bit for this pin" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIODATAREAD"
|
|
width 10.
|
|
rgroup.long (d:0x40083100+0x00)++0x03
|
|
line.long 0x00 "GPADAT_R,GPIO A Data Read Register"
|
|
rgroup.long (d:0x40083100+0x04)++0x03
|
|
line.long 0x00 "GPBDAT_R,GPIO B Data Read Register"
|
|
rgroup.long (d:0x40083100+0x08)++0x03
|
|
line.long 0x00 "GPCDAT_R,GPIO C Data Read Register"
|
|
rgroup.long (d:0x40083100+0x0C)++0x03
|
|
line.long 0x00 "GPDDAT_R,GPIO D Data Read Register"
|
|
rgroup.long (d:0x40083100+0x10)++0x03
|
|
line.long 0x00 "GPEDAT_R,GPIO E Data Read Register"
|
|
rgroup.long (d:0x40083100+0x14)++0x03
|
|
line.long 0x00 "GPFDAT_R,GPIO F Data Read Register"
|
|
rgroup.long (d:0x40083100+0x18)++0x03
|
|
line.long 0x00 "GPGDAT_R,GPIO G Data Read Register"
|
|
rgroup.long (d:0x40083100+0x1C)++0x03
|
|
line.long 0x00 "GPHDAT_R,GPIO H Data Read Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Inter-Integrated Circuit Module (I2C)"
|
|
width 15.
|
|
group.long (d:0x40020000+0x00)++0x03
|
|
line.long 0x00 "I2CMSA,I2C Master Slave Address"
|
|
bitfld.long 0x00 1.--7. " SA ,I2C Slave Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0. " RS ,Receive/Send" "0,1"
|
|
rgroup.long (d:0x40020000+0x04)++0x03
|
|
line.long 0x00 "I2CMCS,I2C Master Control/Status"
|
|
bitfld.long 0x00 31. " ACTDMARX ,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x00 30. " ACTDMATX ,DMA TX Active Status" "0,1"
|
|
bitfld.long 0x00 7. " CLKTO ,Clock Timeout Error" "0,1"
|
|
bitfld.long 0x00 6. " BUSBSY ,Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " IDLE ,I2C Idle" "0,1"
|
|
bitfld.long 0x00 4. " ARBLST ,Arbitration Lost" "0,1"
|
|
bitfld.long 0x00 3. " DATACK ,Acknowledge Data" "0,1"
|
|
bitfld.long 0x00 2. " ADRACK ,Acknowledge Address" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " ERROR ,Error" "0,1"
|
|
bitfld.long 0x00 0. " BUSY ,I2C Busy" "0,1"
|
|
group.long (d:0x40020000+0x08)++0x03
|
|
line.long 0x00 "I2CMDR,I2C Master Data"
|
|
hexmask.long 0x00 0.--7. 1. "DATA,Data transmitted/received"
|
|
group.long (d:0x40020000+0x0C)++0x03
|
|
line.long 0x00 "I2CMTPR,I2C Master Timer Period"
|
|
bitfld.long 0x00 16.--18. " PULSEL ,Glitch Suppression Pulse Width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " HS ,High-Speed Enable" "0,1"
|
|
bitfld.long 0x00 0.--6. " TPR ,Timer Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x40020000+0x10)++0x03
|
|
line.long 0x00 "I2CMIMR,I2C Master Interrupt Mask"
|
|
bitfld.long 0x00 11. " RXFFIM ,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 10. " TXFEIM ,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 9. " RXIM ,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 8. " TXIM ,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ARBLOSTIM ,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " STOPIM ,STOP Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " STARTIM ,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 4. " NACKIM ,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMATXIM ,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 2. " DMARXIM ,Receive DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 1. " CLKIM ,Clock Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 0. " IM ,Master Interrupt Mask" "0,1"
|
|
rgroup.long (d:0x40020000+0x14)++0x03
|
|
line.long 0x00 "I2CMRIS,I2C Master Raw Interrupt Status"
|
|
bitfld.long 0x00 11. " RXFFRIS ,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 10. " TXFERIS ,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 9. " RXRIS ,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 8. " TXRIS ,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ARBLOSTRIS ,Arbitration Lost Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 6. " STOPRIS ,STOP Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 5. " STARTRIS ,START Detection Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 4. " NACKRIS ,Address/Data NACK Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMATXRIS ,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 2. " DMARXRIS ,Receive DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " CLKRIS ,Clock Timeout Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 0. " RIS ,Master Raw Interrupt Status" "0,1"
|
|
rgroup.long (d:0x40020000+0x18)++0x03
|
|
line.long 0x00 "I2CMMIS,I2C Master Masked Interrupt Status"
|
|
bitfld.long 0x00 11. " RXFFMIS ,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 10. " TXFEMIS ,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 9. " RXMIS ,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 8. " TXMIS ,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ARBLOSTMIS ,Arbitration Lost Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " STOPMIS ,STOP Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " STARTMIS ,START Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 4. " NACKMIS ,Address/Data NACK Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMATXMIS ,Transmit DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x00 2. " DMARXMIS ,Receive DMA Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " CLKMIS ,Clock Timeout Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 0. " MIS ,Masked Interrupt Status" "0,1"
|
|
group.long (d:0x40020000+0x1C)++0x03
|
|
line.long 0x00 "I2CMICR,I2C Master Interrupt Clear"
|
|
bitfld.long 0x00 11. " RXFFIC ,Receive FIFO Full Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 10. " TXFEIC ,Transmit FIFO Empty Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 9. " RXIC ,Receive FIFO Request Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 8. " TXIC ,Transmit FIFO Request Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ARBLOSTIC ,Arbitration Lost Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 6. " STOPIC ,STOP Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 5. " STARTIC ,START Detection Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 4. " NACKIC ,Address/Data NACK Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " DMATXIC ,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 2. " DMARXIC ,Receive DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 1. " CLKIC ,Clock Timeout Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 0. " IC ,Master Interrupt Clear" "0,1"
|
|
group.long (d:0x40020000+0x20)++0x03
|
|
line.long 0x00 "I2CMCR,I2C Master Configuration"
|
|
bitfld.long 0x00 5. " SFE ,I2C Slave Function Enable" "0,1"
|
|
bitfld.long 0x00 4. " MFE ,I2C Master Function Enable" "0,1"
|
|
bitfld.long 0x00 0. " LPBK ,I2C Loopback" "0,1"
|
|
group.long (d:0x40020000+0x24)++0x03
|
|
line.long 0x00 "I2CMCLKOCNT,I2C Master Clock Low Timeout Count"
|
|
hexmask.long 0x00 0.--7. 1. "CNTL,I2C Master Count"
|
|
rgroup.long (d:0x40020000+0x2C)++0x03
|
|
line.long 0x00 "I2CMBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x00 1. " SDA ,I2C SDA Status" "0,1"
|
|
bitfld.long 0x00 0. " SCL ,I2C SCL Status" "0,1"
|
|
group.long (d:0x40020000+0x30)++0x03
|
|
line.long 0x00 "I2CMBLEN,I2C Master Burst Length"
|
|
hexmask.long 0x00 0.--7. 1. "CNTL,I2C Burst Length"
|
|
rgroup.long (d:0x40020000+0x34)++0x03
|
|
line.long 0x00 "I2CMBCNT,I2C Master Burst Count"
|
|
hexmask.long 0x00 0.--7. 1. "CNTL,I2C Master Burst Count"
|
|
group.long (d:0x40020000+0x800)++0x03
|
|
line.long 0x00 "I2CSOAR,I2C Slave Own Address"
|
|
bitfld.long 0x00 0.--6. " OAR ,I2C Slave Own Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rgroup.long (d:0x40020000+0x804)++0x03
|
|
line.long 0x00 "I2CSCSR,I2C Slave Control/Status"
|
|
bitfld.long 0x00 31. " ACTDMARX ,DMA RX Active Status" "0,1"
|
|
bitfld.long 0x00 30. " ACTDMATX ,DMA TX Active Status" "0,1"
|
|
bitfld.long 0x00 5. " QCMDRW ,Quick Command Read / Write" "0,1"
|
|
bitfld.long 0x00 4. " QCMDST ,Quick Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " OAR2SEL ,OAR2 Address Matched" "0,1"
|
|
bitfld.long 0x00 2. " FBR ,First Byte Received" "0,1"
|
|
bitfld.long 0x00 1. " TREQ ,Transmit Request" "0,1"
|
|
bitfld.long 0x00 0. " RREQ ,Receive Request" "0,1"
|
|
group.long (d:0x40020000+0x808)++0x03
|
|
line.long 0x00 "I2CSDR,I2C Slave Data"
|
|
hexmask.long 0x00 0.--7. 1. "DATA,Data for Transfer"
|
|
group.long (d:0x40020000+0x80C)++0x03
|
|
line.long 0x00 "I2CSIMR,I2C Slave Interrupt Mask"
|
|
bitfld.long 0x00 8. " RXFFIM ,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 7. " TXFEIM ,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " RXIM ,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " TXIM ,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " DMATXIM ,Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 3. " DMARXIM ,Receive DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 2. " STOPIM ,Stop Condition Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 1. " STARTIM ,Start Condition Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " DATAIM ,Data Interrupt Mask" "0,1"
|
|
rgroup.long (d:0x40020000+0x810)++0x03
|
|
line.long 0x00 "I2CSRIS,I2C Slave Raw Interrupt Status"
|
|
bitfld.long 0x00 8. " RXFFRIS ,Receive FIFO Full Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 7. " TXFERIS ,Transmit FIFO Empty Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 6. " RXRIS ,Receive FIFO Request Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit Request Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " DMATXRIS ,Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 3. " DMARXRIS ,Receive DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 2. " STOPRIS ,Stop Condition Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " STARTRIS ,Start Condition Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " DATARIS ,Data Raw Interrupt Status" "0,1"
|
|
rgroup.long (d:0x40020000+0x814)++0x03
|
|
line.long 0x00 "I2CSMIS,I2C Slave Masked Interrupt Status"
|
|
bitfld.long 0x00 8. " RXFFMIS ,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 7. " TXFEMIS ,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " RXMIS ,Receive FIFO Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " TXMIS ,Transmit FIFO Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " DMATXMIS ,Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 3. " DMARXMIS ,Receive DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 2. " STOPMIS ,Stop Condition Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " STARTMIS ,Start Condition Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " DATAMIS ,Data Masked Interrupt Status" "0,1"
|
|
group.long (d:0x40020000+0x818)++0x03
|
|
line.long 0x00 "I2CSICR,I2C Slave Interrupt Clear"
|
|
bitfld.long 0x00 8. " RXFFIC ,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 7. " TXFEIC ,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 6. " RXIC ,Receive Request Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " TXIC ,Transmit Request Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " DMATXIC ,Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 3. " DMARXIC ,Receive DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 2. " STOPIC ,Stop Condition Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 1. " STARTIC ,Start Condition Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " DATAIC ,Data Interrupt Clear" "0,1"
|
|
group.long (d:0x40020000+0x81C)++0x03
|
|
line.long 0x00 "I2CSOAR2,I2C Slave Own Address 2"
|
|
bitfld.long 0x00 7. " OAR2EN ,I2C Slave Own Address 2 Enable" "0,1"
|
|
bitfld.long 0x00 0.--6. " OAR2 ,I2C Slave Own Address 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x40020000+0x820)++0x03
|
|
line.long 0x00 "I2CSACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x00 1. " ACKOVAL ,I2C Slave ACK Override Value" "0,1"
|
|
bitfld.long 0x00 0. " ACKOEN ,I2C Slave ACK Override Enable" "0,1"
|
|
rgroup.long (d:0x40020000+0xF00)++0x03
|
|
line.long 0x00 "I2CFIFODATARX,I2C FIFO Data RX"
|
|
hexmask.long 0x00 0.--7. 1. "DATA,I2C RX FIFO Read Data Byte"
|
|
group.long (d:0x40020000+0xF04)++0x03
|
|
line.long 0x00 "I2CFIFOCTL,I2C FIFO Control"
|
|
bitfld.long 0x00 31. " RXASGNMT ,RX Control Assignment" "0,1"
|
|
bitfld.long 0x00 30. " RXFLUSH ,RX FIFO Flush" "0,1"
|
|
bitfld.long 0x00 29. " DMARXENA ,DMA RX Channel Enable" "0,1"
|
|
bitfld.long 0x00 16.--18. " RXTRIG ,RX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " TXASGNMT ,TX Control Assignment" "0,1"
|
|
bitfld.long 0x00 14. " TXFLUSH ,TX FIFO Flush" "0,1"
|
|
bitfld.long 0x00 13. " DMATXENA ,DMA TX Channel Enable" "0,1"
|
|
bitfld.long 0x00 0.--2. " TXTRIG ,TX FIFO Trigger" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x40020000+0xF08)++0x03
|
|
line.long 0x00 "I2CFIFOSTATUS,I2C FIFO Status"
|
|
bitfld.long 0x00 18. " RXABVTRIG ,RX FIFO Above Trigger Level" "0,1"
|
|
bitfld.long 0x00 17. " RXFF ,RX FIFO Full" "0,1"
|
|
bitfld.long 0x00 16. " RXFE ,RX FIFO Empty" "0,1"
|
|
bitfld.long 0x00 2. " TXBLWTRIG ,TX FIFO Below Trigger Level" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " TXFF ,TX FIFO Full" "0,1"
|
|
bitfld.long 0x00 0. " TXFE ,TX FIFO Empty" "0,1"
|
|
rgroup.long (d:0x40020000+0xFC0)++0x03
|
|
line.long 0x00 "I2CPP,I2C Peripheral Properties"
|
|
bitfld.long 0x00 0. " HS ,High-Speed Capable" "0,1"
|
|
group.long (d:0x40020000+0xFC4)++0x03
|
|
line.long 0x00 "I2CPC,I2C Peripheral Configuration"
|
|
bitfld.long 0x00 0. " HS ,High-Speed Capable" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Interprocessor Communication (IPC)"
|
|
tree "IPCCMTOCPU1"
|
|
width 21.
|
|
group.long (d:0x400FD000+0x00)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCACK,CMTOCPU1IPCACK Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC28 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC24 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC20 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC16 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC8 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC4 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Acknowledgement from CM to CPU1TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long (d:0x400FD000+0x04)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCSTS,CPU1TOCMIPCSTS Register"
|
|
bitfld.long 0x00 31. " IPC31 ,IPC31 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,IPC30 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,IPC29 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,IPC28 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,IPC27 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,IPC26 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,IPC25 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,IPC24 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,IPC23 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,IPC22 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,IPC21 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,IPC20 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,IPC19 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,IPC18 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,IPC17 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,IPC16 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,IPC15 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,IPC14 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,IPC13 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,IPC12 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,IPC11 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,IPC10 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,IPC9 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,IPC8 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,IPC7 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,IPC6 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,IPC5 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,IPC4 Request from CPU1 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,IPC3 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,IPC2 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,IPC1 Request from CPU1 to CM" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,IPC0 Request from CPU1 to CM" "0,1"
|
|
group.long (d:0x400FD000+0x08)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSET,CMTOCPU1IPCSET Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Set CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Set CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Set CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Set CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Set CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Set CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Set CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Set CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Set CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Set CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Set CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Set CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Set CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Set CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Set CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Set CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Set CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Set CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Set CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Set CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Set CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Set CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Set CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Set CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Set CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Set CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Set CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Set CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Set CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Set CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Set CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Set CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
group.long (d:0x400FD000+0x0C)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCCLR,CMTOCPU1IPCCLR Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Clear CMTOCPU1IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Clear CMTOCPU1IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Clear CMTOCPU1IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Clear CMTOCPU1IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Clear CMTOCPU1IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Clear CMTOCPU1IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Clear CMTOCPU1IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Clear CMTOCPU1IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Clear CMTOCPU1IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Clear CMTOCPU1IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Clear CMTOCPU1IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Clear CMTOCPU1IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Clear CMTOCPU1IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Clear CMTOCPU1IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Clear CMTOCPU1IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Clear CMTOCPU1IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Clear CMTOCPU1IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Clear CMTOCPU1IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Clear CMTOCPU1IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Clear CMTOCPU1IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Clear CMTOCPU1IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Clear CMTOCPU1IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Clear CMTOCPU1IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Clear CMTOCPU1IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Clear CMTOCPU1IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Clear CMTOCPU1IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Clear CMTOCPU1IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Clear CMTOCPU1IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Clear CMTOCPU1IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Clear CMTOCPU1IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Clear CMTOCPU1IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Clear CMTOCPU1IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long (d:0x400FD000+0x10)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCFLG,CMTOCPU1IPCFLG Register"
|
|
bitfld.long 0x00 31. " IPC31 ,CM to CPU1 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,CM to CPU1 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,CM to CPU1 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,CM to CPU1 IPC28 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,CM to CPU1 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,CM to CPU1 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,CM to CPU1 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,CM to CPU1 IPC24 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,CM to CPU1 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,CM to CPU1 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,CM to CPU1 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,CM to CPU1 IPC20 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,CM to CPU1 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,CM to CPU1 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,CM to CPU1 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,CM to CPU1 IPC16 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,CM to CPU1 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,CM to CPU1 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,CM to CPU1 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,CM to CPU1 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,CM to CPU1 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,CM to CPU1 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,CM to CPU1 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,CM to CPU1 IPC8 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,CM to CPU1 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,CM to CPU1 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,CM to CPU1 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,CM to CPU1 IPC4 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,CM to CPU1 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,CM to CPU1 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,CM to CPU1 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,CM to CPU1 IPC0 Flag Status" "0,1"
|
|
rgroup.long (d:0x400FD000+0x18)++0x03
|
|
line.long 0x00 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
rgroup.long (d:0x400FD000+0x1C)++0x03
|
|
line.long 0x00 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
rgroup.long (d:0x400FD000+0x20)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVCOM,CPU1TOCMIPCRECVCOM Register"
|
|
rgroup.long (d:0x400FD000+0x24)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVADDR,CPU1TOCMIPCRECVADDR Register"
|
|
rgroup.long (d:0x400FD000+0x28)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCRECVDATA,CPU1TOCMIPCRECVDATA Register"
|
|
group.long (d:0x400FD000+0x2C)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCREPLY,CMTOCPU1IPCREPLY Register"
|
|
group.long (d:0x400FD000+0x30)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDCOM,CMTOCPU1IPCSENDCOM Register"
|
|
group.long (d:0x400FD000+0x34)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDADDR,CMTOCPU1IPCSENDADDR Register"
|
|
group.long (d:0x400FD000+0x38)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCSENDDATA,CMTOCPU1IPCSENDDATA Register"
|
|
group.long (d:0x400FD000+0x3C)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCREPLY,CPU1TOCMIPCREPLY Register"
|
|
group.long (d:0x400FD000+0x40)++0x03
|
|
line.long 0x00 "CMTOCPU1IPCBOOTSTS,CMTOCPU1IPCBOOTSTS Register"
|
|
group.long (d:0x400FD000+0x44)++0x03
|
|
line.long 0x00 "CPU1TOCMIPCBOOTMODE,CPU1TOCMIPCBOOTMODE Register"
|
|
group.long (d:0x400FD000+0x48)++0x03
|
|
line.long 0x00 "PUMPREQUEST,PUMPREQUEST Register"
|
|
hexmask.long 0x00 16.--31. 1. "KEY,Key Qualifier for writes to this register"
|
|
bitfld.long 0x00 0.--1. " SEM ,Flash Pump Request Semaphore between CPU1, CPU2 and CM" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("F28388S*")&&!cpuis("F28386S*")&&!cpuis("F28384S*")
|
|
tree "IPCCMTOCPU2"
|
|
width 21.
|
|
group.long (d:0x400FD080+0x00)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCACK,CMTOCPU2IPCACK Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC31 bit" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC30 bit" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC29 bit" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC28 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC27 bit" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC26 bit" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC25 bit" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC24 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC23 bit" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC22 bit" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC21 bit" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC20 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC19 bit" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC18 bit" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC17 bit" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC16 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC15 bit" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC14 bit" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC13 bit" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC12 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC11 bit" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC10 bit" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC9 bit" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC8 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC7 bit" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC6 bit" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC5 bit" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC4 bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC3 bit" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC2 bit" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC1 bit" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Acknowledgement from CM to CPU2TOCMIPCFLG.IPC0 bit" "0,1"
|
|
rgroup.long (d:0x400FD080+0x04)++0x03
|
|
line.long 0x00 "CPU2TOCMIPCSTS,CPU2TOCMIPCSTS Register"
|
|
bitfld.long 0x00 31. " IPC31 ,IPC31 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,IPC30 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,IPC29 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,IPC28 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,IPC27 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,IPC26 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,IPC25 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,IPC24 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,IPC23 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,IPC22 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,IPC21 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,IPC20 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,IPC19 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,IPC18 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,IPC17 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,IPC16 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,IPC15 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,IPC14 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,IPC13 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,IPC12 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,IPC11 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,IPC10 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,IPC9 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,IPC8 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,IPC7 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,IPC6 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,IPC5 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,IPC4 Request from CPU2 to CM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,IPC3 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,IPC2 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,IPC1 Request from CPU2 to CM" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,IPC0 Request from CPU2 to CM" "0,1"
|
|
group.long (d:0x400FD080+0x08)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCSET,CMTOCPU2IPCSET Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Set CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Set CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Set CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Set CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Set CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Set CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Set CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Set CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Set CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Set CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Set CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Set CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Set CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Set CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Set CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Set CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Set CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Set CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Set CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Set CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Set CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Set CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Set CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Set CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Set CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Set CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Set CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Set CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Set CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Set CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Set CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Set CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
group.long (d:0x400FD080+0x0C)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCCLR,CMTOCPU2IPCCLR Register"
|
|
bitfld.long 0x00 31. " IPC31 ,Clear CMTOCPU2IPCFLG.IPC31 Flag" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,Clear CMTOCPU2IPCFLG.IPC30 Flag" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,Clear CMTOCPU2IPCFLG.IPC29 Flag" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,Clear CMTOCPU2IPCFLG.IPC28 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,Clear CMTOCPU2IPCFLG.IPC27 Flag" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,Clear CMTOCPU2IPCFLG.IPC26 Flag" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,Clear CMTOCPU2IPCFLG.IPC25 Flag" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,Clear CMTOCPU2IPCFLG.IPC24 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,Clear CMTOCPU2IPCFLG.IPC23 Flag" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,Clear CMTOCPU2IPCFLG.IPC22 Flag" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,Clear CMTOCPU2IPCFLG.IPC21 Flag" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,Clear CMTOCPU2IPCFLG.IPC20 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,Clear CMTOCPU2IPCFLG.IPC19 Flag" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,Clear CMTOCPU2IPCFLG.IPC18 Flag" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,Clear CMTOCPU2IPCFLG.IPC17 Flag" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,Clear CMTOCPU2IPCFLG.IPC16 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,Clear CMTOCPU2IPCFLG.IPC15 Flag" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,Clear CMTOCPU2IPCFLG.IPC14 Flag" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,Clear CMTOCPU2IPCFLG.IPC13 Flag" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,Clear CMTOCPU2IPCFLG.IPC12 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,Clear CMTOCPU2IPCFLG.IPC11 Flag" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,Clear CMTOCPU2IPCFLG.IPC10 Flag" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,Clear CMTOCPU2IPCFLG.IPC9 Flag" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,Clear CMTOCPU2IPCFLG.IPC8 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,Clear CMTOCPU2IPCFLG.IPC7 Flag" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,Clear CMTOCPU2IPCFLG.IPC6 Flag" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,Clear CMTOCPU2IPCFLG.IPC5 Flag" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,Clear CMTOCPU2IPCFLG.IPC4 Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,Clear CMTOCPU2IPCFLG.IPC3 Flag" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,Clear CMTOCPU2IPCFLG.IPC2 Flag" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,Clear CMTOCPU2IPCFLG.IPC1 Flag" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,Clear CMTOCPU2IPCFLG.IPC0 Flag" "0,1"
|
|
rgroup.long (d:0x400FD080+0x10)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCFLG,CMTOCPU2IPCFLG Register"
|
|
bitfld.long 0x00 31. " IPC31 ,CM to CPU2 IPC31 Flag Status" "0,1"
|
|
bitfld.long 0x00 30. " IPC30 ,CM to CPU2 IPC30 Flag Status" "0,1"
|
|
bitfld.long 0x00 29. " IPC29 ,CM to CPU2 IPC29 Flag Status" "0,1"
|
|
bitfld.long 0x00 28. " IPC28 ,CM to CPU2 IPC28 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " IPC27 ,CM to CPU2 IPC27 Flag Status" "0,1"
|
|
bitfld.long 0x00 26. " IPC26 ,CM to CPU2 IPC26 Flag Status" "0,1"
|
|
bitfld.long 0x00 25. " IPC25 ,CM to CPU2 IPC25 Flag Status" "0,1"
|
|
bitfld.long 0x00 24. " IPC24 ,CM to CPU2 IPC24 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " IPC23 ,CM to CPU2 IPC23 Flag Status" "0,1"
|
|
bitfld.long 0x00 22. " IPC22 ,CM to CPU2 IPC22 Flag Status" "0,1"
|
|
bitfld.long 0x00 21. " IPC21 ,CM to CPU2 IPC21 Flag Status" "0,1"
|
|
bitfld.long 0x00 20. " IPC20 ,CM to CPU2 IPC20 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " IPC19 ,CM to CPU2 IPC19 Flag Status" "0,1"
|
|
bitfld.long 0x00 18. " IPC18 ,CM to CPU2 IPC18 Flag Status" "0,1"
|
|
bitfld.long 0x00 17. " IPC17 ,CM to CPU2 IPC17 Flag Status" "0,1"
|
|
bitfld.long 0x00 16. " IPC16 ,CM to CPU2 IPC16 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " IPC15 ,CM to CPU2 IPC15 Flag Status" "0,1"
|
|
bitfld.long 0x00 14. " IPC14 ,CM to CPU2 IPC14 Flag Status" "0,1"
|
|
bitfld.long 0x00 13. " IPC13 ,CM to CPU2 IPC13 Flag Status" "0,1"
|
|
bitfld.long 0x00 12. " IPC12 ,CM to CPU2 IPC12 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " IPC11 ,CM to CPU2 IPC11 Flag Status" "0,1"
|
|
bitfld.long 0x00 10. " IPC10 ,CM to CPU2 IPC10 Flag Status" "0,1"
|
|
bitfld.long 0x00 9. " IPC9 ,CM to CPU2 IPC9 Flag Status" "0,1"
|
|
bitfld.long 0x00 8. " IPC8 ,CM to CPU2 IPC8 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " IPC7 ,CM to CPU2 IPC7 Flag Status" "0,1"
|
|
bitfld.long 0x00 6. " IPC6 ,CM to CPU2 IPC6 Flag Status" "0,1"
|
|
bitfld.long 0x00 5. " IPC5 ,CM to CPU2 IPC5 Flag Status" "0,1"
|
|
bitfld.long 0x00 4. " IPC4 ,CM to CPU2 IPC4 Flag Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " IPC3 ,CM to CPU2 IPC3 Flag Status" "0,1"
|
|
bitfld.long 0x00 2. " IPC2 ,CM to CPU2 IPC2 Flag Status" "0,1"
|
|
bitfld.long 0x00 1. " IPC1 ,CM to CPU2 IPC1 Flag Status" "0,1"
|
|
bitfld.long 0x00 0. " IPC0 ,CM to CPU2 IPC0 Flag Status" "0,1"
|
|
rgroup.long (d:0x400FD080+0x18)++0x03
|
|
line.long 0x00 "IPCCOUNTERL,IPCCOUNTERL Register"
|
|
rgroup.long (d:0x400FD080+0x1C)++0x03
|
|
line.long 0x00 "IPCCOUNTERH,IPCCOUNTERH Register"
|
|
rgroup.long (d:0x400FD080+0x20)++0x03
|
|
line.long 0x00 "CPU2TOCMIPCRECVCOM,CPU2TOCMIPCRECVCOM Register"
|
|
rgroup.long (d:0x400FD080+0x24)++0x03
|
|
line.long 0x00 "CPU2TOCMIPCRECVADDR,CPU2TOCMIPCRECVADDR Register"
|
|
rgroup.long (d:0x400FD080+0x28)++0x03
|
|
line.long 0x00 "CPU2TOCMIPCRECVDATA,CPU2TOCMIPCRECVDATA Register"
|
|
group.long (d:0x400FD080+0x2C)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCREPLY,CMTOCPU2IPCREPLY Register"
|
|
group.long (d:0x400FD080+0x30)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCSENDCOM,CMTOCPU2IPCSENDCOM Register"
|
|
group.long (d:0x400FD080+0x34)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCSENDADDR,CMTOCPU2IPCSENDADDR Register"
|
|
group.long (d:0x400FD080+0x38)++0x03
|
|
line.long 0x00 "CMTOCPU2IPCSENDDATA,CMTOCPU2IPCSENDDATA Register"
|
|
group.long (d:0x400FD080+0x3C)++0x03
|
|
line.long 0x00 "CPU2TOCMIPCREPLY,CPU2TOCMIPCREPLY Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "Modular Controller Area Network (MCAN)"
|
|
tree "MCANSS"
|
|
width 36.
|
|
rgroup.long (d:0x4007C400+0x00)++0x03
|
|
line.long 0x00 "MCANSS_PID,MCAN Subsystem Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C400+0x04)++0x03
|
|
line.long 0x00 "MCANSS_CTRL,MCAN Subsystem Control Register"
|
|
bitfld.long 0x00 6. " EXT_TS_CNTR_EN ,External Timestamp Counter Enable" "0,1"
|
|
bitfld.long 0x00 5. " AUTOWAKEUP ,Automatic Wakeup Enable" "0,1"
|
|
bitfld.long 0x00 4. " WAKEUPREQEN ,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x00 3. " DBGSUSP_FREE ,Debug Suspend Free" "0,1"
|
|
rgroup.long (d:0x4007C400+0x08)++0x03
|
|
line.long 0x00 "MCANSS_STAT,MCAN Subsystem Status Register"
|
|
bitfld.long 0x00 2. " ENABLE_FDOE ,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x00 1. " MEM_INIT_DONE ,Memory Initialization Done" "0,1"
|
|
bitfld.long 0x00 0. " RESET ,Soft Reset Status" "0,1"
|
|
group.long (d:0x4007C400+0x0C)++0x03
|
|
line.long 0x00 "MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status Clear" "0,1"
|
|
group.long (d:0x4007C400+0x10)++0x03
|
|
line.long 0x00 "MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Status" "0,1"
|
|
group.long (d:0x4007C400+0x14)++0x03
|
|
line.long 0x00 "MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable Clear" "0,1"
|
|
group.long (d:0x4007C400+0x18)++0x03
|
|
line.long 0x00 "MCANSS_IE,MCAN Subsystem Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable" "0,1"
|
|
rgroup.long (d:0x4007C400+0x1C)++0x03
|
|
line.long 0x00 "MCANSS_IES,MCAN Subsystem Interrupt Enable Status"
|
|
bitfld.long 0x00 0. " EXT_TS_CNTR_OVFL ,External Timestamp Counter Overflow Interrupt Enable Status" "0,1"
|
|
group.long (d:0x4007C400+0x20)++0x03
|
|
line.long 0x00 "MCANSS_EOI,MCAN Subsystem End of Interrupt"
|
|
hexmask.long 0x00 0.--7. 1. "EOI,External Timestamp Counter Overflow End of Interrupt"
|
|
group.long (d:0x4007C400+0x24)++0x03
|
|
line.long 0x00 "MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0"
|
|
hexmask.long 0x00 0.--23. 1. "PRESCALER,External Timestamp Prescaler"
|
|
rgroup.long (d:0x4007C400+0x28)++0x03
|
|
line.long 0x00 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter"
|
|
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,External Timestamp Counter Unserviced Rollover Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCAN"
|
|
width 13.
|
|
rgroup.long (d:0x4007C600+0x00)++0x03
|
|
line.long 0x00 "MCAN_CREL,MCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long 0x00 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long 0x00 0.--7. 1. "DAY,Time Stamp Day"
|
|
rgroup.long (d:0x4007C600+0x04)++0x03
|
|
line.long 0x00 "MCAN_ENDN,MCAN Endian Register"
|
|
group.long (d:0x4007C600+0x0C)++0x03
|
|
line.long 0x00 "MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 23. " TDC ,Transmitter Delay Compensation" "0,1"
|
|
bitfld.long 0x00 16.--20. " DBRP ,Data Bit Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " DTSEG1 ,Data Time Segment Before Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " DTSEG2 ,Data Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DSJW ,Data Resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x4007C600+0x10)++0x03
|
|
line.long 0x00 "MCAN_TEST,MCAN Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Receive Pin" "0,1"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "0,1"
|
|
group.long (d:0x4007C600+0x14)++0x03
|
|
line.long 0x00 "MCAN_RWD,MCAN RAM Watchdog"
|
|
hexmask.long 0x00 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long 0x00 0.--7. 1. "WDC,Watchdog Configuration"
|
|
group.long (d:0x4007C600+0x18)++0x03
|
|
line.long 0x00 "MCAN_CCCR,MCAN CC Control Register"
|
|
bitfld.long 0x00 15. " NISO ,Non-ISO Operation" "0,1"
|
|
bitfld.long 0x00 14. " TXP ,Transmit Pause" "0,1"
|
|
bitfld.long 0x00 13. " EFBI ,Edge Filtering During Bus Integration" "0,1"
|
|
bitfld.long 0x00 12. " PXHD ,Protocol Exception Handling Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " BRSE ,Bit Rate Switch Enable" "0,1"
|
|
bitfld.long 0x00 8. " FDOE ,Flexible Datarate Operation Enable" "0,1"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "0,1"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "0,1"
|
|
bitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "0,1"
|
|
group.long (d:0x4007C600+0x1C)++0x03
|
|
line.long 0x00 "MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 25.--31. " NSJW ,Nominal (Re)Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
hexmask.long 0x00 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
bitfld.long 0x00 0.--6. " NTSEG2 ,Nominal Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x4007C600+0x20)++0x03
|
|
line.long 0x00 "MCAN_TSCC,MCAN Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,1,2,3"
|
|
group.long (d:0x4007C600+0x24)++0x03
|
|
line.long 0x00 "MCAN_TSCV,MCAN Timestamp Counter Value"
|
|
hexmask.long 0x00 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long (d:0x4007C600+0x28)++0x03
|
|
line.long 0x00 "MCAN_TOCC,MCAN Timeout Counter Configuration"
|
|
hexmask.long 0x00 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "0,1"
|
|
group.long (d:0x4007C600+0x2C)++0x03
|
|
line.long 0x00 "MCAN_TOCV,MCAN Timeout Counter Value"
|
|
hexmask.long 0x00 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long (d:0x4007C600+0x40)++0x03
|
|
line.long 0x00 "MCAN_ECR,MCAN Error Counter Register"
|
|
hexmask.long 0x00 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "0,1"
|
|
bitfld.long 0x00 8.--14. " REC ,Receive Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
rgroup.long (d:0x4007C600+0x44)++0x03
|
|
line.long 0x00 "MCAN_PSR,MCAN Protocol Status Register"
|
|
bitfld.long 0x00 16.--22. " TDCV ,Transmitter Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 14. " PXE ,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x00 13. " RFDF ,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x00 12. " RBRS ,BRS Flag of Last Received CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " RESI ,ESI Flag of Last Received CAN FD Message" "0,1"
|
|
bitfld.long 0x00 8.--10. " DLEC ,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " BO ,Bus_Off Status" "0,1"
|
|
bitfld.long 0x00 6. " EW ,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " EP ,Error Passive" "0,1"
|
|
bitfld.long 0x00 3.--4. " ACT ,Node Activity" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x4007C600+0x48)++0x03
|
|
line.long 0x00 "MCAN_TDCR,MCAN Transmitter Delay Compensation Register"
|
|
bitfld.long 0x00 8.--14. " TDCO ,Transmitter Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 0.--6. " TDCF ,Transmitter Delay Compensation Filter Window Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x4007C600+0x50)++0x03
|
|
line.long 0x00 "MCAN_IR,MCAN Interrupt Register"
|
|
bitfld.long 0x00 29. " ARA ,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x00 28. " PED ,Protocol Error in Data Phase" "0,1"
|
|
bitfld.long 0x00 27. " PEA ,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x00 26. " WDI ,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BO ,Bus_Off Status" "0,1"
|
|
bitfld.long 0x00 24. " EW ,Warning Status" "0,1"
|
|
bitfld.long 0x00 23. " EP ,Error Passive" "0,1"
|
|
bitfld.long 0x00 22. " ELO ,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEU ,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x00 19. " DRX ,Message Stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x00 18. " TOO ,Timeout Occurred" "0,1"
|
|
bitfld.long 0x00 17. " MRAF ,Message RAM Access Failure" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " TSW ,Timestamp Wraparound" "0,1"
|
|
bitfld.long 0x00 15. " TEFL ,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 14. " TEFF ,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 13. " TEFW ,Tx Event FIFO Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. " TEFN ,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x00 11. " TFE ,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x00 10. " TCF ,Transmission Cancellation Finished" "0,1"
|
|
bitfld.long 0x00 9. " TC ,Transmission Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. " HPM ,High Priority Message" "0,1"
|
|
bitfld.long 0x00 7. " RF1L ,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x00 5. " RF1W ,Rx FIFO 1 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " RF1N ,Rx FIFO 1 New Message" "0,1"
|
|
bitfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 1. " RF0W ,Rx FIFO 0 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " RF0N ,Rx FIFO 0 New Message" "0,1"
|
|
group.long (d:0x4007C600+0x54)++0x03
|
|
line.long 0x00 "MCAN_IE,MCAN Interrupt Enable"
|
|
bitfld.long 0x00 29. " ARAE ,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x00 28. " PEDE ,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x00 27. " PEAE ,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x00 26. " WDIE ,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BOE ,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x00 24. " EWE ,Warning Status Enable" "0,1"
|
|
bitfld.long 0x00 23. " EPE ,Error Passive Enable" "0,1"
|
|
bitfld.long 0x00 22. " ELOE ,Error Logging Overflow Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEUE ,Bit Error Uncorrected Enable" "0,1"
|
|
bitfld.long 0x00 20. " BECE ,Bit Error Corrected Enable" "0,1"
|
|
bitfld.long 0x00 19. " DRXE ,Message Stored to Dedicated Rx Buffer Enable" "0,1"
|
|
bitfld.long 0x00 18. " TOOE ,Timeout Occurred Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MRAFE ,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x00 16. " TSWE ,Timestamp Wraparound Enable" "0,1"
|
|
bitfld.long 0x00 15. " TEFLE ,Tx Event FIFO Element Lost Enable" "0,1"
|
|
bitfld.long 0x00 14. " TEFFE ,Tx Event FIFO Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " TEFWE ,Tx Event FIFO Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 12. " TEFNE ,Tx Event FIFO New Entry Enable" "0,1"
|
|
bitfld.long 0x00 11. " TFEE ,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x00 10. " TCFE ,Transmission Cancellation Finished Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " TCE ,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x00 8. " HPME ,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x00 7. " RF1LE ,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 6. " RF1FE ,Rx FIFO 1 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " RF1WE ,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 4. " RF1NE ,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x00 3. " RF0LE ,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 2. " RF0FE ,Rx FIFO 0 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " RF0WE ,Rx FIFO 0 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 0. " RF0NE ,Rx FIFO 0 New Message Enable" "0,1"
|
|
group.long (d:0x4007C600+0x58)++0x03
|
|
line.long 0x00 "MCAN_ILS,MCAN Interrupt Line Select"
|
|
bitfld.long 0x00 29. " ARAL ,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x00 28. " PEDL ,Protocol Error in Data Phase Line" "0,1"
|
|
bitfld.long 0x00 27. " PEAL ,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x00 26. " WDIL ,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " BOL ,Bus_Off Status Line" "0,1"
|
|
bitfld.long 0x00 24. " EWL ,Warning Status Line" "0,1"
|
|
bitfld.long 0x00 23. " EPL ,Error Passive Line" "0,1"
|
|
bitfld.long 0x00 22. " ELOL ,Error Logging Overflow Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " BEUL ,Bit Error Uncorrected Line" "0,1"
|
|
bitfld.long 0x00 20. " BECL ,Bit Error Corrected Line" "0,1"
|
|
bitfld.long 0x00 19. " DRXL ,Message Stored to Dedicated Rx Buffer Line" "0,1"
|
|
bitfld.long 0x00 18. " TOOL ,Timeout Occurred Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MRAFL ,Message RAM Access Failure Line" "0,1"
|
|
bitfld.long 0x00 16. " TSWL ,Timestamp Wraparound Line" "0,1"
|
|
bitfld.long 0x00 15. " TEFLL ,Tx Event FIFO Element Lost Line" "0,1"
|
|
bitfld.long 0x00 14. " TEFFL ,Tx Event FIFO Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " TEFWL ,Tx Event FIFO Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 12. " TEFNL ,Tx Event FIFO New Entry Line" "0,1"
|
|
bitfld.long 0x00 11. " TFEL ,Tx FIFO Empty Line" "0,1"
|
|
bitfld.long 0x00 10. " TCFL ,Transmission Cancellation Finished Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " TCL ,Transmission Completed Line" "0,1"
|
|
bitfld.long 0x00 8. " HPML ,High Priority Message Line" "0,1"
|
|
bitfld.long 0x00 7. " RF1LL ,Rx FIFO 1 Message Lost Line" "0,1"
|
|
bitfld.long 0x00 6. " RF1FL ,Rx FIFO 1 Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " RF1WL ,Rx FIFO 1 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 4. " RF1NL ,Rx FIFO 1 New Message Line" "0,1"
|
|
bitfld.long 0x00 3. " RF0LL ,Rx FIFO 0 Message Lost Line" "0,1"
|
|
bitfld.long 0x00 2. " RF0FL ,Rx FIFO 0 Full Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " RF0WL ,Rx FIFO 0 Watermark Reached Line" "0,1"
|
|
bitfld.long 0x00 0. " RF0NL ,Rx FIFO 0 New Message Line" "0,1"
|
|
group.long (d:0x4007C600+0x5C)++0x03
|
|
line.long 0x00 "MCAN_ILE,MCAN Interrupt Line Enable"
|
|
bitfld.long 0x00 1. " EINT1 ,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0x00 0. " EINT0 ,Enable Interrupt Line 0" "0,1"
|
|
group.long (d:0x4007C600+0x80)++0x03
|
|
line.long 0x00 "MCAN_GFC,MCAN Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. " RRFS ,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x00 0. " RRFE ,Reject Remote Frames Extended" "0,1"
|
|
group.long (d:0x4007C600+0x84)++0x03
|
|
line.long 0x00 "MCAN_SIDFC,MCAN Standard ID Filter Configuration"
|
|
hexmask.long 0x00 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
group.long (d:0x4007C600+0x88)++0x03
|
|
line.long 0x00 "MCAN_XIDFC,MCAN Extended ID Filter Configuration"
|
|
bitfld.long 0x00 16.--22. " LSE ,List Size Extended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long (d:0x4007C600+0x90)++0x03
|
|
line.long 0x00 "MCAN_XIDAM,MCAN Extended ID and Mask"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long (d:0x4007C600+0x94)++0x03
|
|
line.long 0x00 "MCAN_HPMS,MCAN High Priority Message Status"
|
|
bitfld.long 0x00 15. " FLST ,Filter List" "0,1"
|
|
bitfld.long 0x00 8.--14. " FIDX ,Filter Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 6.--7. " MSI ,Message Storage Indicator" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BIDX ,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C600+0x98)++0x03
|
|
line.long 0x00 "MCAN_NDAT1,MCAN New Data 1"
|
|
bitfld.long 0x00 31. " ND31 ,New Data RX Buffer 31" "0,1"
|
|
bitfld.long 0x00 30. " ND30 ,New Data RX Buffer 30" "0,1"
|
|
bitfld.long 0x00 29. " ND29 ,New Data RX Buffer 29" "0,1"
|
|
bitfld.long 0x00 28. " ND28 ,New Data RX Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ND27 ,New Data RX Buffer 27" "0,1"
|
|
bitfld.long 0x00 26. " ND26 ,New Data RX Buffer 26" "0,1"
|
|
bitfld.long 0x00 25. " ND25 ,New Data RX Buffer 25" "0,1"
|
|
bitfld.long 0x00 24. " ND24 ,New Data RX Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ND23 ,New Data RX Buffer 23" "0,1"
|
|
bitfld.long 0x00 22. " ND22 ,New Data RX Buffer 22" "0,1"
|
|
bitfld.long 0x00 21. " ND21 ,New Data RX Buffer 21" "0,1"
|
|
bitfld.long 0x00 20. " ND20 ,New Data RX Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ND19 ,New Data RX Buffer 19" "0,1"
|
|
bitfld.long 0x00 18. " ND18 ,New Data RX Buffer 18" "0,1"
|
|
bitfld.long 0x00 17. " ND17 ,New Data RX Buffer 17" "0,1"
|
|
bitfld.long 0x00 16. " ND16 ,New Data RX Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ND15 ,New Data RX Buffer 15" "0,1"
|
|
bitfld.long 0x00 14. " ND14 ,New Data RX Buffer 14" "0,1"
|
|
bitfld.long 0x00 13. " ND13 ,New Data RX Buffer 13" "0,1"
|
|
bitfld.long 0x00 12. " ND12 ,New Data RX Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ND11 ,New Data RX Buffer 11" "0,1"
|
|
bitfld.long 0x00 10. " ND10 ,New Data RX Buffer 10" "0,1"
|
|
bitfld.long 0x00 9. " ND9 ,New Data RX Buffer 9" "0,1"
|
|
bitfld.long 0x00 8. " ND8 ,New Data RX Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ND7 ,New Data RX Buffer 7" "0,1"
|
|
bitfld.long 0x00 6. " ND6 ,New Data RX Buffer 6" "0,1"
|
|
bitfld.long 0x00 5. " ND5 ,New Data RX Buffer 5" "0,1"
|
|
bitfld.long 0x00 4. " ND4 ,New Data RX Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ND3 ,New Data RX Buffer 3" "0,1"
|
|
bitfld.long 0x00 2. " ND2 ,New Data RX Buffer 2" "0,1"
|
|
bitfld.long 0x00 1. " ND1 ,New Data RX Buffer 1" "0,1"
|
|
bitfld.long 0x00 0. " ND0 ,New Data RX Buffer 0" "0,1"
|
|
group.long (d:0x4007C600+0x9C)++0x03
|
|
line.long 0x00 "MCAN_NDAT2,MCAN New Data 2"
|
|
bitfld.long 0x00 31. " ND63 ,New Data RX Buffer 63" "0,1"
|
|
bitfld.long 0x00 30. " ND62 ,New Data RX Buffer 62" "0,1"
|
|
bitfld.long 0x00 29. " ND61 ,New Data RX Buffer 61" "0,1"
|
|
bitfld.long 0x00 28. " ND60 ,New Data RX Buffer 60" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " ND59 ,New Data RX Buffer 59" "0,1"
|
|
bitfld.long 0x00 26. " ND58 ,New Data RX Buffer 58" "0,1"
|
|
bitfld.long 0x00 25. " ND57 ,New Data RX Buffer 57" "0,1"
|
|
bitfld.long 0x00 24. " ND56 ,New Data RX Buffer 56" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " ND55 ,New Data RX Buffer 55" "0,1"
|
|
bitfld.long 0x00 22. " ND54 ,New Data RX Buffer 54" "0,1"
|
|
bitfld.long 0x00 21. " ND53 ,New Data RX Buffer 53" "0,1"
|
|
bitfld.long 0x00 20. " ND52 ,New Data RX Buffer 52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " ND51 ,New Data RX Buffer 51" "0,1"
|
|
bitfld.long 0x00 18. " ND50 ,New Data RX Buffer 50" "0,1"
|
|
bitfld.long 0x00 17. " ND49 ,New Data RX Buffer 49" "0,1"
|
|
bitfld.long 0x00 16. " ND48 ,New Data RX Buffer 48" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " ND47 ,New Data RX Buffer 47" "0,1"
|
|
bitfld.long 0x00 14. " ND46 ,New Data RX Buffer 46" "0,1"
|
|
bitfld.long 0x00 13. " ND45 ,New Data RX Buffer 45" "0,1"
|
|
bitfld.long 0x00 12. " ND44 ,New Data RX Buffer 44" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " ND43 ,New Data RX Buffer 43" "0,1"
|
|
bitfld.long 0x00 10. " ND42 ,New Data RX Buffer 42" "0,1"
|
|
bitfld.long 0x00 9. " ND41 ,New Data RX Buffer 41" "0,1"
|
|
bitfld.long 0x00 8. " ND40 ,New Data RX Buffer 40" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " ND39 ,New Data RX Buffer 39" "0,1"
|
|
bitfld.long 0x00 6. " ND38 ,New Data RX Buffer 38" "0,1"
|
|
bitfld.long 0x00 5. " ND37 ,New Data RX Buffer 37" "0,1"
|
|
bitfld.long 0x00 4. " ND36 ,New Data RX Buffer 36" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " ND35 ,New Data RX Buffer 35" "0,1"
|
|
bitfld.long 0x00 2. " ND34 ,New Data RX Buffer 34" "0,1"
|
|
bitfld.long 0x00 1. " ND33 ,New Data RX Buffer 33" "0,1"
|
|
bitfld.long 0x00 0. " ND32 ,New Data RX Buffer 32" "0,1"
|
|
group.long (d:0x4007C600+0xA0)++0x03
|
|
line.long 0x00 "MCAN_RXF0C,MCAN Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "0,1"
|
|
bitfld.long 0x00 24.--30. " F0WM ,Rx FIFO 0 Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 16.--22. " F0S ,Rx FIFO 0 Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long (d:0x4007C600+0xA4)++0x03
|
|
line.long 0x00 "MCAN_RXF0S,MCAN Rx FIFO 0 Status"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--6. " F0FL ,Rx FIFO 0 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x4007C600+0xA8)++0x03
|
|
line.long 0x00 "MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C600+0xAC)++0x03
|
|
line.long 0x00 "MCAN_RXBC,MCAN Rx Buffer Configuration"
|
|
hexmask.long 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
group.long (d:0x4007C600+0xB0)++0x03
|
|
line.long 0x00 "MCAN_RXF1C,MCAN Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 Operation Mode" "0,1"
|
|
bitfld.long 0x00 24.--30. " F1WM ,Rx FIFO 1 Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 16.--22. " F1S ,Rx FIFO 1 Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
hexmask.long 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long (d:0x4007C600+0xB4)++0x03
|
|
line.long 0x00 "MCAN_RXF1S,MCAN Rx FIFO 1 Status"
|
|
bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "0,1,2,3"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--6. " F1FL ,Rx FIFO 1 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
group.long (d:0x4007C600+0xB8)++0x03
|
|
line.long 0x00 "MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C600+0xBC)++0x03
|
|
line.long 0x00 "MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
group.long (d:0x4007C600+0xC0)++0x03
|
|
line.long 0x00 "MCAN_TXBC,MCAN Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "0,1"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long (d:0x4007C600+0xC4)++0x03
|
|
line.long 0x00 "MCAN_TXFQS,MCAN Tx FIFO / Queue Status"
|
|
bitfld.long 0x00 21. " TFQF ,Tx FIFO/Queue Full" "0,1"
|
|
bitfld.long 0x00 16.--20. " TFQP ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " TFFL ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C600+0xC8)++0x03
|
|
line.long 0x00 "MCAN_TXESC,MCAN Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long (d:0x4007C600+0xCC)++0x03
|
|
line.long 0x00 "MCAN_TXBRP,MCAN Tx Buffer Request Pending"
|
|
bitfld.long 0x00 31. " TRP31 ,Transmission Request Pending 31" "0,1"
|
|
bitfld.long 0x00 30. " TRP30 ,Transmission Request Pending 30" "0,1"
|
|
bitfld.long 0x00 29. " TRP29 ,Transmission Request Pending 29" "0,1"
|
|
bitfld.long 0x00 28. " TRP28 ,Transmission Request Pending 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " TRP27 ,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x00 26. " TRP26 ,Transmission Request Pending 26" "0,1"
|
|
bitfld.long 0x00 25. " TRP25 ,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x00 24. " TRP24 ,Transmission Request Pending 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TRP23 ,Transmission Request Pending 23" "0,1"
|
|
bitfld.long 0x00 22. " TRP22 ,Transmission Request Pending 22" "0,1"
|
|
bitfld.long 0x00 21. " TRP21 ,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x00 20. " TRP20 ,Transmission Request Pending 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TRP19 ,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x00 18. " TRP18 ,Transmission Request Pending 18" "0,1"
|
|
bitfld.long 0x00 17. " TRP17 ,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x00 16. " TRP16 ,Transmission Request Pending 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TRP15 ,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x00 14. " TRP14 ,Transmission Request Pending 14" "0,1"
|
|
bitfld.long 0x00 13. " TRP13 ,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x00 12. " TRP12 ,Transmission Request Pending 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TRP11 ,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x00 10. " TRP10 ,Transmission Request Pending 10" "0,1"
|
|
bitfld.long 0x00 9. " TRP9 ,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x00 8. " TRP8 ,Transmission Request Pending 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TRP7 ,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x00 6. " TRP6 ,Transmission Request Pending 6" "0,1"
|
|
bitfld.long 0x00 5. " TRP5 ,Transmission Request Pending 5" "0,1"
|
|
bitfld.long 0x00 4. " TRP4 ,Transmission Request Pending 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TRP3 ,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x00 2. " TRP2 ,Transmission Request Pending 2" "0,1"
|
|
bitfld.long 0x00 1. " TRP1 ,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x00 0. " TRP0 ,Transmission Request Pending 0" "0,1"
|
|
group.long (d:0x4007C600+0xD0)++0x03
|
|
line.long 0x00 "MCAN_TXBAR,MCAN Tx Buffer Add Request"
|
|
bitfld.long 0x00 31. " AR31 ,Add Request 31" "0,1"
|
|
bitfld.long 0x00 30. " AR30 ,Add Request 30" "0,1"
|
|
bitfld.long 0x00 29. " AR29 ,Add Request 29" "0,1"
|
|
bitfld.long 0x00 28. " AR28 ,Add Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " AR27 ,Add Request 27" "0,1"
|
|
bitfld.long 0x00 26. " AR26 ,Add Request 26" "0,1"
|
|
bitfld.long 0x00 25. " AR25 ,Add Request 25" "0,1"
|
|
bitfld.long 0x00 24. " AR24 ,Add Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " AR23 ,Add Request 23" "0,1"
|
|
bitfld.long 0x00 22. " AR22 ,Add Request 22" "0,1"
|
|
bitfld.long 0x00 21. " AR21 ,Add Request 21" "0,1"
|
|
bitfld.long 0x00 20. " AR20 ,Add Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " AR19 ,Add Request 19" "0,1"
|
|
bitfld.long 0x00 18. " AR18 ,Add Request 18" "0,1"
|
|
bitfld.long 0x00 17. " AR17 ,Add Request 17" "0,1"
|
|
bitfld.long 0x00 16. " AR16 ,Add Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " AR15 ,Add Request 15" "0,1"
|
|
bitfld.long 0x00 14. " AR14 ,Add Request 14" "0,1"
|
|
bitfld.long 0x00 13. " AR13 ,Add Request 13" "0,1"
|
|
bitfld.long 0x00 12. " AR12 ,Add Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " AR11 ,Add Request 11" "0,1"
|
|
bitfld.long 0x00 10. " AR10 ,Add Request 10" "0,1"
|
|
bitfld.long 0x00 9. " AR9 ,Add Request 9" "0,1"
|
|
bitfld.long 0x00 8. " AR8 ,Add Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " AR7 ,Add Request 7" "0,1"
|
|
bitfld.long 0x00 6. " AR6 ,Add Request 6" "0,1"
|
|
bitfld.long 0x00 5. " AR5 ,Add Request 5" "0,1"
|
|
bitfld.long 0x00 4. " AR4 ,Add Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " AR3 ,Add Request 3" "0,1"
|
|
bitfld.long 0x00 2. " AR2 ,Add Request 2" "0,1"
|
|
bitfld.long 0x00 1. " AR1 ,Add Request 1" "0,1"
|
|
bitfld.long 0x00 0. " AR0 ,Add Request 0" "0,1"
|
|
group.long (d:0x4007C600+0xD4)++0x03
|
|
line.long 0x00 "MCAN_TXBCR,MCAN Tx Buffer Cancellation Request"
|
|
bitfld.long 0x00 31. " CR31 ,Cancellation Request 31" "0,1"
|
|
bitfld.long 0x00 30. " CR30 ,Cancellation Request 30" "0,1"
|
|
bitfld.long 0x00 29. " CR29 ,Cancellation Request 29" "0,1"
|
|
bitfld.long 0x00 28. " CR28 ,Cancellation Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CR27 ,Cancellation Request 27" "0,1"
|
|
bitfld.long 0x00 26. " CR26 ,Cancellation Request 26" "0,1"
|
|
bitfld.long 0x00 25. " CR25 ,Cancellation Request 25" "0,1"
|
|
bitfld.long 0x00 24. " CR24 ,Cancellation Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CR23 ,Cancellation Request 23" "0,1"
|
|
bitfld.long 0x00 22. " CR22 ,Cancellation Request 22" "0,1"
|
|
bitfld.long 0x00 21. " CR21 ,Cancellation Request 21" "0,1"
|
|
bitfld.long 0x00 20. " CR20 ,Cancellation Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CR19 ,Cancellation Request 19" "0,1"
|
|
bitfld.long 0x00 18. " CR18 ,Cancellation Request 18" "0,1"
|
|
bitfld.long 0x00 17. " CR17 ,Cancellation Request 17" "0,1"
|
|
bitfld.long 0x00 16. " CR16 ,Cancellation Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CR15 ,Cancellation Request 15" "0,1"
|
|
bitfld.long 0x00 14. " CR14 ,Cancellation Request 14" "0,1"
|
|
bitfld.long 0x00 13. " CR13 ,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x00 12. " CR12 ,Cancellation Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CR11 ,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x00 10. " CR10 ,Cancellation Request 10" "0,1"
|
|
bitfld.long 0x00 9. " CR9 ,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x00 8. " CR8 ,Cancellation Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CR7 ,Cancellation Request 7" "0,1"
|
|
bitfld.long 0x00 6. " CR6 ,Cancellation Request 6" "0,1"
|
|
bitfld.long 0x00 5. " CR5 ,Cancellation Request 5" "0,1"
|
|
bitfld.long 0x00 4. " CR4 ,Cancellation Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CR3 ,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x00 2. " CR2 ,Cancellation Request 2" "0,1"
|
|
bitfld.long 0x00 1. " CR1 ,Cancellation Request 1" "0,1"
|
|
bitfld.long 0x00 0. " CR0 ,Cancellation Request 0" "0,1"
|
|
rgroup.long (d:0x4007C600+0xD8)++0x03
|
|
line.long 0x00 "MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x00 31. " TO31 ,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x00 30. " TO30 ,Transmission Occurred 30" "0,1"
|
|
bitfld.long 0x00 29. " TO29 ,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x00 28. " TO28 ,Transmission Occurred 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " TO27 ,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x00 26. " TO26 ,Transmission Occurred 26" "0,1"
|
|
bitfld.long 0x00 25. " TO25 ,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x00 24. " TO24 ,Transmission Occurred 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TO23 ,Transmission Occurred 23" "0,1"
|
|
bitfld.long 0x00 22. " TO22 ,Transmission Occurred 22" "0,1"
|
|
bitfld.long 0x00 21. " TO21 ,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x00 20. " TO20 ,Transmission Occurred 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TO19 ,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x00 18. " TO18 ,Transmission Occurred 18" "0,1"
|
|
bitfld.long 0x00 17. " TO17 ,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x00 16. " TO16 ,Transmission Occurred 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TO15 ,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x00 14. " TO14 ,Transmission Occurred 14" "0,1"
|
|
bitfld.long 0x00 13. " TO13 ,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x00 12. " TO12 ,Transmission Occurred 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TO11 ,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x00 10. " TO10 ,Transmission Occurred 10" "0,1"
|
|
bitfld.long 0x00 9. " TO9 ,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x00 8. " TO8 ,Transmission Occurred 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TO7 ,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x00 6. " TO6 ,Transmission Occurred 6" "0,1"
|
|
bitfld.long 0x00 5. " TO5 ,Transmission Occurred 5" "0,1"
|
|
bitfld.long 0x00 4. " TO4 ,Transmission Occurred 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TO3 ,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x00 2. " TO2 ,Transmission Occurred 2" "0,1"
|
|
bitfld.long 0x00 1. " TO1 ,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x00 0. " TO0 ,Transmission Occurred 0" "0,1"
|
|
rgroup.long (d:0x4007C600+0xDC)++0x03
|
|
line.long 0x00 "MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x00 31. " CF31 ,Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x00 30. " CF30 ,Cancellation Finished 30" "0,1"
|
|
bitfld.long 0x00 29. " CF29 ,Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x00 28. " CF28 ,Cancellation Finished 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CF27 ,Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x00 26. " CF26 ,Cancellation Finished 26" "0,1"
|
|
bitfld.long 0x00 25. " CF25 ,Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x00 24. " CF24 ,Cancellation Finished 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CF23 ,Cancellation Finished 23" "0,1"
|
|
bitfld.long 0x00 22. " CF22 ,Cancellation Finished 22" "0,1"
|
|
bitfld.long 0x00 21. " CF21 ,Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x00 20. " CF20 ,Cancellation Finished 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CF19 ,Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x00 18. " CF18 ,Cancellation Finished 18" "0,1"
|
|
bitfld.long 0x00 17. " CF17 ,Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x00 16. " CF16 ,Cancellation Finished 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CF15 ,Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x00 14. " CF14 ,Cancellation Finished 14" "0,1"
|
|
bitfld.long 0x00 13. " CF13 ,Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x00 12. " CF12 ,Cancellation Finished 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CF11 ,Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x00 10. " CF10 ,Cancellation Finished 10" "0,1"
|
|
bitfld.long 0x00 9. " CF9 ,Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x00 8. " CF8 ,Cancellation Finished 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CF7 ,Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x00 6. " CF6 ,Cancellation Finished 6" "0,1"
|
|
bitfld.long 0x00 5. " CF5 ,Cancellation Finished 5" "0,1"
|
|
bitfld.long 0x00 4. " CF4 ,Cancellation Finished 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CF3 ,Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x00 2. " CF2 ,Cancellation Finished 2" "0,1"
|
|
bitfld.long 0x00 1. " CF1 ,Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x00 0. " CF0 ,Cancellation Finished 0" "0,1"
|
|
group.long (d:0x4007C600+0xE0)++0x03
|
|
line.long 0x00 "MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x00 31. " TIE31 ,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x00 30. " TIE30 ,Transmission Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x00 29. " TIE29 ,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x00 28. " TIE28 ,Transmission Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " TIE27 ,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x00 26. " TIE26 ,Transmission Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x00 25. " TIE25 ,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x00 24. " TIE24 ,Transmission Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " TIE23 ,Transmission Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x00 22. " TIE22 ,Transmission Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x00 21. " TIE21 ,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x00 20. " TIE20 ,Transmission Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " TIE19 ,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x00 18. " TIE18 ,Transmission Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x00 17. " TIE17 ,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x00 16. " TIE16 ,Transmission Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " TIE15 ,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x00 14. " TIE14 ,Transmission Interrupt Enable 14" "0,1"
|
|
bitfld.long 0x00 13. " TIE13 ,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x00 12. " TIE12 ,Transmission Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " TIE11 ,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x00 10. " TIE10 ,Transmission Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x00 9. " TIE9 ,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x00 8. " TIE8 ,Transmission Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TIE7 ,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x00 6. " TIE6 ,Transmission Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x00 5. " TIE5 ,Transmission Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x00 4. " TIE4 ,Transmission Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " TIE3 ,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x00 2. " TIE2 ,Transmission Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x00 1. " TIE1 ,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x00 0. " TIE0 ,Transmission Interrupt Enable 0" "0,1"
|
|
group.long (d:0x4007C600+0xE4)++0x03
|
|
line.long 0x00 "MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x00 31. " CFIE31 ,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x00 30. " CFIE30 ,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
bitfld.long 0x00 29. " CFIE29 ,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x00 28. " CFIE28 ,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. " CFIE27 ,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x00 26. " CFIE26 ,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
bitfld.long 0x00 25. " CFIE25 ,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x00 24. " CFIE24 ,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " CFIE23 ,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x00 22. " CFIE22 ,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
bitfld.long 0x00 21. " CFIE21 ,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x00 20. " CFIE20 ,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " CFIE19 ,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x00 18. " CFIE18 ,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
bitfld.long 0x00 17. " CFIE17 ,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x00 16. " CFIE16 ,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " CFIE15 ,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x00 14. " CFIE14 ,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
bitfld.long 0x00 13. " CFIE13 ,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x00 12. " CFIE12 ,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " CFIE11 ,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x00 10. " CFIE10 ,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x00 9. " CFIE9 ,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x00 8. " CFIE8 ,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " CFIE7 ,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x00 6. " CFIE6 ,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x00 5. " CFIE5 ,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x00 4. " CFIE4 ,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " CFIE3 ,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x00 2. " CFIE2 ,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x00 1. " CFIE1 ,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x00 0. " CFIE0 ,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long (d:0x4007C600+0xF0)++0x03
|
|
line.long 0x00 "MCAN_TXEFC,MCAN Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long (d:0x4007C600+0xF4)++0x03
|
|
line.long 0x00 "MCAN_TXEFS,MCAN Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C600+0xF8)++0x03
|
|
line.long 0x00 "MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCANERR"
|
|
width 25.
|
|
rgroup.long (d:0x4007C800+0x00)++0x03
|
|
line.long 0x00 "MCANERR_REV,MCAN Error Aggregator Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C800+0x08)++0x03
|
|
line.long 0x00 "MCANERR_VECTOR,MCAN ECC Vector Register"
|
|
rbitfld.long 0x00 24. " RD_SVBUS_DONE ,Read Completion Flag" "0,1"
|
|
hexmask.long 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset"
|
|
bitfld.long 0x00 15. " RD_SVBUS ,Read Trigger" "0,1"
|
|
hexmask.long 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID"
|
|
rgroup.long (d:0x4007C800+0x0C)++0x03
|
|
line.long 0x00 "MCANERR_STAT,MCAN Error Misc Status"
|
|
hexmask.long 0x00 0.--10. 1. "NUM_RAMS,Number of RAMs"
|
|
rgroup.long (d:0x4007C800+0x10)++0x03
|
|
line.long 0x00 "MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Scheme" "0,1,2,3"
|
|
hexmask.long 0x00 16.--27. 1. "MODULE_ID,Module Identification Number"
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long (d:0x4007C800+0x14)++0x03
|
|
line.long 0x00 "MCANERR_CTRL,MCAN ECC Control"
|
|
bitfld.long 0x00 8. " CHECK_SVBUS_TIMEOUT ,SVBUS Timeout Enable" "0,1"
|
|
bitfld.long 0x00 6. " ERROR_ONCE ,Force Error Only Once Enable" "0,1"
|
|
bitfld.long 0x00 5. " FORCE_N_ROW ,Force Next Single/Double Bit Error" "0,1"
|
|
bitfld.long 0x00 4. " FORCE_DED ,Force Double Bit Error Detected Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FORCE_SEC ,Force Single Bit Error Corrected Error" "0,1"
|
|
bitfld.long 0x00 2. " ENABLE_RMW ,Enable Read-Modify-Write" "0,1"
|
|
bitfld.long 0x00 1. " ECC_CHECK ,Enable ECC Check" "0,1"
|
|
bitfld.long 0x00 0. " ECC_ENABLE ,Enable ECC Generation" "0,1"
|
|
group.long (d:0x4007C800+0x18)++0x03
|
|
line.long 0x00 "MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register"
|
|
group.long (d:0x4007C800+0x1C)++0x03
|
|
line.long 0x00 "MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register"
|
|
hexmask.long 0x00 16.--31. 1. "ECC_BIT2,Force Error Bit2 Column Index"
|
|
hexmask.long 0x00 0.--15. 1. "ECC_BIT1,Force Error Bit1 Column Index"
|
|
group.long (d:0x4007C800+0x20)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register"
|
|
hexmask.long 0x00 16.--31. 1. "ECC_BIT1,ECC Error Bit Position"
|
|
bitfld.long 0x00 15. " CLR_CTRL_REG_ERROR ,Clear Control Register Error" "0,1"
|
|
bitfld.long 0x00 12. " CLR_ECC_OTHER ,Clear ECC_OTHER" "0,1"
|
|
bitfld.long 0x00 10.--11. " CLR_ECC_DED ,Clear ECC_DED" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CLR_ECC_SEC ,Clear ECC_SEC" "0,1,2,3"
|
|
bitfld.long 0x00 7. " CTRL_REG_ERROR ,Control Register Error" "0,1"
|
|
bitfld.long 0x00 4. " ECC_OTHER ,SEC While Writeback Error Status" "0,1"
|
|
bitfld.long 0x00 2.--3. " ECC_DED ,Double Bit Error Detected Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " ECC_SEC ,Single Bit Error Corrected Status" "0,1,2,3"
|
|
rgroup.long (d:0x4007C800+0x24)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register"
|
|
rgroup.long (d:0x4007C800+0x28)++0x03
|
|
line.long 0x00 "MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register"
|
|
bitfld.long 0x00 9. " CLR_SVBUS_TIMEOUT ,Clear Serial VBUS Timeout" "0,1"
|
|
bitfld.long 0x00 1. " SVBUS_TIMEOUT ,Serial VBUS Timeout Flag" "0,1"
|
|
rbitfld.long 0x00 0. " WB_PEND ,Delayed Write Back Pending Status" "0,1"
|
|
group.long (d:0x4007C800+0x3C)++0x03
|
|
line.long 0x00 "MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI_WR ,End of Interrupt" "0,1"
|
|
group.long (d:0x4007C800+0x40)++0x03
|
|
line.long 0x00 "MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register"
|
|
bitfld.long 0x00 0. " MSGMEM_PEND ,Message RAM SEC Interrupt Pending" "0,1"
|
|
group.long (d:0x4007C800+0x80)++0x03
|
|
line.long 0x00 "MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_SET ,Message RAM SEC Interrupt Pending Enable Set" "0,1"
|
|
group.long (d:0x4007C800+0xC0)++0x03
|
|
line.long 0x00 "MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_CLR ,Message RAM SEC Interrupt Pending Enable Clear" "0,1"
|
|
group.long (d:0x4007C800+0x13C)++0x03
|
|
line.long 0x00 "MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register"
|
|
bitfld.long 0x00 0. " EOI_WR ,End of Interrupt" "0,1"
|
|
group.long (d:0x4007C800+0x140)++0x03
|
|
line.long 0x00 "MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register"
|
|
bitfld.long 0x00 0. " MSGMEM_PEND ,Message RAM DED Interrupt Pending" "0,1"
|
|
group.long (d:0x4007C800+0x180)++0x03
|
|
line.long 0x00 "MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_SET ,Message RAM DED Interrupt Pending Enable Set" "0,1"
|
|
group.long (d:0x4007C800+0x1C0)++0x03
|
|
line.long 0x00 "MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 0. " MSGMEM_ENABLE_CLR ,Message RAM DED Interrupt Pending Enable Clear" "0,1"
|
|
group.long (d:0x4007C800+0x200)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register"
|
|
bitfld.long 0x00 1. " ENABLE_TIMEOUT_SET ,Enable Timeout Errors Set" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE_PARITY_SET ,Enable Parity Errors Set" "0,1"
|
|
group.long (d:0x4007C800+0x204)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register"
|
|
bitfld.long 0x00 1. " ENABLE_TIMEOUT_CLR ,Enable Timeout Errors Clear" "0,1"
|
|
bitfld.long 0x00 0. " ENABLE_PARITY_CLR ,Enable Parity Errors Clear" "0,1"
|
|
group.long (d:0x4007C800+0x208)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register"
|
|
bitfld.long 0x00 2.--3. " SVBUS_TIMEOUT ,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AGGR_PARITY_ERR ,Aggregator Parity Error Status" "0,1,2,3"
|
|
group.long (d:0x4007C800+0x20C)++0x03
|
|
line.long 0x00 "MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register"
|
|
bitfld.long 0x00 2.--3. " SVBUS_TIMEOUT ,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " AGGR_PARITY_ERR ,Aggregator Parity Error Status" "0,1,2,3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Synchronous Serial Interface (SSI)"
|
|
width 14.
|
|
group.long (d:0x40008000+0x00)++0x03
|
|
line.long 0x00 "SSICR0,SSI Control 0"
|
|
hexmask.long 0x00 8.--15. 1. "SCR,SSI Serial Clock Rate"
|
|
bitfld.long 0x00 7. " SPH ,SSI Serial clock PHase" "0,1"
|
|
bitfld.long 0x00 6. " SPO ,SSI Serial clock POlarity" "0,1"
|
|
bitfld.long 0x00 4.--5. " FRF ,SSI FRame Format Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DSS ,SSI Data Size Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x40008000+0x04)++0x03
|
|
line.long 0x00 "SSICR1,SSI Control 1"
|
|
bitfld.long 0x00 10. " FSSHLDFRM ,FSS Hold Frame" "0,1"
|
|
bitfld.long 0x00 9. " HSCLKEN ,High Speed Clock Enable" "0,1"
|
|
bitfld.long 0x00 8. " DIR ,SSI Direction of Operation" "0,1"
|
|
bitfld.long 0x00 4. " EOT ,End of Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " MS ,SSI Master/Slave Select" "0,1"
|
|
bitfld.long 0x00 1. " SSE ,SSI Synchronous Serial Port Enable" "0,1"
|
|
bitfld.long 0x00 0. " LBM ,SSI Loopback Mode" "0,1"
|
|
group.long (d:0x40008000+0x08)++0x03
|
|
line.long 0x00 "SSIDR,SSI Data"
|
|
hexmask.long 0x00 0.--15. 1. "DATA,SSI Receive/Transmit Data"
|
|
rgroup.long (d:0x40008000+0x0C)++0x03
|
|
line.long 0x00 "SSISR,SSI Status"
|
|
bitfld.long 0x00 4. " BSY ,SSI Busy Bit" "0,1"
|
|
bitfld.long 0x00 3. " RFF ,SSI Receive FIFO Full" "0,1"
|
|
bitfld.long 0x00 2. " RNE ,SSI Receive FIFO Not Empty" "0,1"
|
|
bitfld.long 0x00 1. " TNF ,SSI Transmit FIFO Not Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " TFE ,SSI Transmit FIFO Empty" "0,1"
|
|
group.long (d:0x40008000+0x10)++0x03
|
|
line.long 0x00 "SSICPSR,SSI Clock Prescale"
|
|
hexmask.long 0x00 0.--7. 1. "CPSDVSR,SSI Clock Prescale Divisor"
|
|
group.long (d:0x40008000+0x14)++0x03
|
|
line.long 0x00 "SSIIM,SSI Interrupt Mask"
|
|
bitfld.long 0x00 6. " EOTIM ,End of Transmit Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 5. " DMATXIM ,SSI Transmit DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 4. " DMARXIM ,SSI Receive DMA Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 3. " TXIM ,SSI Transmit FIFO Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " RXIM ,SSI Receive FIFO Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 1. " RTIM ,SSI Receive Time-Out Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 0. " RORIM ,SSI Receive Overrun Interrupt Mask" "0,1"
|
|
rgroup.long (d:0x40008000+0x18)++0x03
|
|
line.long 0x00 "SSIRIS,SSI Raw Interrupt Status"
|
|
bitfld.long 0x00 6. " EOTRIS ,End of Transmit Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 5. " DMATXRIS ,SSI Transmit DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 4. " DMARXRIS ,SSI Receive DMA Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 3. " TXRIS ,SSI Transmit FIFO Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " RXRIS ,SSI Receive FIFO Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " RTRIS ,SSI Receive Time-Out Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x00 0. " RORRIS ,SSI Receive Overrun Raw Interrupt Status" "0,1"
|
|
rgroup.long (d:0x40008000+0x1C)++0x03
|
|
line.long 0x00 "SSIMIS,SSI Masked Interrupt Status"
|
|
bitfld.long 0x00 6. " EOTMIS ,End of Transmit Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 5. " DMATXMIS ,SSI Transmit DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 4. " DMARXMIS ,SSI Receive DMA Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 3. " TXMIS ,SSI Transmit FIFO Masked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " RXMIS ,SSI Receive FIFO Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 1. " RTMIS ,SSI Receive Time-Out Masked Interrupt Status" "0,1"
|
|
bitfld.long 0x00 0. " RORMIS ,SSI Receive Overrun Masked Interrupt Status" "0,1"
|
|
group.long (d:0x40008000+0x20)++0x03
|
|
line.long 0x00 "SSIICR,SSI Interrupt Clear"
|
|
bitfld.long 0x00 6. " EOTIC ,End of Transmit Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 5. " DMATXIC ,SSI Transmit DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 4. " DMARXIC ,SSI Receive DMA Interrupt Clear" "0,1"
|
|
bitfld.long 0x00 1. " RTIC ,SSI Receive Time-Out Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " RORIC ,SSI Receive Overrun Interrupt Clear" "0,1"
|
|
group.long (d:0x40008000+0x24)++0x03
|
|
line.long 0x00 "SSIDMACTL,SSI DMA Control"
|
|
bitfld.long 0x00 1. " TXDMAE ,Transmit DMA Enable" "0,1"
|
|
bitfld.long 0x00 0. " RXDMAE ,Receive DMA Enable" "0,1"
|
|
rgroup.long (d:0x40008000+0xFB0)++0x03
|
|
line.long 0x00 "SSIPV,SSI Peripheral Version"
|
|
hexmask.long 0x00 8.--15. 1. "MAJOR,Major Revision"
|
|
hexmask.long 0x00 0.--7. 1. "MINOR,Minor Revision"
|
|
rgroup.long (d:0x40008000+0xFC0)++0x03
|
|
line.long 0x00 "SSIPP,SSI Peripheral Properties"
|
|
bitfld.long 0x00 3. " FSSHLDFRM ,SSInFss Hold Frame Capability" "0,1"
|
|
bitfld.long 0x00 1.--2. " MODE ,Mode of Operation" "0,1,2,3"
|
|
bitfld.long 0x00 0. " HSCLK ,High Speed Capability" "0,1"
|
|
hgroup.long (d:0x40008000+0xFC4)++0x03
|
|
hide.long 0x00 "SSIPC,SSI Peripheral Configuration"
|
|
rgroup.long (d:0x40008000+0xFD0)++0x03
|
|
line.long 0x00 "SSIPeriphID4,SSI Peripheral Identification 4"
|
|
hexmask.long 0x00 0.--7. 1. "PID4,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFD4)++0x03
|
|
line.long 0x00 "SSIPeriphID5,SSI Peripheral Identification 5"
|
|
hexmask.long 0x00 0.--7. 1. "PID5,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFD8)++0x03
|
|
line.long 0x00 "SSIPeriphID6,SSI Peripheral Identification 6"
|
|
hexmask.long 0x00 0.--7. 1. "PID6,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFDC)++0x03
|
|
line.long 0x00 "SSIPeriphID7,SSI Peripheral Identification 7"
|
|
hexmask.long 0x00 0.--7. 1. "PID7,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFE0)++0x03
|
|
line.long 0x00 "SSIPeriphID0,SSI Peripheral Identification 0"
|
|
hexmask.long 0x00 0.--7. 1. "PID0,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFE4)++0x03
|
|
line.long 0x00 "SSIPeriphID1,SSI Peripheral Identification 1"
|
|
hexmask.long 0x00 0.--7. 1. "PID1,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFE8)++0x03
|
|
line.long 0x00 "SSIPeriphID2,SSI Peripheral Identification 2"
|
|
hexmask.long 0x00 0.--7. 1. "PID2,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFEC)++0x03
|
|
line.long 0x00 "SSIPeriphID3,SSI Peripheral Identification 3"
|
|
hexmask.long 0x00 0.--7. 1. "PID3,SSI Peripheral ID Register"
|
|
rgroup.long (d:0x40008000+0xFF0)++0x03
|
|
line.long 0x00 "SSIPCellID0,SSI PrimeCell Identification 0"
|
|
hexmask.long 0x00 0.--7. 1. "CID0,SSI PrimeCell ID Register"
|
|
rgroup.long (d:0x40008000+0xFF4)++0x03
|
|
line.long 0x00 "SSIPCellID1,SSI PrimeCell Identification 1"
|
|
hexmask.long 0x00 0.--7. 1. "CID1,SSI PrimeCell ID Register"
|
|
rgroup.long (d:0x40008000+0xFF8)++0x03
|
|
line.long 0x00 "SSIPCellID2,SSI PrimeCell Identification 2"
|
|
hexmask.long 0x00 0.--7. 1. "CID2,SSI PrimeCell ID Register"
|
|
rgroup.long (d:0x40008000+0xFFC)++0x03
|
|
line.long 0x00 "SSIPCellID3,SSI PrimeCell Identification 3"
|
|
hexmask.long 0x00 0.--7. 1. "CID3,SSI PrimeCell ID Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Universal Asynchronous Receiver/Transmitter (UART)"
|
|
width 9.
|
|
group.long (d:0x4000C000+0x04)++0x03
|
|
line.long 0x00 "UARTECR,UART Error Clear"
|
|
hexmask.long 0x00 0.--7. 1. "DATA,Error Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Micro Direct Memory Access (uDMA)"
|
|
width 16.
|
|
rgroup.long (d:0x400FF000+0x00)++0x03
|
|
line.long 0x00 "DMASTAT,DMA Status"
|
|
bitfld.long 0x00 16.--20. " DMACHANS ,Available DMA Channels Minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " STATE ,Control State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " MASTEN ,Master Enable Status" "0,1"
|
|
group.long (d:0x400FF000+0x04)++0x03
|
|
line.long 0x00 "DMACFG,DMA Configuration"
|
|
bitfld.long 0x00 0. " MASTEN ,Controller Master Enable" "0,1"
|
|
group.long (d:0x400FF000+0x08)++0x03
|
|
line.long 0x00 "DMACTLBASE,DMA Channel Control Base Pointer"
|
|
hexmask.long 0x00 10.--31. 1. "ADDR,Channel Control Base Address"
|
|
rgroup.long (d:0x400FF000+0x0C)++0x03
|
|
line.long 0x00 "DMAALTBASE,DMA Alternate Channel Control Base Pointer"
|
|
group.long (d:0x400FF000+0x14)++0x03
|
|
line.long 0x00 "DMASWREQ,DMA Channel Software Request"
|
|
group.long (d:0x400FF000+0x18)++0x03
|
|
line.long 0x00 "DMAUSEBURSTSET,DMA Channel Useburst Set"
|
|
group.long (d:0x400FF000+0x1C)++0x03
|
|
line.long 0x00 "DMAUSEBURSTCLR,DMA Channel Useburst Clear"
|
|
group.long (d:0x400FF000+0x20)++0x03
|
|
line.long 0x00 "DMAREQMASKSET,DMA Channel Request Mask Set"
|
|
group.long (d:0x400FF000+0x24)++0x03
|
|
line.long 0x00 "DMAREQMASKCLR,DMA Channel Request Mask Clear"
|
|
group.long (d:0x400FF000+0x28)++0x03
|
|
line.long 0x00 "DMAENASET,DMA Channel Enable Set"
|
|
group.long (d:0x400FF000+0x2C)++0x03
|
|
line.long 0x00 "DMAENACLR,DMA Channel Enable Clear"
|
|
group.long (d:0x400FF000+0x30)++0x03
|
|
line.long 0x00 "DMAALTSET,DMA Channel Primary Alternate Set"
|
|
group.long (d:0x400FF000+0x34)++0x03
|
|
line.long 0x00 "DMAALTCLR,DMA Channel Primary Alternate Clear"
|
|
group.long (d:0x400FF000+0x38)++0x03
|
|
line.long 0x00 "DMAPRIOSET,DMA Channel Priority Set"
|
|
group.long (d:0x400FF000+0x3C)++0x03
|
|
line.long 0x00 "DMAPRIOCLR,DMA Channel Priority Clear"
|
|
group.long (d:0x400FF000+0x4C)++0x03
|
|
line.long 0x00 "DMAERRCLR,DMA Bus Error Clear"
|
|
bitfld.long 0x00 0. " ERRCLR ,DMA Bus Error Status" "0,1"
|
|
group.long (d:0x400FF000+0x510)++0x03
|
|
line.long 0x00 "DMACHMAP0,DMA Channel Map Select 0"
|
|
bitfld.long 0x00 28.--31. " CH7SEL ,DMA Channel 7 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CH6SEL ,DMA Channel 6 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CH5SEL ,DMA Channel 5 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CH4SEL ,DMA Channel 4 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " CH3SEL ,DMA Channel 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH2SEL ,DMA Channel 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CH1SEL ,DMA Channel 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH0SEL ,DMA Channel 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400FF000+0x514)++0x03
|
|
line.long 0x00 "DMACHMAP1,DMA Channel Map Select 1"
|
|
bitfld.long 0x00 28.--31. " CH15SEL ,DMA Channel 15 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CH14SEL ,DMA Channel 14 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CH13SEL ,DMA Channel 13 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CH12SEL ,DMA Channel 12 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " CH11SEL ,DMA Channel 11 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH10SEL ,DMA Channel 10 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CH9SEL ,DMA Channel 9 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH8SEL ,DMA Channel 8 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400FF000+0x518)++0x03
|
|
line.long 0x00 "DMACHMAP2,DMA Channel Map Select 2"
|
|
bitfld.long 0x00 28.--31. " CH23SEL ,DMA Channel 23 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CH22SEL ,DMA Channel 22 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CH21SEL ,DMA Channel 21 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CH20SEL ,DMA Channel 20 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " CH19SEL ,DMA Channel 19 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH18SEL ,DMA Channel 18 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CH17SEL ,DMA Channel 17 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH16SEL ,DMA Channel 16 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (d:0x400FF000+0x51C)++0x03
|
|
line.long 0x00 "DMACHMAP3,DMA Channel Map Select 3"
|
|
bitfld.long 0x00 28.--31. " CH31SEL ,DMA Channel 31 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " CH30SEL ,DMA Channel 30 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CH29SEL ,DMA Channel 29 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CH28SEL ,DMA Channel 28 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " CH27SEL ,DMA Channel 27 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CH26SEL ,DMA Channel 26 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CH25SEL ,DMA Channel 25 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CH24SEL ,DMA Channel 24 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long (d:0x400FF000+0xFD0)++0x03
|
|
line.long 0x00 "DMAPeriphID4,DMA Peripheral Identification 4"
|
|
hexmask.long 0x00 0.--7. 1. "PID4,DMA Peripheral ID Register"
|
|
rgroup.long (d:0x400FF000+0xFE0)++0x03
|
|
line.long 0x00 "DMAPeriphID0,DMA Peripheral Identification 0"
|
|
hexmask.long 0x00 0.--7. 1. "PID0,DMA Peripheral ID Register [7:0]"
|
|
rgroup.long (d:0x400FF000+0xFE4)++0x03
|
|
line.long 0x00 "DMAPeriphID1,DMA Peripheral Identification 1"
|
|
hexmask.long 0x00 0.--7. 1. "PID1,DMA Peripheral ID Register [15:8]"
|
|
rgroup.long (d:0x400FF000+0xFE8)++0x03
|
|
line.long 0x00 "DMAPeriphID2,DMA Peripheral Identification 2"
|
|
hexmask.long 0x00 0.--7. 1. "PID2,DMA Peripheral ID Register [23:16]"
|
|
rgroup.long (d:0x400FF000+0xFEC)++0x03
|
|
line.long 0x00 "DMAPeriphID3,DMA Peripheral Identification 3"
|
|
hexmask.long 0x00 0.--7. 1. "PID3,DMA Peripheral ID Register [31:24]"
|
|
rgroup.long (d:0x400FF000+0xFF0)++0x03
|
|
line.long 0x00 "DMAPCellID0,DMA PrimeCell Identification 0"
|
|
hexmask.long 0x00 0.--7. 1. "CID0,DMA PrimeCell ID Register [7:0]"
|
|
rgroup.long (d:0x400FF000+0xFF4)++0x03
|
|
line.long 0x00 "DMAPCellID1,DMA PrimeCell Identification 1"
|
|
hexmask.long 0x00 0.--7. 1. "CID1,DMA PrimeCell ID Register [15:8]"
|
|
rgroup.long (d:0x400FF000+0xFF8)++0x03
|
|
line.long 0x00 "DMAPCellID2,DMA PrimeCell Identification 2"
|
|
hexmask.long 0x00 0.--7. 1. "CID2,DMA PrimeCell ID Register [23:16]"
|
|
rgroup.long (d:0x400FF000+0xFFC)++0x03
|
|
line.long 0x00 "DMAPCellID3,DMA PrimeCell Identification 3"
|
|
hexmask.long 0x00 0.--7. 1. "CID3,DMA PrimeCell ID Register [31:24]"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.OFF
|
|
newline
|