2030 lines
89 KiB
Plaintext
2030 lines
89 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: TMPM036 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-04-07 NEJ
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; @Manufacturer: TOSHIBA - Toshiba
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; @Doc: SVD generated, based on: M036.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: TMPM036FWFG
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertmpm036.per 14590 2022-04-08 08:39:47Z kwisniewski $
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
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line.long 0x18 "INT6,Interrupt Priority Register"
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bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ADC (10-bit Analog/Digital Converter)"
|
|
base ad:0x400FC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 6.--7. "ADCC,ADCC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "ADCLK,ADCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
rbitfld.long 0x00 7. "EOCFN,EOCFN" "0,1"
|
|
rbitfld.long 0x00 6. "ADBFN,ADBFN" "0,1"
|
|
bitfld.long 0x00 3.--4. "ITM,ITM" "0,1,2,3"
|
|
bitfld.long 0x00 2. "REPEAT,REPEAT" "0,1"
|
|
bitfld.long 0x00 1. "SCAN,SCAN" "0,1"
|
|
bitfld.long 0x00 0. "ADS,ADS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
bitfld.long 0x00 7. "VREFON,VREFON" "0,1"
|
|
bitfld.long 0x00 6. "I2AD,I2AD" "0,1"
|
|
bitfld.long 0x00 4.--5. "ADSCN,ADSCN" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "ADCH,ADCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
rbitfld.long 0x00 7. "EOCFHP,EOCFHP" "0,1"
|
|
rbitfld.long 0x00 6. "ADBFHP,ADBFHP" "0,1"
|
|
bitfld.long 0x00 5. "HPADCE,HPADCE" "0,1"
|
|
bitfld.long 0x00 0.--3. "HPADCH,HPADCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD3,AD Mode Control Register 3"
|
|
bitfld.long 0x00 5. "ADOBIC0,ADOBIC0" "0,1"
|
|
bitfld.long 0x00 1.--4. "ADREGS0,ADREGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "ADOBSV0,ADOBSV0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD4,AD Mode Control Register 4"
|
|
bitfld.long 0x00 7. "HADHS,HADHS" "0,1"
|
|
bitfld.long 0x00 6. "HADHTG,HADHTG" "0,1"
|
|
bitfld.long 0x00 5. "ADHS,ADHS" "0,1"
|
|
bitfld.long 0x00 4. "ADHTG,ADHTG" "0,1"
|
|
bitfld.long 0x00 0.--1. "ADRST,ADRST" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD5,AD Mode Control Register 5"
|
|
bitfld.long 0x00 5. "ADOBIC1,ADOBIC1" "0,1"
|
|
bitfld.long 0x00 1.--4. "ADREGS1,ADREGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "ADOBSV1,ADOBSV1" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MOD6,AD Mode Control Register 6"
|
|
bitfld.long 0x00 3. "ADM1DMA,ADM1DMA" "0,1"
|
|
bitfld.long 0x00 2. "ADM0DMA,ADM0DMA" "0,1"
|
|
bitfld.long 0x00 1. "ADHPDMA,ADHPDMA" "0,1"
|
|
bitfld.long 0x00 0. "ADDMA,ADDMA" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "REG0,AD Conversion Result Register 0"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR0,ADR0"
|
|
bitfld.long 0x00 1. "OVR0,OVR0" "0,1"
|
|
bitfld.long 0x00 0. "ADR0RF,ADR0RF" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR1,ADR1"
|
|
bitfld.long 0x00 1. "OVR1,OVR1" "0,1"
|
|
bitfld.long 0x00 0. "ADR1RF,ADR1RF" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR2,ADR2"
|
|
bitfld.long 0x00 1. "OVR2,OVR2" "0,1"
|
|
bitfld.long 0x00 0. "ADR2RF,ADR2RF" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR3,ADR3"
|
|
bitfld.long 0x00 1. "OVR3,OVR3" "0,1"
|
|
bitfld.long 0x00 0. "ADR3RF,ADR3RF" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR4,ADR4"
|
|
bitfld.long 0x00 1. "OVR4,OVR4" "0,1"
|
|
bitfld.long 0x00 0. "ADR4RF,ADR4RF" "0,1"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR5,ADR5"
|
|
bitfld.long 0x00 1. "OVR5,OVR5" "0,1"
|
|
bitfld.long 0x00 0. "ADR5RF,ADR5RF" "0,1"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR6,ADR6"
|
|
bitfld.long 0x00 1. "OVR6,OVR6" "0,1"
|
|
bitfld.long 0x00 0. "ADR6RF,ADR6RF" "0,1"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADR7,ADR7"
|
|
bitfld.long 0x00 1. "OVR7,OVR7" "0,1"
|
|
bitfld.long 0x00 0. "ADR7RF,ADR7RF" "0,1"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "REGSP,AD Conversion Result Register SP"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADRSP,ADRSP"
|
|
bitfld.long 0x00 1. "OBRSP,OBRSP" "0,1"
|
|
bitfld.long 0x00 0. "ADRSPRF,ADRSPRF" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result comparing register0"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADCOM0,ADCOM0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CMP1,AD Conversion result comparing register1"
|
|
hexmask.long.word 0x00 6.--15. 1. "ADCOM1,ADCOM1"
|
|
tree.end
|
|
tree "CG (Clock Generator Registers)"
|
|
base ad:0x400F3000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSCR,System Control Register"
|
|
bitfld.long 0x00 20. "FCSTOP,FCSTOP" "0,1"
|
|
bitfld.long 0x00 12. "FPSEL,FPSEL" "0,1"
|
|
bitfld.long 0x00 8.--10. "PRCK,PRCK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "GEAR,GEAR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCCR,Oscillation Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "WUODR,WUODR"
|
|
bitfld.long 0x00 19. "HWUPSEL,HWUPSEL" "0,1"
|
|
bitfld.long 0x00 18. "EHOSCSEL,EHOSCSEL" "0,1"
|
|
bitfld.long 0x00 17. "OSCSEL,OSCSEL" "0,1"
|
|
bitfld.long 0x00 16. "XEN2,XEN2" "0,1"
|
|
rbitfld.long 0x00 9. "OSCF,OSCF" "0,1"
|
|
bitfld.long 0x00 8. "XEN1,XEN1" "0,1"
|
|
bitfld.long 0x00 2. "PLLON,PLLON" "0,1"
|
|
rbitfld.long 0x00 1. "WUEF,WUEF" "0,1"
|
|
bitfld.long 0x00 0. "WUEON,WUEON" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STBYCR,Standby Control Register"
|
|
bitfld.long 0x00 0.--2. "STBY,STBY" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLLSEL,PLL Selection Register"
|
|
rbitfld.long 0x00 18. "PLLST,PLLST" "0,1"
|
|
hexmask.long.word 0x00 1.--15. 1. "PLLSET,PLLSET"
|
|
bitfld.long 0x00 0. "PLLSEL,PLLSEL" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PROTECT,Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CGPROTECT,CGPROTECT"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IMCGA,CG Interrupt Mode Control Register A"
|
|
bitfld.long 0x00 28.--30. "EMCG3,EMCG3" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 26.--27. "EMST3,EMST3" "0,1,2,3"
|
|
bitfld.long 0x00 24. "INT3EN,INT3EN" "0,1"
|
|
bitfld.long 0x00 20.--22. "EMCG2,EMCG2" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 18.--19. "EMST2,EMST2" "0,1,2,3"
|
|
bitfld.long 0x00 16. "INT2EN,INT2EN" "0,1"
|
|
bitfld.long 0x00 12.--14. "EMCG1,EMCG1" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 10.--11. "EMST1,EMST1" "0,1,2,3"
|
|
bitfld.long 0x00 8. "INT1EN,INT1EN" "0,1"
|
|
bitfld.long 0x00 4.--6. "EMCG0,EMCG0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 2.--3. "EMST0,EMST0" "0,1,2,3"
|
|
bitfld.long 0x00 0. "INT0EN,INT0EN" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IMCGB,CG Interrupt Mode Control Register B"
|
|
bitfld.long 0x00 12.--14. "EMCG5,EMCG5" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 10.--11. "EMST5,EMST5" "0,1,2,3"
|
|
bitfld.long 0x00 8. "INT5EN,INT5EN" "0,1"
|
|
bitfld.long 0x00 4.--6. "EMCG4,EMCG4" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 2.--3. "EMST4,EMST4" "0,1,2,3"
|
|
bitfld.long 0x00 0. "INT4EN,INT4EN" "0,1"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "ICRCG,CG Interrupt Request Clear Register"
|
|
bitfld.long 0x00 0.--4. "ICRCG,ICRCG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RSTFLG,Reset Flag Register"
|
|
bitfld.long 0x00 6. "LVDRSTF,LVDRSTF" "0,1"
|
|
bitfld.long 0x00 4. "SYSRSTF,SYSRSTF" "0,1"
|
|
bitfld.long 0x00 2. "WDTRSTF,WDTRSTF" "0,1"
|
|
bitfld.long 0x00 1. "PINRSTF,PINRSTF" "0,1"
|
|
bitfld.long 0x00 0. "PONRSTF,PONRSTF" "0,1"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "NMIFLG,NMI Flag Register"
|
|
bitfld.long 0x00 3. "NMIFLG3,NMIFLG3" "0,1"
|
|
bitfld.long 0x00 2. "NMIFLG2,NMIFLG2" "0,1"
|
|
bitfld.long 0x00 0. "NMIFLG0,NMIFLG0" "0,1"
|
|
tree.end
|
|
tree "DMACA (DMA Controller A)"
|
|
base ad:0x40000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTSTATUS,DMAC Interrupt status register"
|
|
bitfld.long 0x00 1. "INTSTATUS1,INTSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTSTATUS0,INTSTATUS0" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTTCSTATUS,DMAC Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "INTTCSTATUS1,INTTCSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCSTATUS0,INTTCSTATUS0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "INTTCCLEAR,DMAC Interrupt Terminal Count Clear Register"
|
|
bitfld.long 0x00 1. "INTTCCLEAR1,INTTCCLEAR1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCCLEAR0,INTTCCLEAR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTERRORSTATUS,DMAC Interrupt Error Status Register"
|
|
bitfld.long 0x00 1. "INTERRSTATUS1,INTERRSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRSTATUS0,INTERRSTATUS0" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "INTERRCLR,DMAC Interrupt Error Clear Register"
|
|
bitfld.long 0x00 1. "INTERRCLR1,INTERRCLR1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRCLR0,INTERRCLR0" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAWINTTCSTATUS,DMAC Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "RAWINTTCS1,RAWINTTCS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTTCS0,RAWINTTCS0" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAWINTERRORSTATUS,DMAC Raw Error Interrupt Status Register"
|
|
bitfld.long 0x00 1. "RAWINTERRS1,RAWINTERRS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTERRS0,RAWINTERRS0" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ENBLDCHNS,DMAC Enabled Channel Register"
|
|
bitfld.long 0x00 1. "ENABLEDCH1,ENABLEDCH1" "0,1"
|
|
bitfld.long 0x00 0. "ENABLEDCH0,ENABLEDCH0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOFTBREQ,DMAC Software Burst Request Register"
|
|
bitfld.long 0x00 15. "SOFTBREQ15,SOFTBREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTBREQ14,SOFTBREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTBREQ13,SOFTBREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTBREQ12,SOFTBREQ12" "0,1"
|
|
bitfld.long 0x00 11. "SOFTBREQ11,SOFTBREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTBREQ10,SOFTBREQ10" "0,1"
|
|
bitfld.long 0x00 9. "SOFTBREQ9,SOFTBREQ9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SOFTBREQ8,SOFTBREQ8" "0,1"
|
|
bitfld.long 0x00 7. "SOFTBREQ7,SOFTBREQ7" "0,1"
|
|
bitfld.long 0x00 6. "SOFTBREQ6,SOFTBREQ6" "0,1"
|
|
bitfld.long 0x00 5. "SOFTBREQ5,SOFTBREQ5" "0,1"
|
|
bitfld.long 0x00 4. "SOFTBREQ4,SOFTBREQ4" "0,1"
|
|
bitfld.long 0x00 3. "SOFTBREQ3,SOFTBREQ3" "0,1"
|
|
bitfld.long 0x00 2. "SOFTBREQ2,SOFTBREQ2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SOFTBREQ1,SOFTBREQ1" "0,1"
|
|
bitfld.long 0x00 0. "SOFTBREQ0,SOFTBREQ0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SOFTSREQ,DMAC Software Single Request Register"
|
|
bitfld.long 0x00 15. "SOFTSREQ15,SOFTSREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTSREQ14,SOFTSREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTSREQ13,SOFTSREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTSREQ12,SOFTSREQ12" "0,1"
|
|
bitfld.long 0x00 11. "SOFTSREQ11,SOFTSREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTSREQ10,SOFTSREQ10" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CONFIGURATION,DMAC Configuration Register"
|
|
bitfld.long 0x00 1. "M,M" "0,1"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0SRCADDR,DMAC Channel0 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "C0DESTADDR,DMAC Channel0 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "C0LLI,DMAC Channel0 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "C0CONTROL,DMAC Channel0 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0CONFIGURATION,DMAC Channel0 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1SRCADDR,DMAC Channel1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "C1DESTADDR,DMAC Channel1 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "C1LLI,DMAC Channel1 Linked List Item Register"
|
|
hexmask.long 0x00 1.--31. 1. "LLI,LLI"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "C1CONTROL,DMAC Channel1 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1CONFIGURATION,DMAC Channel1 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
tree.end
|
|
tree "DMACB (DMA Controller B)"
|
|
base ad:0x40001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTSTATUS,DMAC Interrupt status register"
|
|
bitfld.long 0x00 1. "INTSTATUS1,INTSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTSTATUS0,INTSTATUS0" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTTCSTATUS,DMAC Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "INTTCSTATUS1,INTTCSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCSTATUS0,INTTCSTATUS0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "INTTCCLEAR,DMAC Interrupt Terminal Count Clear Register"
|
|
bitfld.long 0x00 1. "INTTCCLEAR1,INTTCCLEAR1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCCLEAR0,INTTCCLEAR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTERRORSTATUS,DMAC Interrupt Error Status Register"
|
|
bitfld.long 0x00 1. "INTERRSTATUS1,INTERRSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRSTATUS0,INTERRSTATUS0" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "INTERRCLR,DMAC Interrupt Error Clear Register"
|
|
bitfld.long 0x00 1. "INTERRCLR1,INTERRCLR1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRCLR0,INTERRCLR0" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAWINTTCSTATUS,DMAC Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "RAWINTTCS1,RAWINTTCS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTTCS0,RAWINTTCS0" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAWINTERRORSTATUS,DMAC Raw Error Interrupt Status Register"
|
|
bitfld.long 0x00 1. "RAWINTERRS1,RAWINTERRS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTERRS0,RAWINTERRS0" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ENBLDCHNS,DMAC Enabled Channel Register"
|
|
bitfld.long 0x00 1. "ENABLEDCH1,ENABLEDCH1" "0,1"
|
|
bitfld.long 0x00 0. "ENABLEDCH0,ENABLEDCH0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOFTBREQ,DMAC Software Burst Request Register"
|
|
bitfld.long 0x00 15. "SOFTBREQ15,SOFTBREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTBREQ14,SOFTBREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTBREQ13,SOFTBREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTBREQ12,SOFTBREQ12" "0,1"
|
|
bitfld.long 0x00 11. "SOFTBREQ11,SOFTBREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTBREQ10,SOFTBREQ10" "0,1"
|
|
bitfld.long 0x00 9. "SOFTBREQ9,SOFTBREQ9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SOFTBREQ8,SOFTBREQ8" "0,1"
|
|
bitfld.long 0x00 7. "SOFTBREQ7,SOFTBREQ7" "0,1"
|
|
bitfld.long 0x00 6. "SOFTBREQ6,SOFTBREQ6" "0,1"
|
|
bitfld.long 0x00 5. "SOFTBREQ5,SOFTBREQ5" "0,1"
|
|
bitfld.long 0x00 4. "SOFTBREQ4,SOFTBREQ4" "0,1"
|
|
bitfld.long 0x00 3. "SOFTBREQ3,SOFTBREQ3" "0,1"
|
|
bitfld.long 0x00 2. "SOFTBREQ2,SOFTBREQ2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SOFTBREQ1,SOFTBREQ1" "0,1"
|
|
bitfld.long 0x00 0. "SOFTBREQ0,SOFTBREQ0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SOFTSREQ,DMAC Software Single Request Register"
|
|
bitfld.long 0x00 15. "SOFTSREQ15,SOFTSREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTSREQ14,SOFTSREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTSREQ13,SOFTSREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTSREQ12,SOFTSREQ12" "0,1"
|
|
bitfld.long 0x00 11. "SOFTSREQ11,SOFTSREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTSREQ10,SOFTSREQ10" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CONFIGURATION,DMAC Configuration Register"
|
|
bitfld.long 0x00 1. "M,M" "0,1"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0SRCADDR,DMAC Channel0 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "C0DESTADDR,DMAC Channel0 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "C0LLI,DMAC Channel0 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "C0CONTROL,DMAC Channel0 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0CONFIGURATION,DMAC Channel0 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1SRCADDR,DMAC Channel1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "C1DESTADDR,DMAC Channel1 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "C1LLI,DMAC Channel1 Linked List Item Register"
|
|
hexmask.long 0x00 1.--31. 1. "LLI,LLI"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "C1CONTROL,DMAC Channel1 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1CONFIGURATION,DMAC Channel1 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
tree.end
|
|
tree "DMACRQ (DMAC Request Control)"
|
|
base ad:0x4005F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "REDGE,DMAC Request Edge setting Register"
|
|
bitfld.long 0x00 1. "I2CDMAC1,I2CDMAC1" "0,1"
|
|
bitfld.long 0x00 0. "I2CDMAC0,I2CDMAC0" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "RCLR,DMAC Request Clear Register"
|
|
bitfld.long 0x00 1. "DCLR1,DCLR1" "0,1"
|
|
bitfld.long 0x00 0. "DCLR0,DCLR0" "0,1"
|
|
tree.end
|
|
tree "FC (Flash Control)"
|
|
base ad:0x41FFF000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SECBIT,FC Security Bit Register"
|
|
bitfld.long 0x00 0. "SECBIT,SECBIT" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SR,FC Flash Status Register"
|
|
bitfld.long 0x00 0. "RDY_BSY,RDY_BSY" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PSRA,FC Protect status register"
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
bitfld.long 0x00 0. "BLK0,BLK0" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PMRA,FC Protect Mask register"
|
|
bitfld.long 0x00 3. "BLKM3,BLKM3" "0,1"
|
|
bitfld.long 0x00 2. "BLKM2,BLKM2" "0,1"
|
|
bitfld.long 0x00 1. "BLKM1,BLKM1" "0,1"
|
|
bitfld.long 0x00 0. "BLKM0,BLKM0" "0,1"
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
repeat 2. (list 0. 1.) (list ad:0x400A0000 ad:0x400A1000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "ADO,ADO" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. "IE,IE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 0. "ISIC,ISIC" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "INTM (Interrupt Mask and Status Flag Register)"
|
|
base ad:0x400F5100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLG,Interrupt Status Flag register"
|
|
bitfld.long 0x00 9. "INTFLG9,INTFLG9" "0,1"
|
|
bitfld.long 0x00 8. "INTFLG8,INTFLG8" "0,1"
|
|
bitfld.long 0x00 7. "INTFLG7,INTFLG7" "0,1"
|
|
bitfld.long 0x00 6. "INTFLG6,INTFLG6" "0,1"
|
|
bitfld.long 0x00 5. "INTFLG5,INTFLG5" "0,1"
|
|
bitfld.long 0x00 4. "INTFLG4,INTFLG4" "0,1"
|
|
bitfld.long 0x00 3. "INTFLG3,INTFLG3" "0,1"
|
|
bitfld.long 0x00 2. "INTFLG2,INTFLG2" "0,1"
|
|
bitfld.long 0x00 1. "INTFLG1,INTFLG1" "0,1"
|
|
bitfld.long 0x00 0. "INTFLG0,INTFLG0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MASK,Interrupt Mask register"
|
|
bitfld.long 0x00 9. "INTMSK9,INTMSK9" "0,1"
|
|
bitfld.long 0x00 8. "INTMSK8,INTMSK8" "0,1"
|
|
bitfld.long 0x00 7. "INTMSK7,INTMSK7" "0,1"
|
|
bitfld.long 0x00 6. "INTMSK6,INTMSK6" "0,1"
|
|
bitfld.long 0x00 5. "INTMSK5,INTMSK5" "0,1"
|
|
bitfld.long 0x00 4. "INTMSK4,INTMSK4" "0,1"
|
|
bitfld.long 0x00 3. "INTMSK3,INTMSK3" "0,1"
|
|
bitfld.long 0x00 2. "INTMSK2,INTMSK2" "0,1"
|
|
bitfld.long 0x00 1. "INTMSK1,INTMSK1" "0,1"
|
|
bitfld.long 0x00 0. "INTMSK0,INTMSK0" "0,1"
|
|
tree.end
|
|
tree "LVD (Low Voltage Detection)"
|
|
base ad:0x400F4000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,LVD Control register"
|
|
rbitfld.long 0x00 7. "ST,ST" "0,1"
|
|
bitfld.long 0x00 6. "RSTEN,RSTEN" "0,1"
|
|
bitfld.long 0x00 5. "INTEN,INTEN" "0,1"
|
|
bitfld.long 0x00 4. "INTSEL,INTSEL" "0,1"
|
|
bitfld.long 0x00 1.--3. "LVL,LVL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
tree.end
|
|
tree "PA (Port A)"
|
|
base ad:0x400C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PA Data Register"
|
|
bitfld.long 0x00 7. "PA7,PA7" "0,1"
|
|
bitfld.long 0x00 6. "PA6,PA6" "0,1"
|
|
bitfld.long 0x00 5. "PA5,PA5" "0,1"
|
|
bitfld.long 0x00 4. "PA4,PA4" "0,1"
|
|
bitfld.long 0x00 3. "PA3,PA3" "0,1"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PA Control Register"
|
|
bitfld.long 0x00 7. "PA7C,PA7C" "0,1"
|
|
bitfld.long 0x00 6. "PA6C,PA6C" "0,1"
|
|
bitfld.long 0x00 5. "PA5C,PA5C" "0,1"
|
|
bitfld.long 0x00 4. "PA4C,PA4C" "0,1"
|
|
bitfld.long 0x00 3. "PA3C,PA3C" "0,1"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PA Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PA7OD,PA7OD" "0,1"
|
|
bitfld.long 0x00 6. "PA6OD,PA6OD" "0,1"
|
|
bitfld.long 0x00 5. "PA5OD,PA5OD" "0,1"
|
|
bitfld.long 0x00 4. "PA4OD,PA4OD" "0,1"
|
|
bitfld.long 0x00 3. "PA3OD,PA3OD" "0,1"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PA Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PA7UP,PA7UP" "0,1"
|
|
bitfld.long 0x00 6. "PA6UP,PA6UP" "0,1"
|
|
bitfld.long 0x00 5. "PA5UP,PA5UP" "0,1"
|
|
bitfld.long 0x00 4. "PA4UP,PA4UP" "0,1"
|
|
bitfld.long 0x00 3. "PA3UP,PA3UP" "0,1"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
bitfld.long 0x00 1. "PA1UP,PA1UP" "0,1"
|
|
bitfld.long 0x00 0. "PA0UP,PA0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PA Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PA7DN,PA7DN" "0,1"
|
|
bitfld.long 0x00 6. "PA6DN,PA6DN" "0,1"
|
|
bitfld.long 0x00 5. "PA5DN,PA5DN" "0,1"
|
|
bitfld.long 0x00 4. "PA4DN,PA4DN" "0,1"
|
|
bitfld.long 0x00 3. "PA3DN,PA3DN" "0,1"
|
|
bitfld.long 0x00 2. "PA2DN,PA2DN" "0,1"
|
|
bitfld.long 0x00 1. "PA1DN,PA1DN" "0,1"
|
|
bitfld.long 0x00 0. "PA0DN,PA0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PA Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PA7IE,PA7IE" "0,1"
|
|
bitfld.long 0x00 6. "PA6IE,PA6IE" "0,1"
|
|
bitfld.long 0x00 5. "PA5IE,PA5IE" "0,1"
|
|
bitfld.long 0x00 4. "PA4IE,PA4IE" "0,1"
|
|
bitfld.long 0x00 3. "PA3IE,PA3IE" "0,1"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
tree.end
|
|
tree "PB (Port B)"
|
|
base ad:0x400C0100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PB Data Register"
|
|
bitfld.long 0x00 7. "PB7,PB7" "0,1"
|
|
bitfld.long 0x00 6. "PB6,PB6" "0,1"
|
|
bitfld.long 0x00 5. "PB5,PB5" "0,1"
|
|
bitfld.long 0x00 4. "PB4,PB4" "0,1"
|
|
bitfld.long 0x00 3. "PB3,PB3" "0,1"
|
|
bitfld.long 0x00 2. "PB2,PB2" "0,1"
|
|
bitfld.long 0x00 1. "PB1,PB1" "0,1"
|
|
bitfld.long 0x00 0. "PB0,PB0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PB Control Register"
|
|
bitfld.long 0x00 7. "PB7C,PB7C" "0,1"
|
|
bitfld.long 0x00 6. "PB6C,PB6C" "0,1"
|
|
bitfld.long 0x00 5. "PB5C,PB5C" "0,1"
|
|
bitfld.long 0x00 4. "PB4C,PB4C" "0,1"
|
|
bitfld.long 0x00 3. "PB3C,PB3C" "0,1"
|
|
bitfld.long 0x00 2. "PB2C,PB2C" "0,1"
|
|
bitfld.long 0x00 1. "PB1C,PB1C" "0,1"
|
|
bitfld.long 0x00 0. "PB0C,PB0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PB Function Register 1"
|
|
bitfld.long 0x00 3. "PB3F1,PB3F1" "0,1"
|
|
bitfld.long 0x00 2. "PB2F1,PB2F1" "0,1"
|
|
bitfld.long 0x00 1. "PB1F1,PB1F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PB Function Register 2"
|
|
bitfld.long 0x00 2. "PB2F2,PB2F2" "0,1"
|
|
bitfld.long 0x00 1. "PB1F2,PB1F2" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PB Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PB7OD,PB7OD" "0,1"
|
|
bitfld.long 0x00 6. "PB6OD,PB6OD" "0,1"
|
|
bitfld.long 0x00 5. "PB5OD,PB5OD" "0,1"
|
|
bitfld.long 0x00 4. "PB4OD,PB4OD" "0,1"
|
|
bitfld.long 0x00 3. "PB3OD,PB3OD" "0,1"
|
|
bitfld.long 0x00 2. "PB2OD,PB2OD" "0,1"
|
|
bitfld.long 0x00 1. "PB1OD,PB1OD" "0,1"
|
|
bitfld.long 0x00 0. "PB0OD,PB0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PB Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PB7UP,PB7UP" "0,1"
|
|
bitfld.long 0x00 6. "PB6UP,PB6UP" "0,1"
|
|
bitfld.long 0x00 5. "PB5UP,PB5UP" "0,1"
|
|
bitfld.long 0x00 4. "PB4UP,PB4UP" "0,1"
|
|
bitfld.long 0x00 3. "PB3UP,PB3UP" "0,1"
|
|
bitfld.long 0x00 2. "PB2UP,PB2UP" "0,1"
|
|
bitfld.long 0x00 1. "PB1UP,PB1UP" "0,1"
|
|
bitfld.long 0x00 0. "PB0UP,PB0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PB Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PB7DN,PB7DN" "0,1"
|
|
bitfld.long 0x00 6. "PB6DN,PB6DN" "0,1"
|
|
bitfld.long 0x00 5. "PB5DN,PB5DN" "0,1"
|
|
bitfld.long 0x00 4. "PB4DN,PB4DN" "0,1"
|
|
bitfld.long 0x00 3. "PB3DN,PB3DN" "0,1"
|
|
bitfld.long 0x00 2. "PB2DN,PB2DN" "0,1"
|
|
bitfld.long 0x00 1. "PB1DN,PB1DN" "0,1"
|
|
bitfld.long 0x00 0. "PB0DN,PB0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PB Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PB7IE,PB7IE" "0,1"
|
|
bitfld.long 0x00 6. "PB6IE,PB6IE" "0,1"
|
|
bitfld.long 0x00 5. "PB5IE,PB5IE" "0,1"
|
|
bitfld.long 0x00 4. "PB4IE,PB4IE" "0,1"
|
|
bitfld.long 0x00 3. "PB3IE,PB3IE" "0,1"
|
|
bitfld.long 0x00 2. "PB2IE,PB2IE" "0,1"
|
|
bitfld.long 0x00 1. "PB1IE,PB1IE" "0,1"
|
|
bitfld.long 0x00 0. "PB0IE,PB0IE" "0,1"
|
|
tree.end
|
|
tree "PC (Port C)"
|
|
base ad:0x400C0200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PC Data Register"
|
|
bitfld.long 0x00 5. "PC5,PC5" "0,1"
|
|
bitfld.long 0x00 4. "PC4,PC4" "0,1"
|
|
bitfld.long 0x00 3. "PC3,PC3" "0,1"
|
|
bitfld.long 0x00 2. "PC2,PC2" "0,1"
|
|
bitfld.long 0x00 1. "PC1,PC1" "0,1"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PC Control Register"
|
|
bitfld.long 0x00 5. "PC5C,PC5C" "0,1"
|
|
bitfld.long 0x00 4. "PC4C,PC4C" "0,1"
|
|
bitfld.long 0x00 3. "PC3C,PC3C" "0,1"
|
|
bitfld.long 0x00 2. "PC2C,PC2C" "0,1"
|
|
bitfld.long 0x00 1. "PC1C,PC1C" "0,1"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PC Function Register 1"
|
|
bitfld.long 0x00 5. "PC5F1,PC5F1" "0,1"
|
|
bitfld.long 0x00 4. "PC4F1,PC4F1" "0,1"
|
|
bitfld.long 0x00 3. "PC3F1,PC3F1" "0,1"
|
|
bitfld.long 0x00 2. "PC2F1,PC2F1" "0,1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
bitfld.long 0x00 0. "PC0F1,PC0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PC Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PC5OD,PC5OD" "0,1"
|
|
bitfld.long 0x00 4. "PC4OD,PC4OD" "0,1"
|
|
bitfld.long 0x00 3. "PC3OD,PC3OD" "0,1"
|
|
bitfld.long 0x00 2. "PC2OD,PC2OD" "0,1"
|
|
bitfld.long 0x00 1. "PC1OD,PC1OD" "0,1"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PC Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PC5UP,PC5UP" "0,1"
|
|
bitfld.long 0x00 4. "PC4UP,PC4UP" "0,1"
|
|
bitfld.long 0x00 3. "PC3UP,PC3UP" "0,1"
|
|
bitfld.long 0x00 2. "PC2UP,PC2UP" "0,1"
|
|
bitfld.long 0x00 1. "PC1UP,PC1UP" "0,1"
|
|
bitfld.long 0x00 0. "PC0UP,PC0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PC Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PC5DN,PC5DN" "0,1"
|
|
bitfld.long 0x00 4. "PC4DN,PC4DN" "0,1"
|
|
bitfld.long 0x00 3. "PC3DN,PC3DN" "0,1"
|
|
bitfld.long 0x00 2. "PC2DN,PC2DN" "0,1"
|
|
bitfld.long 0x00 1. "PC1DN,PC1DN" "0,1"
|
|
bitfld.long 0x00 0. "PC0DN,PC0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PC Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PC5IE,PC5IE" "0,1"
|
|
bitfld.long 0x00 4. "PC4IE,PC4IE" "0,1"
|
|
bitfld.long 0x00 3. "PC3IE,PC3IE" "0,1"
|
|
bitfld.long 0x00 2. "PC2IE,PC2IE" "0,1"
|
|
bitfld.long 0x00 1. "PC1IE,PC1IE" "0,1"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
tree.end
|
|
tree "PD (Port D)"
|
|
base ad:0x400C0300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PD Data Register"
|
|
bitfld.long 0x00 5. "PD5,PD5" "0,1"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PD Control Register"
|
|
bitfld.long 0x00 5. "PD5C,PD5C" "0,1"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PD Function Register 1"
|
|
bitfld.long 0x00 4. "PD4F1,PD4F1" "0,1"
|
|
bitfld.long 0x00 3. "PD3F1,PD3F1" "0,1"
|
|
bitfld.long 0x00 2. "PD2F1,PD2F1" "0,1"
|
|
bitfld.long 0x00 1. "PD1F1,PD1F1" "0,1"
|
|
bitfld.long 0x00 0. "PD0F1,PD0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PD Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PD5OD,PD5OD" "0,1"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PD Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PD5UP,PD5UP" "0,1"
|
|
bitfld.long 0x00 4. "PD4UP,PD4UP" "0,1"
|
|
bitfld.long 0x00 3. "PD3UP,PD3UP" "0,1"
|
|
bitfld.long 0x00 2. "PD2UP,PD2UP" "0,1"
|
|
bitfld.long 0x00 1. "PD1UP,PD1UP" "0,1"
|
|
bitfld.long 0x00 0. "PD0UP,PD0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PD Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PD5DN,PD5DN" "0,1"
|
|
bitfld.long 0x00 4. "PD4DN,PD4DN" "0,1"
|
|
bitfld.long 0x00 3. "PD3DN,PD3DN" "0,1"
|
|
bitfld.long 0x00 2. "PD2DN,PD2DN" "0,1"
|
|
bitfld.long 0x00 1. "PD1DN,PD1DN" "0,1"
|
|
bitfld.long 0x00 0. "PD0DN,PD0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PD Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PD5IE,PD5IE" "0,1"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
tree.end
|
|
tree "PE (Port E)"
|
|
base ad:0x400C0400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PE Data Register"
|
|
bitfld.long 0x00 7. "PE7,PE7" "0,1"
|
|
bitfld.long 0x00 6. "PE6,PE6" "0,1"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 4. "PE4,PE4" "0,1"
|
|
bitfld.long 0x00 3. "PE3,PE3" "0,1"
|
|
bitfld.long 0x00 2. "PE2,PE2" "0,1"
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PE Control Register"
|
|
bitfld.long 0x00 7. "PE7C,PE7C" "0,1"
|
|
bitfld.long 0x00 6. "PE6C,PE6C" "0,1"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 4. "PE4C,PE4C" "0,1"
|
|
bitfld.long 0x00 3. "PE3C,PE3C" "0,1"
|
|
bitfld.long 0x00 2. "PE2C,PE2C" "0,1"
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PE Function Register 1"
|
|
bitfld.long 0x00 4. "PE4F1,PE4F1" "0,1"
|
|
bitfld.long 0x00 3. "PE3F1,PE3F1" "0,1"
|
|
bitfld.long 0x00 2. "PE2F1,PE2F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PE Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PE7OD,PE7OD" "0,1"
|
|
bitfld.long 0x00 6. "PE6OD,PE6OD" "0,1"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 4. "PE4OD,PE4OD" "0,1"
|
|
bitfld.long 0x00 3. "PE3OD,PE3OD" "0,1"
|
|
bitfld.long 0x00 2. "PE2OD,PE2OD" "0,1"
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PE Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PE7UP,PE7UP" "0,1"
|
|
bitfld.long 0x00 6. "PE6UP,PE6UP" "0,1"
|
|
bitfld.long 0x00 5. "PE5UP,PE5UP" "0,1"
|
|
bitfld.long 0x00 4. "PE4UP,PE4UP" "0,1"
|
|
bitfld.long 0x00 3. "PE3UP,PE3UP" "0,1"
|
|
bitfld.long 0x00 2. "PE2UP,PE2UP" "0,1"
|
|
bitfld.long 0x00 1. "PE1UP,PE1UP" "0,1"
|
|
bitfld.long 0x00 0. "PE0UP,PE0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PE Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PE7DN,PE7DN" "0,1"
|
|
bitfld.long 0x00 6. "PE6DN,PE6DN" "0,1"
|
|
bitfld.long 0x00 5. "PE5DN,PE5DN" "0,1"
|
|
bitfld.long 0x00 4. "PE4DN,PE4DN" "0,1"
|
|
bitfld.long 0x00 3. "PE3DN,PE3DN" "0,1"
|
|
bitfld.long 0x00 2. "PE2DN,PE2DN" "0,1"
|
|
bitfld.long 0x00 1. "PE1DN,PE1DN" "0,1"
|
|
bitfld.long 0x00 0. "PE0DN,PE0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PE Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PE7IE,PE7IE" "0,1"
|
|
bitfld.long 0x00 6. "PE6IE,PE6IE" "0,1"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 4. "PE4IE,PE4IE" "0,1"
|
|
bitfld.long 0x00 3. "PE3IE,PE3IE" "0,1"
|
|
bitfld.long 0x00 2. "PE2IE,PE2IE" "0,1"
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
tree.end
|
|
tree "PF (Port F)"
|
|
base ad:0x400C0500
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PF Data Register"
|
|
bitfld.long 0x00 7. "PF7,PF7" "0,1"
|
|
bitfld.long 0x00 6. "PF6,PF6" "0,1"
|
|
bitfld.long 0x00 5. "PF5,PF5" "0,1"
|
|
bitfld.long 0x00 4. "PF4,PF4" "0,1"
|
|
bitfld.long 0x00 3. "PF3,PF3" "0,1"
|
|
bitfld.long 0x00 2. "PF2,PF2" "0,1"
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PF Control Register"
|
|
bitfld.long 0x00 7. "PF7C,PF7C" "0,1"
|
|
bitfld.long 0x00 6. "PF6C,PF6C" "0,1"
|
|
bitfld.long 0x00 5. "PF5C,PF5C" "0,1"
|
|
bitfld.long 0x00 4. "PF4C,PF4C" "0,1"
|
|
bitfld.long 0x00 3. "PF3C,PF3C" "0,1"
|
|
bitfld.long 0x00 2. "PF2C,PF2C" "0,1"
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PF Function Register 1"
|
|
bitfld.long 0x00 5. "PF5F1,PF5F1" "0,1"
|
|
bitfld.long 0x00 4. "PF4F1,PF4F1" "0,1"
|
|
bitfld.long 0x00 3. "PF3F1,PF3F1" "0,1"
|
|
bitfld.long 0x00 2. "PF2F1,PF2F1" "0,1"
|
|
bitfld.long 0x00 1. "PF1F1,PF1F1" "0,1"
|
|
bitfld.long 0x00 0. "PF0F1,PF0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PF Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PF7OD,PF7OD" "0,1"
|
|
bitfld.long 0x00 6. "PF6OD,PF6OD" "0,1"
|
|
bitfld.long 0x00 5. "PF5OD,PF5OD" "0,1"
|
|
bitfld.long 0x00 4. "PF4OD,PF4OD" "0,1"
|
|
bitfld.long 0x00 3. "PF3OD,PF3OD" "0,1"
|
|
bitfld.long 0x00 2. "PF2OD,PF2OD" "0,1"
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PF Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PF7UP,PF7UP" "0,1"
|
|
bitfld.long 0x00 6. "PF6UP,PF6UP" "0,1"
|
|
bitfld.long 0x00 5. "PF5UP,PF5UP" "0,1"
|
|
bitfld.long 0x00 4. "PF4UP,PF4UP" "0,1"
|
|
bitfld.long 0x00 3. "PF3UP,PF3UP" "0,1"
|
|
bitfld.long 0x00 2. "PF2UP,PF2UP" "0,1"
|
|
bitfld.long 0x00 1. "PF1UP,PF1UP" "0,1"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PF Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PF7DN,PF7DN" "0,1"
|
|
bitfld.long 0x00 6. "PF6DN,PF6DN" "0,1"
|
|
bitfld.long 0x00 5. "PF5DN,PF5DN" "0,1"
|
|
bitfld.long 0x00 4. "PF4DN,PF4DN" "0,1"
|
|
bitfld.long 0x00 3. "PF3DN,PF3DN" "0,1"
|
|
bitfld.long 0x00 2. "PF2DN,PF2DN" "0,1"
|
|
bitfld.long 0x00 1. "PF1DN,PF1DN" "0,1"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PF Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PF7IE,PF7IE" "0,1"
|
|
bitfld.long 0x00 6. "PF6IE,PF6IE" "0,1"
|
|
bitfld.long 0x00 5. "PF5IE,PF5IE" "0,1"
|
|
bitfld.long 0x00 4. "PF4IE,PF4IE" "0,1"
|
|
bitfld.long 0x00 3. "PF3IE,PF3IE" "0,1"
|
|
bitfld.long 0x00 2. "PF2IE,PF2IE" "0,1"
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
tree.end
|
|
tree "PG (Port G)"
|
|
base ad:0x400C0600
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PG Data Register"
|
|
bitfld.long 0x00 7. "PG7,PG7" "0,1"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PG Control Register"
|
|
bitfld.long 0x00 7. "PG7C,PG7C" "0,1"
|
|
bitfld.long 0x00 6. "PG6C,PG6C" "0,1"
|
|
bitfld.long 0x00 5. "PG5C,PG5C" "0,1"
|
|
bitfld.long 0x00 4. "PG4C,PG4C" "0,1"
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PG Function Register 1"
|
|
bitfld.long 0x00 7. "PG7F1,PG7F1" "0,1"
|
|
bitfld.long 0x00 6. "PG6F1,PG6F1" "0,1"
|
|
bitfld.long 0x00 5. "PG5F1,PG5F1" "0,1"
|
|
bitfld.long 0x00 4. "PG4F1,PG4F1" "0,1"
|
|
bitfld.long 0x00 3. "PG3F1,PG3F1" "0,1"
|
|
bitfld.long 0x00 2. "PG2F1,PG2F1" "0,1"
|
|
bitfld.long 0x00 1. "PG1F1,PG1F1" "0,1"
|
|
bitfld.long 0x00 0. "PG0F1,PG0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PG Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PG7OD,PG7OD" "0,1"
|
|
bitfld.long 0x00 6. "PG6OD,PG6OD" "0,1"
|
|
bitfld.long 0x00 5. "PG5OD,PG5OD" "0,1"
|
|
bitfld.long 0x00 4. "PG4OD,PG4OD" "0,1"
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PG Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PG7UP,PG7UP" "0,1"
|
|
bitfld.long 0x00 6. "PG6UP,PG6UP" "0,1"
|
|
bitfld.long 0x00 5. "PG5UP,PG5UP" "0,1"
|
|
bitfld.long 0x00 4. "PG4UP,PG4UP" "0,1"
|
|
bitfld.long 0x00 3. "PG3UP,PG3UP" "0,1"
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
bitfld.long 0x00 1. "PG1UP,PG1UP" "0,1"
|
|
bitfld.long 0x00 0. "PG0UP,PG0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PG Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PG7DN,PG7DN" "0,1"
|
|
bitfld.long 0x00 6. "PG6DN,PG6DN" "0,1"
|
|
bitfld.long 0x00 5. "PG5DN,PG5DN" "0,1"
|
|
bitfld.long 0x00 4. "PG4DN,PG4DN" "0,1"
|
|
bitfld.long 0x00 3. "PG3DN,PG3DN" "0,1"
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
bitfld.long 0x00 1. "PG1DN,PG1DN" "0,1"
|
|
bitfld.long 0x00 0. "PG0DN,PG0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PG Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PG7IE,PG7IE" "0,1"
|
|
bitfld.long 0x00 6. "PG6IE,PG6IE" "0,1"
|
|
bitfld.long 0x00 5. "PG5IE,PG5IE" "0,1"
|
|
bitfld.long 0x00 4. "PG4IE,PG4IE" "0,1"
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
tree.end
|
|
tree "PH (Port H)"
|
|
base ad:0x400C0700
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PH Data Register"
|
|
bitfld.long 0x00 7. "PH7,PH7" "0,1"
|
|
bitfld.long 0x00 6. "PH6,PH6" "0,1"
|
|
bitfld.long 0x00 5. "PH5,PH5" "0,1"
|
|
bitfld.long 0x00 4. "PH4,PH4" "0,1"
|
|
bitfld.long 0x00 3. "PH3,PH3" "0,1"
|
|
bitfld.long 0x00 2. "PH2,PH2" "0,1"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PH Control Register"
|
|
bitfld.long 0x00 7. "PH7C,PH7C" "0,1"
|
|
bitfld.long 0x00 6. "PH6C,PH6C" "0,1"
|
|
bitfld.long 0x00 5. "PH5C,PH5C" "0,1"
|
|
bitfld.long 0x00 4. "PH4C,PH4C" "0,1"
|
|
bitfld.long 0x00 3. "PH3C,PH3C" "0,1"
|
|
bitfld.long 0x00 2. "PH2C,PH2C" "0,1"
|
|
bitfld.long 0x00 1. "PH1C,PH1C" "0,1"
|
|
bitfld.long 0x00 0. "PH0C,PH0C" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PH Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PH7OD,PH7OD" "0,1"
|
|
bitfld.long 0x00 6. "PH6OD,PH6OD" "0,1"
|
|
bitfld.long 0x00 5. "PH5OD,PH5OD" "0,1"
|
|
bitfld.long 0x00 4. "PH4OD,PH4OD" "0,1"
|
|
bitfld.long 0x00 3. "PH3OD,PH3OD" "0,1"
|
|
bitfld.long 0x00 2. "PH2OD,PH2OD" "0,1"
|
|
bitfld.long 0x00 1. "PH1OD,PH1OD" "0,1"
|
|
bitfld.long 0x00 0. "PH0OD,PH0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PH Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PH7UP,PH7UP" "0,1"
|
|
bitfld.long 0x00 6. "PH6UP,PH6UP" "0,1"
|
|
bitfld.long 0x00 5. "PH5UP,PH5UP" "0,1"
|
|
bitfld.long 0x00 4. "PH4UP,PH4UP" "0,1"
|
|
bitfld.long 0x00 3. "PH3UP,PH3UP" "0,1"
|
|
bitfld.long 0x00 2. "PH2UP,PH2UP" "0,1"
|
|
bitfld.long 0x00 1. "PH1UP,PH1UP" "0,1"
|
|
bitfld.long 0x00 0. "PH0UP,PH0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PH Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PH7DN,PH7DN" "0,1"
|
|
bitfld.long 0x00 6. "PH6DN,PH6DN" "0,1"
|
|
bitfld.long 0x00 5. "PH5DN,PH5DN" "0,1"
|
|
bitfld.long 0x00 4. "PH4DN,PH4DN" "0,1"
|
|
bitfld.long 0x00 3. "PH3DN,PH3DN" "0,1"
|
|
bitfld.long 0x00 2. "PH2DN,PH2DN" "0,1"
|
|
bitfld.long 0x00 1. "PH1DN,PH1DN" "0,1"
|
|
bitfld.long 0x00 0. "PH0DN,PH0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PH Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PH7IE,PH7IE" "0,1"
|
|
bitfld.long 0x00 6. "PH6IE,PH6IE" "0,1"
|
|
bitfld.long 0x00 5. "PH5IE,PH5IE" "0,1"
|
|
bitfld.long 0x00 4. "PH4IE,PH4IE" "0,1"
|
|
bitfld.long 0x00 3. "PH3IE,PH3IE" "0,1"
|
|
bitfld.long 0x00 2. "PH2IE,PH2IE" "0,1"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
tree.end
|
|
tree "PJ (Port J)"
|
|
base ad:0x400C0800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PJ Data Register"
|
|
bitfld.long 0x00 7. "PJ7,PJ7" "0,1"
|
|
bitfld.long 0x00 6. "PJ6,PJ6" "0,1"
|
|
bitfld.long 0x00 5. "PJ5,PJ5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4,PJ4" "0,1"
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PJ Control Register"
|
|
bitfld.long 0x00 7. "PJ7C,PJ7C" "0,1"
|
|
bitfld.long 0x00 6. "PJ6C,PJ6C" "0,1"
|
|
bitfld.long 0x00 5. "PJ5C,PJ5C" "0,1"
|
|
bitfld.long 0x00 4. "PJ4C,PJ4C" "0,1"
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PJ Function Register 1"
|
|
bitfld.long 0x00 2. "PJ2F1,PJ2F1" "0,1"
|
|
bitfld.long 0x00 1. "PJ1F1,PJ1F1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F1,PJ0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PJ Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PJ7OD,PJ7OD" "0,1"
|
|
bitfld.long 0x00 6. "PJ6OD,PJ6OD" "0,1"
|
|
bitfld.long 0x00 5. "PJ5OD,PJ5OD" "0,1"
|
|
bitfld.long 0x00 4. "PJ4OD,PJ4OD" "0,1"
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PJ Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PJ7UP,PJ7UP" "0,1"
|
|
bitfld.long 0x00 6. "PJ6UP,PJ6UP" "0,1"
|
|
bitfld.long 0x00 5. "PJ5UP,PJ5UP" "0,1"
|
|
bitfld.long 0x00 4. "PJ4UP,PJ4UP" "0,1"
|
|
bitfld.long 0x00 3. "PJ3UP,PJ3UP" "0,1"
|
|
bitfld.long 0x00 2. "PJ2UP,PJ2UP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1UP,PJ1UP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0UP,PJ0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PJ Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PJ7DN,PJ7DN" "0,1"
|
|
bitfld.long 0x00 6. "PJ6DN,PJ6DN" "0,1"
|
|
bitfld.long 0x00 5. "PJ5DN,PJ5DN" "0,1"
|
|
bitfld.long 0x00 4. "PJ4DN,PJ4DN" "0,1"
|
|
bitfld.long 0x00 3. "PJ3DN,PJ3DN" "0,1"
|
|
bitfld.long 0x00 2. "PJ2DN,PJ2DN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PJ Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PJ7IE,PJ7IE" "0,1"
|
|
bitfld.long 0x00 6. "PJ6IE,PJ6IE" "0,1"
|
|
bitfld.long 0x00 5. "PJ5IE,PJ5IE" "0,1"
|
|
bitfld.long 0x00 4. "PJ4IE,PJ4IE" "0,1"
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
tree.end
|
|
tree "PK (Port K)"
|
|
base ad:0x400C0900
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PK Data Register"
|
|
bitfld.long 0x00 6. "PK6,PK6" "0,1"
|
|
bitfld.long 0x00 5. "PK5,PK5" "0,1"
|
|
bitfld.long 0x00 4. "PK4,PK4" "0,1"
|
|
bitfld.long 0x00 3. "PK3,PK3" "0,1"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PK Control Register"
|
|
bitfld.long 0x00 6. "PK6C,PK6C" "0,1"
|
|
bitfld.long 0x00 5. "PK5C,PK5C" "0,1"
|
|
bitfld.long 0x00 4. "PK4C,PK4C" "0,1"
|
|
bitfld.long 0x00 3. "PK3C,PK3C" "0,1"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PK Function Register 1"
|
|
bitfld.long 0x00 6. "PK6F1,PK6F1" "0,1"
|
|
bitfld.long 0x00 5. "PK5F1,PK5F1" "0,1"
|
|
bitfld.long 0x00 4. "PK4F1,PK4F1" "0,1"
|
|
bitfld.long 0x00 1. "PK1F1,PK1F1" "0,1"
|
|
bitfld.long 0x00 0. "PK0F1,PK0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PK Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PK6OD,PK6OD" "0,1"
|
|
bitfld.long 0x00 5. "PK5OD,PK5OD" "0,1"
|
|
bitfld.long 0x00 4. "PK4OD,PK4OD" "0,1"
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PK Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PK6UP,PK6UP" "0,1"
|
|
bitfld.long 0x00 5. "PK5UP,PK5UP" "0,1"
|
|
bitfld.long 0x00 4. "PK4UP,PK4UP" "0,1"
|
|
bitfld.long 0x00 3. "PK3UP,PK3UP" "0,1"
|
|
bitfld.long 0x00 2. "PK2UP,PK2UP" "0,1"
|
|
bitfld.long 0x00 1. "PK1UP,PK1UP" "0,1"
|
|
bitfld.long 0x00 0. "PK0UP,PK0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PK Pull-Down Control Register"
|
|
bitfld.long 0x00 6. "PK6DN,PK6DN" "0,1"
|
|
bitfld.long 0x00 5. "PK5DN,PK5DN" "0,1"
|
|
bitfld.long 0x00 4. "PK4DN,PK4DN" "0,1"
|
|
bitfld.long 0x00 3. "PK3DN,PK3DN" "0,1"
|
|
bitfld.long 0x00 2. "PK2DN,PK2DN" "0,1"
|
|
bitfld.long 0x00 1. "PK1DN,PK1DN" "0,1"
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PK Input Enable Control Register"
|
|
bitfld.long 0x00 6. "PK6IE,PK6IE" "0,1"
|
|
bitfld.long 0x00 5. "PK5IE,PK5IE" "0,1"
|
|
bitfld.long 0x00 4. "PK4IE,PK4IE" "0,1"
|
|
bitfld.long 0x00 3. "PK3IE,PK3IE" "0,1"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
tree.end
|
|
tree "PL (Port L)"
|
|
base ad:0x400C0A00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PL Data Register"
|
|
bitfld.long 0x00 6. "PL6,PL6" "0,1"
|
|
bitfld.long 0x00 5. "PL5,PL5" "0,1"
|
|
bitfld.long 0x00 4. "PL4,PL4" "0,1"
|
|
bitfld.long 0x00 3. "PL3,PL3" "0,1"
|
|
bitfld.long 0x00 2. "PL2,PL2" "0,1"
|
|
bitfld.long 0x00 1. "PL1,PL1" "0,1"
|
|
bitfld.long 0x00 0. "PL0,PL0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PL Control Register"
|
|
bitfld.long 0x00 6. "PL6C,PL6C" "0,1"
|
|
bitfld.long 0x00 5. "PL5C,PL5C" "0,1"
|
|
bitfld.long 0x00 4. "PL4C,PL4C" "0,1"
|
|
bitfld.long 0x00 3. "PL3C,PL3C" "0,1"
|
|
bitfld.long 0x00 2. "PL2C,PL2C" "0,1"
|
|
bitfld.long 0x00 1. "PL1C,PL1C" "0,1"
|
|
bitfld.long 0x00 0. "PL0C,PL0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PL Function Register 1"
|
|
bitfld.long 0x00 5. "PL5F1,PL5F1" "0,1"
|
|
bitfld.long 0x00 4. "PL4F1,PL4F1" "0,1"
|
|
bitfld.long 0x00 3. "PL3F1,PL3F1" "0,1"
|
|
bitfld.long 0x00 2. "PL2F1,PL2F1" "0,1"
|
|
bitfld.long 0x00 1. "PL1F1,PL1F1" "0,1"
|
|
bitfld.long 0x00 0. "PL0F1,PL0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PL Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PL6OD,PL6OD" "0,1"
|
|
bitfld.long 0x00 5. "PL5OD,PL5OD" "0,1"
|
|
bitfld.long 0x00 4. "PL4OD,PL4OD" "0,1"
|
|
bitfld.long 0x00 3. "PL3OD,PL3OD" "0,1"
|
|
bitfld.long 0x00 2. "PL2OD,PL2OD" "0,1"
|
|
bitfld.long 0x00 1. "PL1OD,PL1OD" "0,1"
|
|
bitfld.long 0x00 0. "PL0OD,PL0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PL Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PL6UP,PL6UP" "0,1"
|
|
bitfld.long 0x00 5. "PL5UP,PL5UP" "0,1"
|
|
bitfld.long 0x00 4. "PL4UP,PL4UP" "0,1"
|
|
bitfld.long 0x00 3. "PL3UP,PL3UP" "0,1"
|
|
bitfld.long 0x00 2. "PL2UP,PL2UP" "0,1"
|
|
bitfld.long 0x00 1. "PL1UP,PL1UP" "0,1"
|
|
bitfld.long 0x00 0. "PL0UP,PL0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PL Pull-Down Control Register"
|
|
bitfld.long 0x00 6. "PL6DN,PL6DN" "0,1"
|
|
bitfld.long 0x00 5. "PL5DN,PL5DN" "0,1"
|
|
bitfld.long 0x00 4. "PL4DN,PL4DN" "0,1"
|
|
bitfld.long 0x00 3. "PL3DN,PL3DN" "0,1"
|
|
bitfld.long 0x00 2. "PL2DN,PL2DN" "0,1"
|
|
bitfld.long 0x00 1. "PL1DN,PL1DN" "0,1"
|
|
bitfld.long 0x00 0. "PL0DN,PL0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PL Input Enable Control Register"
|
|
bitfld.long 0x00 6. "PK6IE,PK6IE" "0,1"
|
|
bitfld.long 0x00 5. "PK5IE,PK5IE" "0,1"
|
|
bitfld.long 0x00 4. "PL4IE,PL4IE" "0,1"
|
|
bitfld.long 0x00 3. "PL3IE,PL3IE" "0,1"
|
|
bitfld.long 0x00 2. "PL2IE,PL2IE" "0,1"
|
|
bitfld.long 0x00 1. "PL1IE,PL1IE" "0,1"
|
|
bitfld.long 0x00 0. "PL0IE,PL0IE" "0,1"
|
|
tree.end
|
|
tree "PM (Port M)"
|
|
base ad:0x400C0B00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PM Data Register"
|
|
bitfld.long 0x00 2. "PM2,PM2" "0,1"
|
|
bitfld.long 0x00 1. "PM1,PM1" "0,1"
|
|
bitfld.long 0x00 0. "PM0,PM0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PM Control Register"
|
|
bitfld.long 0x00 2. "PM2C,PM2C" "0,1"
|
|
bitfld.long 0x00 1. "PM1C,PM1C" "0,1"
|
|
bitfld.long 0x00 0. "PM0C,PM0C" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PM Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PM2OD,PM2OD" "0,1"
|
|
bitfld.long 0x00 1. "PM1OD,PM1OD" "0,1"
|
|
bitfld.long 0x00 0. "PM0OD,PM0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PM Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PM2UP,PM2UP" "0,1"
|
|
bitfld.long 0x00 1. "PM1UP,PM1UP" "0,1"
|
|
bitfld.long 0x00 0. "PM0UP,PM0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PM Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PM2DN,PM2DN" "0,1"
|
|
bitfld.long 0x00 1. "PM1DN,PM1DN" "0,1"
|
|
bitfld.long 0x00 0. "PM0DN,PM0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PM Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PM2IE,PM2IE" "0,1"
|
|
bitfld.long 0x00 1. "PM1IE,PM1IE" "0,1"
|
|
bitfld.long 0x00 0. "PM0IE,PM0IE" "0,1"
|
|
tree.end
|
|
tree "PN (Port N)"
|
|
base ad:0x400C0C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PN Data Register"
|
|
bitfld.long 0x00 0. "PN0,PN0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PN Control Register"
|
|
bitfld.long 0x00 0. "PN0C,PN0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PN Function Register 1"
|
|
bitfld.long 0x00 0. "PN0F1,PN0F1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PN Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PN0OD,PN0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PN Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PN0UP,PN0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PN Pull-Down Control Register"
|
|
bitfld.long 0x00 0. "PN0DN,PN0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PN Input Enable Control Register"
|
|
bitfld.long 0x00 0. "PN0IE,PN0IE" "0,1"
|
|
tree.end
|
|
tree "SC (Serial Channel with 4bytes FIFO)"
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5.) (list ad:0x400E1000 ad:0x400E1100 ad:0x400E1200 ad:0x400E1300 ad:0x400E1400 ad:0x400E1500)
|
|
tree "SC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,SC Enable Register"
|
|
bitfld.long 0x00 1. "BRCKSEL,BRCKSEL" "0,1"
|
|
bitfld.long 0x00 0. "SIOE,SIOE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BUF,SC Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TB_RB,TB_RB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,SC Control Register"
|
|
bitfld.long 0x00 12.--14. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 8.--9. "TIDLE,TIDLE" "0,1,2,3"
|
|
rbitfld.long 0x00 7. "RB8,RB8" "0,1"
|
|
bitfld.long 0x00 6. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 5. "PE,PE" "0,1"
|
|
rbitfld.long 0x00 4. "OERR,OERR" "0,1"
|
|
rbitfld.long 0x00 3. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 2. "FERR,FERR" "0,1"
|
|
bitfld.long 0x00 1. "SCLKS,SCLKS" "0,1"
|
|
bitfld.long 0x00 0. "IOC,IOC" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD0,SC Mode Control Register 0"
|
|
bitfld.long 0x00 7. "TB8,TB8" "0,1"
|
|
bitfld.long 0x00 6. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 5. "RXE,RXE" "0,1"
|
|
bitfld.long 0x00 4. "WU,WU" "0,1"
|
|
bitfld.long 0x00 2.--3. "SM,SM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SC,SC" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRCR,SC Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 6. "BRADDE,BRADDE" "0,1"
|
|
bitfld.long 0x00 4.--5. "BRCK,BRCK" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BRADD,SC Baud Rate Generator Control Register 2"
|
|
bitfld.long 0x00 0.--3. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD1,SC Mode Control Register 1"
|
|
bitfld.long 0x00 7. "I2SC,I2SC" "0,1"
|
|
bitfld.long 0x00 5.--6. "FDPX,FDPX" "0,1,2,3"
|
|
bitfld.long 0x00 4. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 1.--3. "SINT,SINT" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MOD2,SC Mode Control Register 2"
|
|
rbitfld.long 0x00 7. "TBEMP,TBEMP" "0,1"
|
|
rbitfld.long 0x00 6. "RBFLL,RBFLL" "0,1"
|
|
rbitfld.long 0x00 5. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "DRCHG,DRCHG" "0,1"
|
|
bitfld.long 0x00 2. "WBUF,WBUF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RFC,SC RX FIFO Configuration Register"
|
|
bitfld.long 0x00 7. "RFCS,RFCS" "0,1"
|
|
bitfld.long 0x00 6. "RFIS,RFIS" "0,1"
|
|
bitfld.long 0x00 0.--1. "RIL,RIL" "0,1,2,3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TFC,SC TX FIFO Configuration Register"
|
|
bitfld.long 0x00 8. "TBCLR,TBCLR" "0,1"
|
|
bitfld.long 0x00 7. "TFCS,TFCS" "0,1"
|
|
bitfld.long 0x00 6. "TFIS,TFIS" "0,1"
|
|
bitfld.long 0x00 0.--1. "TIL,TIL" "0,1,2,3"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RST,SC RX FIFO Status Register"
|
|
bitfld.long 0x00 7. "ROR,ROR" "0,1"
|
|
bitfld.long 0x00 0.--2. "RLVL,RLVL" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TST,SC TX FIFO Status Register"
|
|
bitfld.long 0x00 7. "TUR,TUR" "0,1"
|
|
bitfld.long 0x00 0.--2. "TLVL,TLVL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FCNF,SC FIFO Configuration Register"
|
|
bitfld.long 0x00 4. "RFST,RFST" "0,1"
|
|
bitfld.long 0x00 3. "TFIE,TFIE" "0,1"
|
|
bitfld.long 0x00 2. "RFIE,RFIE" "0,1"
|
|
bitfld.long 0x00 1. "RXTXCNT,RXTXCNT" "0,1"
|
|
bitfld.long 0x00 0. "CNFG,CNFG" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMA,SC DMA Request Register"
|
|
bitfld.long 0x00 1. "DMAEN1,DMAEN1" "0,1"
|
|
bitfld.long 0x00 0. "DMAEN0,DMAEN0" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "TMR16A (16-bit Timer A)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x4008D000 ad:0x4008E000 ad:0x4008F000 ad:0x40090000)
|
|
tree "T16A$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,Enable Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "I2T16A,I2T16A" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RUN,RUN Register"
|
|
bitfld.long 0x00 0. "RUN,RUN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. "FFEN,FFEN" "0,1"
|
|
bitfld.long 0x00 4.--5. "FFCR,FFCR" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CLK,CLK" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RG,Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RG,RG"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CP,Capture Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CP,CP"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "TMRB (16-bit Timer/Event Counter)"
|
|
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9.) (list ad:0x400C4000 ad:0x400C4100 ad:0x400C4200 ad:0x400C4300 ad:0x400C4400 ad:0x400C4500 ad:0x400C4600 ad:0x400C4700 ad:0x400C4800 ad:0x400C4900)
|
|
tree "TB$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,TB Enable Register"
|
|
bitfld.long 0x00 7. "TBEN,TBEN" "0,1"
|
|
bitfld.long 0x00 6. "TBHALT,TBHALT" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RUN,TB RUN Register"
|
|
bitfld.long 0x00 2. "TBPRUN,TBPRUN" "0,1"
|
|
bitfld.long 0x00 0. "TBRUN,TBRUN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,TB Control Register"
|
|
bitfld.long 0x00 7. "TBWBF,TBWBF" "0,1"
|
|
bitfld.long 0x00 5. "TBSYNC,TBSYNC" "0,1"
|
|
bitfld.long 0x00 3. "I2TB,I2TB" "0,1"
|
|
bitfld.long 0x00 1. "TRGSEL,TRGSEL" "0,1"
|
|
bitfld.long 0x00 0. "CSSEL,CSSEL" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD,TB Mode Register"
|
|
bitfld.long 0x00 6. "TBCP,TBCP" "0,1"
|
|
bitfld.long 0x00 4.--5. "TBCPM,TBCPM" "0,1,2,3"
|
|
bitfld.long 0x00 3. "TBCLE,TBCLE" "0,1"
|
|
bitfld.long 0x00 0.--2. "TBCLK,TBCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FFCR,TB Flip-Flop Control Register"
|
|
bitfld.long 0x00 5. "TBC1T1,TBC1T1" "0,1"
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bitfld.long 0x00 4. "TBC0T1,TBC0T1" "0,1"
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bitfld.long 0x00 3. "TBE1T1,TBE1T1" "0,1"
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bitfld.long 0x00 2. "TBE0T1,TBE0T1" "0,1"
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bitfld.long 0x00 0.--1. "TBFF0C,TBFF0C" "0,1,2,3"
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rgroup.long 0x14++0x03
|
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line.long 0x00 "ST,TB Status Register"
|
|
bitfld.long 0x00 2. "INTTBOF,INTTBOF" "0,1"
|
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bitfld.long 0x00 1. "INTTB1,INTTB1" "0,1"
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bitfld.long 0x00 0. "INTTB0,INTTB0" "0,1"
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group.long 0x18++0x03
|
|
line.long 0x00 "IM,TB Interrupt Mask Register"
|
|
bitfld.long 0x00 2. "TBIMOF,TBIMOF" "0,1"
|
|
bitfld.long 0x00 1. "TBIM1,TBIM1" "0,1"
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bitfld.long 0x00 0. "TBIM0,TBIM0" "0,1"
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rgroup.long 0x1C++0x03
|
|
line.long 0x00 "UC,TB Read Capture Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TBUC,TBUC"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RG0,TB RG0 Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TBRG0,TBRG0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RG1,TB RG1 Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TBRG1,TBRG1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CP0,TB CP0 Capture Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TBCP0,TBCP0"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CP1,TB CP1 Capture Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TBCP1,TBCP1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMA,TB DMA Enable Register"
|
|
bitfld.long 0x00 2. "TBDMAEN2,TBDMAEN2" "0,1"
|
|
bitfld.long 0x00 1. "TBDMAEN1,TBDMAEN1" "0,1"
|
|
bitfld.long 0x00 0. "TBDMAEN0,TBDMAEN0" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400F2000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,WD Mode Register"
|
|
bitfld.long 0x00 7. "WDTE,WDTE" "0,1"
|
|
bitfld.long 0x00 4.--6. "WDTP,WDTP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "I2WDT,I2WDT" "0,1"
|
|
bitfld.long 0x00 1. "RESCR,RESCR" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CR,WD Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDCR,WDCR"
|
|
tree.end
|
|
autoindent.off
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newline
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