33146 lines
2.4 MiB
33146 lines
2.4 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32Lxx On-Chip Peripherals
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; @Props: Released
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; @Author: BIC, CNA, TAT, WIL
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; @Changelog:
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; 2010-12-20
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; 2012-05-02
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; 2016-04-11 WIL
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; 2016-05-04 WIL
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: CD00240193.pdf (2010-11-29); CD00277537.pdf (2010-12-16)
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; user_manual_CD00240193_new.pdf (Rev5 2012-01)
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; STM32L162xD_DM00039232.pdf (Rev2 2012-02)
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; STM32L151xC_STM32L152xC_DM00048356.pdf (Rev1 2012-02)
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; STM32L151xD_STM32L152xD_DM00034689.pdf (Rev2 2012-02)
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; datasheet_CD00277537(2).pdf (Rev2 2010-10)
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; flash_programming_CD00242299.pdf (Rev2 2010-10)
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; reference-CD00240193-1.pdf (Rev13 2015-07)
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; datasheet-DM00048356.pdf (Rev11 2015-08)
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; datasheet-DM00049732.pdf (Rev9 2015-08)
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; datasheet-DM00078689.pdf (Rev3 2015-02)
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; datasheet-DM00098321.pdf (Rev7 2015-04)
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; DM00150658.pdf (Rev2 2015-04)
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; DM00150671.pdf (Rev2 2015-04)
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; STM32L151QC_STM32L151QCH6_STM32L151RC-A_STM32L151RCT6A_to_STM32L152ZCT6TR.pdf
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; (Rev4 2014-09)
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; STM32L162RC-A_STM32L162RCT6A_STM32L162VC-A_STM32L162VCT6A.pdf
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; (Rev2 2014-09)
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; STM32L162RE_STM32L162RET6_STM32L162VE_STM32L162VET6_to_STM32L162ZET6.pdf
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; (Rev3 2014-10)
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; DM00078075.pdf (Rev4 2015-01)
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; DM00090183.pdf (Rev4 2015-04)
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; DM00108661.pdf (Rev4 2015-03)
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; @Core: Cortex-M3
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; @Chip: STM32L151C6-A STM32L151C8-A STM32L151CB-A STM32L151R6-A STM32L151R8-A
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; STM32L151RB-A STM32L151V8-A STM32L151VB-A STM32L152C6-A STM32L152C8-A
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; STM32L152CB-A STM32L152R6-A STM32L152R8-A STM32L152RB-A STM32L152V8-A
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; STM32L152VB-A STM32L151CC STM32L151RC-A STM32L151UC STM32L151VC-A STM32L152CC
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; STM32L152RC-A STM32L152VC-A STM32L162RC STM32L162RC-A STM32L162VC STM32L162VC-A
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; STM32L151QE STM32L151RE STM32L151VE STM32L152QE STM32L152RE STM32L152VE
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; STM32L162RE STM32L162VE STM32L162ZE STM32L151VD-X STM32L152VD-X STM32L162VD-X
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; STM32L100C6 STM32L100R8 STM32L100RB STM32L100C6-A STM32L100R8-A STM32L100RB-A
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; STM32L100RC
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32l.per 17736 2024-04-08 09:26:07Z kwisniewski $
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;
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; Known problems
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;
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; In STM32l162ZE there are channels 27-31 in ADC module, but those are reserved in ADC_CR1 register (bits 0-4)
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width 0x0B
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
|
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "Flash Memory Interface"
|
|
base ad:0x40023C00
|
|
width 15.
|
|
if ((per.l(ad:0x40023C00)&0x04)==0x04)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "FLASH_ACR,Flash Access Control Register"
|
|
bitfld.long 0x00 4. " RUN_PD ,Flash mode during Run" "Idle mode,Power down mode"
|
|
bitfld.long 0x00 3. " SLEEP_PD ,Flash mode during Sleep" "Idle mode,Power down mode"
|
|
bitfld.long 0x00 2. " ACC64 ,64-bit access" "32-bit,64-bit"
|
|
bitfld.long 0x00 1. " PRFTEN ,Prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LATENCY ,Latency" "Zero wait state,One wait state"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "FLASH_ACR,Flash Access Control Register"
|
|
bitfld.long 0x00 4. " RUN_PD ,Flash mode during Run" "Idle mode,Power down mode"
|
|
bitfld.long 0x00 3. " SLEEP_PD ,Flash mode during Sleep" "Idle mode,Power down mode"
|
|
bitfld.long 0x00 2. " ACC64 ,64-bit access" "32-bit,64-bit"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FLASH_PECR,Flash program erase control register"
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x00 18. " OBL_LAUNCH ,Launch the option byte loading" "Completed,Not completed"
|
|
bitfld.long 0x00 17. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EOPIE ,End of programming interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PARALLBANK ,Parallel bank mode" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 18. " OBL_LAUNCH ,Launch the option byte loading" "Completed,Not completed"
|
|
bitfld.long 0x00 17. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EOPIE ,End of programming interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " FPRG ,Half Page/Double Word programming mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ERASE ,Page or Double Word erase mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FTDW ,Fixed time data write for Byte, Half Word and Word programming with any previous erase operation" "No,Yes"
|
|
bitfld.long 0x00 4. " DATA ,Data EEPROM selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PROG ,Program memory selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " OPTLOCK ,Option bytes block lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " PRGLOCK ,Program memory lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " PELOCK ,FLASH_PECR and data EEPROM lock" "Not locked,Locked"
|
|
wgroup.long 0x08++0x0F
|
|
line.long 0x00 "FLASH_PDKEYR,Flash power down key register"
|
|
line.long 0x04 "FLASH_PEKEYR,Flash program erase key register"
|
|
line.long 0x08 "FLASH_PRGKEYR,Flash program memory key register"
|
|
line.long 0x0C "FLASH_OPTKEYR,Flash option key register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FLASH_SR,Flash status register"
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
eventfld.long 0x00 13. " RDERR ,Read protected error" "No error,Error"
|
|
eventfld.long 0x00 12. " OPTVERRUSR ,Option UserValidity Error" "No error,Error"
|
|
eventfld.long 0x00 11. " OPTVERR ,Option validity error" "No error,Error"
|
|
eventfld.long 0x00 10. " SIZERR ,Size error" "No error,Error"
|
|
textline " "
|
|
else
|
|
eventfld.long 0x00 13. " RDERR ,Read protected error" "No error,Error"
|
|
eventfld.long 0x00 11. " OPTVERR ,Option validity error" "No error,Error"
|
|
eventfld.long 0x00 10. " SIZERR ,Size error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 9. " PGAERR ,Programming alignment error" "No error,Error"
|
|
eventfld.long 0x00 8. " WRPERR ,Write protected error" "No error,Error"
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
rbitfld.long 0x00 3. " READY ,Flash ready after low power mode" "Not ready,Ready"
|
|
rbitfld.long 0x00 2. " ENDHV ,End of high voltage" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOP ,End of operation" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " BSY ,Write/erase operations in progress" "Not in progress,In progress"
|
|
else
|
|
bitfld.long 0x00 3. " READY ,Flash ready after low power mode" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ENDHV ,End of high voltage" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOP ,End of operation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " BSY ,Write/erase operations in progress" "Not in progress,In progress"
|
|
endif
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "FLASH_OBR,Option byte register"
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x00 23. " NBFB2 ,Boot from Bank2" "Flash Bank2/1,BOOT0 and BOOT1"
|
|
bitfld.long 0x00 22. " NRST_STDBY ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
bitfld.long 0x00 21. " NRST_STOP ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
bitfld.long 0x00 20. " IWDG_SW ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " NRST_STDBY ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
bitfld.long 0x00 21. " NRST_STOP ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
bitfld.long 0x00 20. " IWDG_SW ,This bit contains the user option byte loaded by the OBL" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--19. " BOR_LEV[3:0] ,Brownout reset threshold level" "Off,Off,Off,Off,Off,Off,Off,Off,LEVEL 1,LEVEL 2,LEVEL 3,LEVEL 4,LEVEL 5,?..."
|
|
textline " "
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")
|
|
bitfld.long 0x00 8. " SPRMOD ,Sector protection mode selection" "Write protection,Write and read protection"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDPRT[7:0] ,Read protection"
|
|
line.long 0x04 "FLASH_WRPR1,Flash write protection register 1"
|
|
bitfld.long 0x04 31. " WRP31 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 30. " WRP30 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 29. " WRP29 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 28. " WRP28 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " WRP27 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 26. " WRP26 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 25. " WRP25 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 24. " WRP24 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 23. " WRP23 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 22. " WRP22 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 21. " WRP21 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 20. " WRP20 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 19. " WRP19 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 18. " WRP18 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 17. " WRP17 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 16. " WRP16 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WRP15 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 14. " WRP14 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 13. " WRP13 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 12. " WRP12 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WRP11 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 10. " WRP10 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 9. " WRP9 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 8. " WRP8 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " WRP7 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 6. " WRP6 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 5. " WRP5 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 4. " WRP4 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WRP3 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 2. " WRP2 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 1. " WRP1 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x04 0. " WRP0 ,Write protection" "Not protected,Protected"
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "FLASH_WRPR2,Flash write protection register 2"
|
|
bitfld.long 0x00 31. " WRP31 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 30. " WRP30 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 29. " WRP29 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 28. " WRP28 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRP27 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 26. " WRP26 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 25. " WRP25 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 24. " WRP24 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WRP23 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 22. " WRP22 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 21. " WRP21 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 20. " WRP20 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WRP19 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 18. " WRP18 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 17. " WRP17 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 16. " WRP16 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WRP15 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 14. " WRP14 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 13. " WRP13 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 12. " WRP12 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WRP11 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 10. " WRP10 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 9. " WRP9 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " WRP8 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WRP7 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 6. " WRP6 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 5. " WRP5 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 4. " WRP4 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WRP3 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 2. " WRP2 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " WRP1 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " WRP0 ,Write protection" "Not protected,Protected"
|
|
endif
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FLASH_WRPR3,Flash write protection register 3"
|
|
bitfld.long 0x00 31. " WRP31 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 30. " WRP30 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 29. " WRP29 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 28. " WRP28 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRP27 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 26. " WRP26 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 25. " WRP25 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 24. " WRP24 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WRP23 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 22. " WRP22 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 21. " WRP21 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 20. " WRP20 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WRP19 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 18. " WRP18 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 17. " WRP17 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 16. " WRP16 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WRP15 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 14. " WRP14 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 13. " WRP13 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 12. " WRP12 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WRP11 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 10. " WRP10 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 9. " WRP9 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " WRP8 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WRP7 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 6. " WRP6 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 5. " WRP5 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 4. " WRP4 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WRP3 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 2. " WRP2 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " WRP1 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " WRP0 ,Write protection" "Not protected,Protected"
|
|
endif
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FLASH_WRPR4,Flash write protection register 4"
|
|
bitfld.long 0x00 31. " WRP31 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 30. " WRP30 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 29. " WRP29 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 28. " WRP28 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRP27 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 26. " WRP26 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 25. " WRP25 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 24. " WRP24 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WRP23 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 22. " WRP22 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 21. " WRP21 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 20. " WRP20 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WRP19 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 18. " WRP18 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 17. " WRP17 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 16. " WRP16 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WRP15 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 14. " WRP14 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 13. " WRP13 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 12. " WRP12 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WRP11 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 10. " WRP10 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 9. " WRP9 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 8. " WRP8 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WRP7 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 6. " WRP6 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 5. " WRP5 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 4. " WRP4 ,Write protection" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WRP3 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 2. " WRP2 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " WRP1 ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " WRP0 ,Write protection" "Not protected,Protected"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40023000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CRC_DR,Data Register"
|
|
sif cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_IDR,Independent Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDR ,General-purpose 8-bit Data Register Bits"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CRC_IDR,Independent Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " IDR ,General-purpose 8-bit Data Register Bits"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CRC_CR,Control Register"
|
|
bitfld.long 0x00 0. " RESET ,Reset Bit" "No reset,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWR (Power Control Register)"
|
|
base ad:0x40007000
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "PWR_CR,Power control register"
|
|
bitfld.long 0x00 14. " LPRUN ,Low power run mode" "Main mode,Low power mode"
|
|
bitfld.long 0x00 11.--12. " VOS ,Voltage scaling range selection" ",1.8V,1.5V,1.2V"
|
|
bitfld.long 0x00 10. " FWU ,Fast wakeup" "Vreftint ready,Vreftint ignored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ULP ,Ultralow power mode" "On,Off"
|
|
bitfld.long 0x00 8. " DBP ,Disable Backup Domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "1.9V,2.1V,2.3V,2.5V,2.7V,2.9V,3.1V,External source"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby"
|
|
bitfld.long 0x00 0. " LPDSR ,Low-Power Deepsleep" "Normal,Low-power"
|
|
line.long 0x04 "PWR_CSR,Power control/status register"
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP pin 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP pin 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
rbitfld.long 0x04 5. " REGLPF ,Regulator LP flag" "Main mode,Low power mode"
|
|
rbitfld.long 0x04 4. " VOSF ,Voltage Scaling select flag" "Ready,Not ready"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF ,Internal voltage reference ready flag" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD Output" "VDD>PVD threshold,VDD<PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,STANDBY Flag" "No standby,Standby"
|
|
rbitfld.long 0x04 0. " WUF ,Wake-Up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 5. " REGLPF ,Regulator LP flag" "Main mode,Low power mode"
|
|
bitfld.long 0x04 4. " VOSF ,Voltage Scaling select flag" "Ready,Not ready"
|
|
bitfld.long 0x04 3. " VREFINTRDYF ,Internal voltage reference ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PVDO ,PVD Output" "VDD>PVD threshold,VDD<PVD threshold"
|
|
bitfld.long 0x04 1. " SBF ,STANDBY Flag" "No standby,Standby"
|
|
bitfld.long 0x04 0. " WUF ,Wake-Up Flag" "No wake-up,Wake-up"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40023800
|
|
width 15.
|
|
if ((d.l(ad:0x40023800)&0x10000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 29.--30. " RTCPRE ,RTC/LCD prescaler" "/2,/4,/8,/16"
|
|
bitfld.long 0x00 28. " CSSON ,Clock Security System enable" "Off,On"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,HSE clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Off,On"
|
|
rbitfld.long 0x00 9. " MSIRDY ,MSI clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " MSION ,MSI clock enable" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high-speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal high-speed clock enable" "Off,On"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 28. " CSSON ,Clock Security System enable" "Off,On"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,HSE clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Off,On"
|
|
rbitfld.long 0x00 9. " MSIRDY ,MSI clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " MSION ,MSI clock enable" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high-speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal high-speed clock enable" "Off,On"
|
|
endif
|
|
group.long 0x04++0x33
|
|
line.long 0x00 "RCC_ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MSITRIM ,MSI clock trimming"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MSICAL ,MSI clock calibration"
|
|
bitfld.long 0x00 13.--15. " MSIRANGE ,MSI clock ranges" "65.536 kHz,131.072 kHz,262.144 kHz,524.288 kHz,1.048 MHz,2.097 MHz,4.194 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " HSITRIM ,High speed internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HSICAL ,Internal high speed clock calibration"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "/1,/2,/4,/8,/16,?..."
|
|
bitfld.long 0x04 24.--26. " MCOSEL ,Microcontroller clock output selection" "Disabled,SYSCLK,HSI,MSI,HSE,PLL,LSI,LSE"
|
|
bitfld.long 0x04 22.--23. " PLLDIV ,PLL output division" ",/2,/3,/4"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL multiplication factor" "x3,x4,x6,x8,x12,x16,x24,x32,x48,?..."
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI,HSE"
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16"
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x04 2.--3. " SWS ,System clock switch status" "MSI,HSI,HSE,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock switch" "MSI,HSI,HSE,PLL"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x08 22. " LSECSSC ,LSE CSS interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x08 21. " MSIRDYC ,MSI ready interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x08 14. " LSECSSIE ,LSE CSS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSIRDYIE ,MSI ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "No Interrupt,Interrupt"
|
|
rbitfld.long 0x08 6. " LSECSSF ,LSE CSS Interrupt flag" "No Interrupt,Interrupt"
|
|
rbitfld.long 0x08 5. " MSIRDYF ,MSI ready interrupt flag" "No Interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "No Interrupt,Interrupt"
|
|
rbitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "No Interrupt,Interrupt"
|
|
rbitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "No Interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "No Interrupt,Interrupt"
|
|
rbitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "No Interrupt,Interrupt"
|
|
line.long 0x0C "RCC_AHBRSTR,AHB peripheral reset register"
|
|
sif ((cpuis("STM32L162*")))
|
|
bitfld.long 0x0C 27. " AESRST ,AES reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x0C 25. " DMA2RST ,DMA2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 24. " DMA1RST ,DMA1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 15. " FLITFRST ,FLITF reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " CRCRST ,CRC reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x0C 7. " GPIOGRST ,IO port G reset" "No effect,Reset"
|
|
bitfld.long 0x0C 6. " GPIOFRST ,IO port F reset" "No effect,Reset"
|
|
bitfld.long 0x0C 5. " GPIOHRST ,IO port H reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " GPIOERST ,IO port E reset" "No effect,Reset"
|
|
bitfld.long 0x0C 3. " GPIODRST ,IO port D reset" "No effect,Reset"
|
|
bitfld.long 0x0C 2. " GPIOCRST ,IO port C reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " GPIOBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " GPIOARST ,IO port A reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 5. " GPIOHRST ,IO port H reset" "No effect,Reset"
|
|
bitfld.long 0x0C 4. " GPIOERST ,IO port E reset" "No effect,Reset"
|
|
bitfld.long 0x0C 3. " GPIODRST ,IO port D reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " GPIOCRST ,IO port C reset" "No effect,Reset"
|
|
bitfld.long 0x0C 1. " GPIOBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " GPIOARST ,IO port A reset" "No effect,Reset"
|
|
endif
|
|
line.long 0x10 "RCC_APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x10 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 9. " ADC1RST ,ADC1 interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 4. " TIM11RST ,TIM11 timer reset" "No effect,Reset"
|
|
bitfld.long 0x10 3. " TIM10RST ,TIM10 timer reset" "No effect,Reset"
|
|
bitfld.long 0x10 2. " TIM9RST ,TIM9 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 0. " SYSCFGRST ,System configuration controller reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_APB1RSTR,APB1 peripheral reset register"
|
|
bitfld.long 0x14 31. " COMPRST ,COMP interface reset" "No effect,Reset"
|
|
bitfld.long 0x14 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
bitfld.long 0x14 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 23. " USBRST ,USB reset" "No effect,Reset"
|
|
bitfld.long 0x14 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x14 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x14 20. " UART5RST ,UART 5 reset" "No effect,Reset"
|
|
bitfld.long 0x14 19. " UART4RST ,UART 4 reset" "No effect,Reset"
|
|
bitfld.long 0x14 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x14 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x14 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
bitfld.long 0x14 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x14 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x14 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 9. " LCDRST ,LCD reset" "No effect,Reset"
|
|
bitfld.long 0x14 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x14 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x14 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
bitfld.long 0x14 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x14 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x14 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x14 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
endif
|
|
line.long 0x18 "RCC_AHBENR,AHB peripheral clock enable register"
|
|
sif cpuis("STM32L162*")
|
|
bitfld.long 0x18 27. " AESEN ,AES clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x18 25. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 12. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x18 24. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x18 7. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 5. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB2ENR,APB2 peripheral clock enable register"
|
|
bitfld.long 0x1C 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " TIM11EN ,TIM11 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " TIM10EN ,TIM10 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TIM9EN ,TIM9 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " SYSCFGEN ,System configuration controller clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_APB1ENR,APB1 peripheral clock enable register"
|
|
bitfld.long 0x20 31. " COMPEN ,COMP interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 23. " USBEN ,USB clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x20 20. " UART5EN ,UART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 19. " UART4EN ,UART 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x20 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " LCDEN ,LCD clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x20 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x24 "RCC_AHBLPENR,AHB peripheral clock enable in low power mode register"
|
|
sif ((cpuis("STM32L162*")))
|
|
bitfld.long 0x24 27. " AESLPEN ,AES clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x24 25. " DMA2LPEN ,DMA2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 24. " DMA1LPEN ,DMA1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 16. " SRAMLPEN ,SRAM clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " FLITFLPEN ,FLITF clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 12. " CRCLPEN ,CRC clock enable during Sleep mode" "Disabled,Enabled"
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x24 7. " GPIOGLPEN ,IO port G clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " GPIOFLPEN ,IO port F clock enable during Sleep mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x24 5. " GPIOHLPEN ,IO port H clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " GPIOEEN ,IO port E clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 3. " GPIODEN ,IO port D clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 2. " GPIOCLPEN ,IO port C clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " GPIOBLPEN ,IO port B clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " GPIOALPEN ,IO port A clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x28 "RCC_APB2LPENR,APB2 peripheral clock enable in low power mode register"
|
|
bitfld.long 0x28 14. " USART1LPEN ,USART1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 12. " SPI1LPEN ,SPI 1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 9. " ADC1LPEN ,ADC1 interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " TIM11LPEN ,TIM11 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " TIM10LPEN ,TIM10 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " TIM9LPEN ,TIM9 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0. " SYSCFGLPEN ,System configuration controller clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x2C "RCC_APB1LPENR,APB1 peripheral clock enable in low power mode register"
|
|
bitfld.long 0x2C 31. " COMPLPEN ,COMP interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " DACLPEN ,DAC interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28. " PWRLPEN ,Power interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 23. " USBLPEN ,USB clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 22. " I2C2LPEN ,I2C 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 21. " I2C1LPEN ,I2C 1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x2C 20. " UART5LPEN ,USART 5 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 19. " UART4LPEN ,USART 4 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 18. " USART3LPEN ,USART 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 17. " USART2LPEN ,USART 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x2C 15. " SPI3LPEN ,SPI 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 14. " SPI2LPEN ,SPI 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 11. " WWDGLPEN ,Window watchdog clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 9. " LCDLPEN ,LCD clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " TIM7LPEN ,Timer 7 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 4. " TIM6LPEN ,Timer 6 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x2C 3. " TIM5LPEN ,Timer 5 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 2. " TIM4LPEN ,Timer 4 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 1. " TIM3LPEN ,Timer 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " TIM2LPEN ,Timer 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x30 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x30 31. " LPWRRSTF ,Low-power management reset" "Not occurred,Occurred"
|
|
bitfld.long 0x30 30. " WWDGRSTF ,Window watchdog reset" "Not occurred,Occurred"
|
|
bitfld.long 0x30 29. " IWDGRSTF ,Independent watchdog reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x30 28. " SFTRSTF ,Software reset" "Not occurred,Occurred"
|
|
bitfld.long 0x30 27. " PORRSTF ,POR/PDR reset" "Not occurred,Occurred"
|
|
bitfld.long 0x30 26. " PINRSTF ,PIN reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x30 25. " OBLRSTF , Options bytes loading reset" "Not occurred,Occurred"
|
|
bitfld.long 0x30 24. " RMVF ,Remove reset flag" "No effect,Cleared"
|
|
bitfld.long 0x30 23. " RTCRST ,RTC software reset" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x30 22. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 16.--17. " RTCSEL ,RTC and LCD clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
rbitfld.long 0x30 12. " LSECSSD ,CSS on LSE failure Detection" "Not detected,Detected"
|
|
bitfld.long 0x30 11. " LSECSSON ,CSS on LSE enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 10. " LSEBYP ,External low-speed oscillator bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x30 9. " LSERDY ,External low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x30 8. " LSEON ,External low-speed oscillator enable" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x30 1. " LSIRDY ,Internal low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x30 0. " LSION ,Internal low-speed oscillator enable" "Off,On"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40023800
|
|
width 14.
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x00 29.--30. " RTCPRE ,RTC/LCD prescaler" "HSE/2,HSE/4,HSE/8,HSE/16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 29.--30. " RTCPRE ,RTC prescaler" "HSE/2,HSE/4,HSE/8,HSE/16"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,HSE clock bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Off,On"
|
|
bitfld.long 0x00 9. " MSIRDY ,MSI clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " MSION ,MSI clock enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal high-speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal high-speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MSITRIM ,MSI clock trimming"
|
|
hexmask.long.byte 0x04 16.--23. 1. " MSICAL ,MSI clock calibration"
|
|
bitfld.long 0x04 13.--15. " MSIRANGE ,MSI clock ranges" "65.536 kHz,131.072 kHz,262.144 kHz,524.288 kHz,1.048 MHz,2.097 MHz,4.194 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " HSITRIM ,High speed internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " HSICAL ,Internal high speed clock calibration"
|
|
line.long 0x08 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x08 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "MCO,MCO/2,MCO/4,MCO/8,MCO/16,?..."
|
|
bitfld.long 0x08 24.--26. " MCOSEL ,Microcontroller clock output selection" "Disabled,SYSCLK,HSI,MSI,HSE,PLL,LSI,LSE"
|
|
bitfld.long 0x08 22.--23. " PLLDIV ,PLL output division" "Reserved,PLLVCO/2,PLLVCO/3,PLLVCO/4"
|
|
textline " "
|
|
bitfld.long 0x08 18.--21. " PLLMUL ,PLL multiplication factor" "PLL x 3,PLL x 4,PLL x 6,PLL x 8,PLL x 12,PLL x 16,PLL x 24,PLL x 32,PLL x 48,?..."
|
|
bitfld.long 0x08 16. " PLLSRC ,PLL entry clock source" "HSI,HSE"
|
|
bitfld.long 0x08 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x08 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
bitfld.long 0x08 2.--3. " SWS ,System clock switch status" "MSI,HSI,HSE,PLL"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SW ,System clock switch" "MSI,HSI,HSE,PLL"
|
|
line.long 0x0C "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x0C 23. " CSSC ,Clock Security System Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x0C 22. " LSECSSC ,LSE CSS interrupt clear" "No effect,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 21. " MSIRDYC ,MSI ready interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x0C 20. " PLLRDYC ,PLL Ready Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x0C 19. " HSERDYC ,HSE Ready Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " HSIRDYC ,HSI Ready Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x0C 17. " LSERDYC ,LSE Ready Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x0C 16. " LSIRDYC ,LSI Ready Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x0C 14. " LSECSSIE ,LSE CSS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 13. " MSIRDYIE ,MSI ready interrupt enable" "No effect,Cleared"
|
|
bitfld.long 0x0C 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x0C 6. " LSECSSF ,LSE CSS Interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 5. " MSIRDYF ,MSI ready interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x0C 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x0C 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x0C 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x0C 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x10 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x10 30. " FSMCRST ,FSMC reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L162*")))
|
|
bitfld.long 0x10 27. " AESRST ,AES reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x10 25. " DMA2RST ,DMA2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 24. " DMA1RST ,DMA1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 15. " FLITFRST ,FLITF reset" "No effect,Reset"
|
|
bitfld.long 0x10 12. " CRCRST ,CRC reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32L1??QD")||cpuis("STM32L1??QC")||cpuis("STM32L1??ZC")||cpuis("STM32L1??ZD"))
|
|
bitfld.long 0x10 7. " GPIOGRST ,IO port G reset" "No effect,Reset"
|
|
bitfld.long 0x10 6. " GPIOFRST ,IO port F reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 5. " GPIOHRST ,IO port H reset" "No effect,Reset"
|
|
textline " "
|
|
sif ((!cpuis("STM32L15?C?"))&&(!cpuis("STM32L1??R?")))
|
|
bitfld.long 0x10 4. " GPIOERST ,IO port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32L15?C?"))
|
|
bitfld.long 0x10 3. " GPIODRST ,IO port D reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 2. " GPIOCRST ,IO port C reset" "No effect,Reset"
|
|
bitfld.long 0x10 1. " GPIOBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " GPIOARST ,IO port A reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x14 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x14 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x14 11. " SDIORST ,SDIO reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 9. " ADC1RST ,ADC1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x14 4. " TIM11RST ,TIM11 timer reset" "No effect,Reset"
|
|
bitfld.long 0x14 3. " TIM10RST ,TIM10 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 2. " TIM9RST ,TIM9 timer reset" "No effect,Reset"
|
|
bitfld.long 0x14 0. " SYSCFGRST ,System configuration controller reset" "No effect,Reset"
|
|
line.long 0x18 "RCC_APB1RSTR,APB1 peripheral reset register"
|
|
bitfld.long 0x18 31. " COMPRST ,COMP interface reset" "No effect,Reset"
|
|
bitfld.long 0x18 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
bitfld.long 0x18 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 23. " USBRST ,USB reset" "No effect,Reset"
|
|
bitfld.long 0x18 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x18 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x18 20. " UART5RST ,UART 5 reset" "No effect,Reset"
|
|
bitfld.long 0x18 19. " UART4RST ,UART 4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x18 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x18 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x18 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x18 9. " LCDRST ,LCD reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x18 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x18 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x18 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x18 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x1C "RCC_AHBENR,AHB peripheral clock enable register"
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x1C 30. " FSMCEN ,FSMC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L162*")))
|
|
bitfld.long 0x1C 27. " AESEN ,AES clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x1C 25. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 24. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L1??QD")||cpuis("STM32L1??QC")||cpuis("STM32L1??ZC")||cpuis("STM32L1??ZD"))
|
|
bitfld.long 0x1C 7. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 5. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((!cpuis("STM32L15?C?"))&&(!cpuis("STM32L1??R?")))
|
|
bitfld.long 0x1C 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32L15?C?"))
|
|
bitfld.long 0x1C 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_APB2ENR,APB2 peripheral clock enable register"
|
|
bitfld.long 0x20 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x20 11. " SDIOEN ,SDIO clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " TIM11EN ,TIM11 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " TIM10EN ,TIM10 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 2. " TIM9EN ,TIM9 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " SYSCFGEN ,System configuration controller clock enable" "Disabled,Enabled"
|
|
line.long 0x24 "RCC_APB1ENR,APB1 peripheral clock enable register"
|
|
bitfld.long 0x24 31. " COMPEN ,COMP interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 23. " USBEN ,USB clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x24 20. " UART5EN ,UART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 19. " UART4EN ,UART 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x24 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32L1?2*")))
|
|
bitfld.long 0x24 9. " LCDEN ,LCD clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x24 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x28 "RCC_AHBLPENR,AHB peripheral clock enable in low power mode register"
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x28 30. " FSMCLPEN ,FSMC clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L162*")))
|
|
bitfld.long 0x28 27. " AESLPEN ,AES clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x28 25. " DMA2LPEN ,DMA2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 24. " DMA1LPEN ,DMA1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 16. " SRAMLPEN ,SRAM clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 15. " FLITFLPEN ,FLITF clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 12. " CRCLPEN ,CRC clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L1??QD")||cpuis("STM32L1??QC")||cpuis("STM32L1??ZC")||cpuis("STM32L1??ZD"))
|
|
bitfld.long 0x28 7. " GPIOGLPEN ,IO port G clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " GPIOFLPEN ,IO port F clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 5. " GPIOHLPEN ,IO port H clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((!cpuis("STM32L15?C?"))&&(!cpuis("STM32L1??R?")))
|
|
bitfld.long 0x28 4. " GPIOEEN ,IO port E clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32L15?C?"))
|
|
bitfld.long 0x28 3. " GPIODEN ,IO port D clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x028 2. " GPIOCLPEN ,IO port C clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x028 1. " GPIOBLPEN ,IO port B clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x028 0. " GPIOALPEN ,IO port A clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x2C "RCC_APB2LPENR,APB2 peripheral clock enable in low power mode register"
|
|
bitfld.long 0x2C 14. " USART1LPEN ,USART1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 12. " SPI1LPEN ,SPI 1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x2C 11. " SDIOLPEN ,SDIO clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 9. " ADC1LPEN ,ADC1 interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 4. " TIM11LPEN ,TIM11 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 3. " TIM10LPEN ,TIM10 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " TIM9LPEN ,TIM9 timer clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " SYSCFGLPEN ,System configuration controller clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x30 "RCC_APB1LPENR,APB1 peripheral clock enable in low power mode register"
|
|
bitfld.long 0x30 31. " COMPLPEN ,COMP interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " DACLPEN ,DAC interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 28. " PWRLPEN ,Power interface clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 23. " USBLPEN ,USB clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 22. " I2C2LPEN ,I2C 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 21. " I2C1LPEN ,I2C 1 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x30 20. " UART5LPEN ,USART 5 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 19. " UART4LPEN ,USART 4 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 18. " USART3LPEN ,USART 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 17. " USART2LPEN ,USART 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x30 15. " SPI3LPEN ,SPI 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 14. " SPI2LPEN ,SPI 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 11. " WWDGLPEN ,Window watchdog clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x30 9. " LCDLPEN ,LCD clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 5. " TIM7LPEN ,Timer 7 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 4. " TIM6LPEN ,Timer 6 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x30 3. " TIM4LPEN ,Timer 5 clock enable during Sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 2. " TIM4LPEN ,Timer 4 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 1. " TIM3LPEN ,Timer 3 clock enable during Sleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " TIM2LPEN ,Timer 2 clock enable during Sleep mode" "Disabled,Enabled"
|
|
line.long 0x34 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x34 31. " LPWRRSTF ,Low-power management reset" "Not occurred,Occurred"
|
|
bitfld.long 0x34 30. " WWDGRSTF ,Window watchdog reset" "Not occurred,Occurred"
|
|
bitfld.long 0x34 29. " IWDGRSTF ,Independent watchdog reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x34 28. " SFTRSTF ,Software reset" "Not occurred,Occurred"
|
|
bitfld.long 0x34 27. " PORRSTF ,POR/PDR reset" "Not occurred,Occurred"
|
|
bitfld.long 0x34 26. " PINRSTF ,PIN reset" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x34 25. " OBLRSTF , Options bytes loading reset" "Not occurred,Occurred"
|
|
bitfld.long 0x34 24. " RMVF ,Remove reset flag" "No effect,Cleared"
|
|
bitfld.long 0x34 23. " RTCRST ,RTC software reset" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x34 22. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 16.--17. " RTCSEL ,RTC and LCD clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x34 22. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 16.--17. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x34 12. " LSECSSD ,CSS on LSE failure Detection" "Not detected,Detected"
|
|
bitfld.long 0x34 11. " LSECSSON ,CSS on LSE enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x34 10. " LSEBYP ,External low-speed oscillator bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x34 9. " LSERDY ,External low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x34 8. " LSEON ,External low-speed oscillator enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x34 1. " LSIRDY ,Internal low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x34 0. " LSION ,Internal low-speed oscillator enable" "Off,On"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree.open "GPIO (General-Purpose I/Os)"
|
|
tree "GPIO A"
|
|
base ad:0x40020000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MICO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTMS-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCL-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MICO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,USB_DP,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,USB_DM,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MISO,,USART1_RTS,,,USB_DP,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,USB_DM,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCL-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" ",,TIM3_CH2,TIM11_CH1,,SPI1_MOSI,,,,,,SEG4,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" ",,TIM3_CH1,TIM10_CH1,,SPI1_MISO,,,,,,SEG3,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" ",TIM2_CH1_ETR,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI1_NSS,,USART2_CK,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",TIM2_CH4,,TIM9_CH2,,,,USART2_RX,,,,SEG2,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",TIM2_CH3,,TIM9_CH1,,,,USART2_TX,,,,SEG1,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",TIM2_CH2,,,,,,USART2_RTS,,,,SEG0,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",TIM2_CH1_ETR,,,,,,USART2_CTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,,,,SPI1_NSS,,,,,,SEG17,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" ",,,,,SPI1_MOSI,,USART1_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" ",,,,,SPI1_MISO,,USART1_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" ",,,,,,,USART1_RX,,,,COM2,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",,,,,,,USART1_TX,,,,COM1,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,,,,,,,USART1_CK,,,,COM0,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port A Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port A Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port A Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port A Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x40020400
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM19_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,USART1_RX,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI/I2S2_SD,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,,,,,,SEG9,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,,,,,,SEG8,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "JTDO,TIM2_CH2,,,,SPI1_SCK,,,,,,SEG7,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,TIM3_CH4,,,,,,,,,SEG6,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" ",,TIM3_CH3,,,,,,,,,SEG5,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,,TIM11_CH1,,SPI2_MOSI,,,,,,SEG15,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,,TIM9_CH2,,SPI2_MISO,,USART3_RTS,,,,SEG14,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,,TIM9_CH1,,SPI2_SCK,,USART3_CTS,,,,SEG13,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",,,TIM10_CH1,I2C2_SMBA,SPI2_NSS,,USART3_CK,,,,SEG12,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,SEG11,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",TIM2_CH3,,,I2C2_SCL,,,USART3_TX,,,,SEG10,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,,,,,,,COM3,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,SEG16,,,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port B Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port B Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port B Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port B Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port B Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port B Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port B Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO C"
|
|
base ad:0x40020800
|
|
sif cpuis("STM32L100C6-A")
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port C output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
sif cpuis("STM32L15?CC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
sif cpuis("STM32L15?C??A")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,I2S3_MCK,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_TX,UART4_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG29/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_SCK/I2S3_CK,USART_TX,,,,COM6/SEG29/42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART_RX,,,,COM5/SEG29/41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART_TX,,,,COM4/SEG28/40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
sif cpuis("STM32L100C6-A")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
elif cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port C output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
sif cpuis("STM32L15?CC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
sif cpuis("STM32L15?C??A")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,I2S3_MCK,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_TX,UART4_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG29/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_SCK/I2S3_CK,USART_TX,,,,COM6/SEG29/42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART_RX,,,,COM5/SEG29/41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART_TX,,,,COM4/SEG28/40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,I2S3_MCK,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,I2S2_MCK,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,SPI3_MISO,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
sif cpuis("STM32L100C6-A")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
elif cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" ",,TIM3_CH2,,,,,,,,,SEG25,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" ",,TIM3_CH1,,,,,,,,,SEG24,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",,,,,,,,,,,SEG23,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,SEG22,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,SEG21,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" ",,,,,,,,,,,SEG20,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,SEG19,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" ",,,,,,,,,,,SEG18,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" ",,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" ",,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" ",,,,,,,USART3_CK,,,,COM6/SEG30/SEG42,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" ",,,,,,,USART3_RX,,,,COM5/SEG29/SEG41,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" ",,,,,,,USART3_TX,,,,COM4/SEG28/SEG40,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" ",,TIM3_CH4,,,,,,,,,SEG27,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" ",,TIM3_CH3,,,,,,,,,SEG26,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port C Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port C Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port C Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port C Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port C Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port C Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif !cpuis("STM32L100C6-A")
|
|
tree "GPIO D"
|
|
base ad:0x40020C00
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
sif cpuis("STM32L15?UC")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
sif cpuis("STM32L162RC")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
sif cpuis("STM32L15?R??A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L15?V??A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,TIM9_CH2,,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
sif cpuis("STM32L15?RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
sif cpuis("STM32L15?RC-A")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L15?VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
sif cpuis("STM32L162RC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
sif cpuis("STM32L162RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,,USART2_CK,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,,USART2_RX,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,,USART2_TX,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,SPI2_MISO,,USART2_CTS,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,,USART3_RTS,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,,USART3_CTS,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,,USART3_CK,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,,USART3_RX,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,,USART3_TX,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
sif cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D Reset bit 2" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
sif cpuis("STM32L15?UC")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
sif cpuis("STM32L162RC")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
sif cpuis("STM32L15?R??A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L15?V??A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,TIM9_CH2,,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
sif cpuis("STM32L15?RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
sif cpuis("STM32L15?RC-A")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L15?VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
sif cpuis("STM32L162RC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,USART2_CK,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,USART2_RX,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,USART2_TX,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,SPI2_MISO,,USART2_CTS,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,USART3_RTS,,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,USART3_CTS,,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,USART3_CK,,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,USART3_RX,,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,USART3_TX,,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
sif cpuis("STM32L162RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
elif cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" ",,,TIM9_CH2,,,,,USART2_CK,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" ",,,,,,,,USART2_RX,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" ",,,,,,,,USART2_TX,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,SPI2_MISO,,USART2_CTS,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM_ETR,,,,,,UART5_RX,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,SPI2_SCK/I2S2_CK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",,,TIM9_CH1,,SPI2_NSS/I2S2_WS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" ",,TIM4_CH4,,,,,,,,,SEG35,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",,TIM4_CH3,,,,,,,,,SEG34,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",,TIM4_CH2,,,,,,,,,SEG33,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" ",,TIM4_CH1,,,,,,USART3_RTS,,,SEG32,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" ",,,,,,,,USART3_CTS,,,SEG31,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" ",,,,,,,,USART3_CK,,,SEG30,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" ",,,,,,,,USART3_RX,,,SEG29,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" ",,,,,,,,USART3_TX,,,SEG28,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
sif cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" ",,TIM3_ETR,,,,,,,,,COM7/SEG31/SEG43,,,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port D Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port D Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port D Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port D Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port D Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port D Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port D Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port D Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port D Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port D Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port D Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port D Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port D Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port D Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port D Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port D Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")&&!cpuis("STM32L100C6-A")&&!cpuis("STM32L100R8-A")&&!cpuis("STM32L100RB-A")&&!cpuis("STM32L100RC")
|
|
tree "GPIO E"
|
|
base ad:0x40021000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOE_ODR,GPIO port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port E output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,TIM5_ETR,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
sif cpuis("STM32L15?V??A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
sif cpuis("STM32L15?QE")||cpuis("STM32L15?VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
sif cpuis("STM32L15?VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
sif cpuis("STM32L162VC-A")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
sif cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,,,TIM9_CH2,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,,,TIM9_CH1,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "TRACED1,,TIM3_CH2,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TRACED0,,TIM3_CH1,,,,,,,,,SEG39,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,,TIM3_ETR,,,,,,,,,SEG38,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,TIM11_CH1,,,,,,,,SEG37,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",,TIM4_ETR,TIM10_CH1,,,,,,,,SEG36,,,TIMx_IC1,EVENTOUT"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",,,,,SPI1_MOSI,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",,,,,SPI1_MISO,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",,,,,SPI1_SCK,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",TIM2_CH4,,,,SPI1_NSS,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",TIM2_CH3,,,,,,,,,,,,,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",TIM2_CH2,,,,,,,,,,,,,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",TIM2_CH1_ETR,,,,,,,,,,,,,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",,,,,,,,,,,,,,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port E Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port E Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port E Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port E Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port E Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port E Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port E Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port E Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port E Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port E Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port E Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port E Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port E Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port E Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port E Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO F"
|
|
base ad:0x40021800
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port F output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
sif cpuis("STM32L15?QE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" ",,TIM5_CH2,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" ",,TIM5_ETR,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F bit 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port F bit 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port F bit 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port F bit 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port F bit 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port F bit 11" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" ",,TIM5_CH4,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port F bit 8" ",,TIM5_CH3,,,,,,,,,,,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
sif cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" ",,TIM5_CH2,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" ",,TIM5_ETR,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F bit 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port F bit 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port F bit 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port F bit 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port F bit 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port F bit 11" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" ",,TIM5_CH4,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port F bit 8" ",,TIM5_CH3,,,,,,,,,,,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port F Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port F Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port F Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port F Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port F Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port F Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port F Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port F Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port F Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port F Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port F Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO G"
|
|
base ad:0x40021C00
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOG_MODER,GPIO port G mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOG_OTYPER,GPIO port G mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOG_OSPEEDR,GPIO port G output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port G output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOG_PUPDR,GPIO port G pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port G configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOG_IDR,GPIO port G input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port G input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOG_ODR,GPIO port G output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port G output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOG_LCKR,GPIO port G configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
sif cpuis("STM32L15?QE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port G bit 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port G bit 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port G bit 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port G bit 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port G bit 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port G bit 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port G bit 10" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port G bit 9" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
sif cpuis("STM32L162ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port G bit 7" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port G bit 6" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port G bit 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port G bit 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port G bit 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port G bit 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port G bit 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port G bit 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port G bit 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port G bit 11" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port G bit 10" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port G bit 9" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port G bit 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOG_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port G Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port G Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port G Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port G Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port G Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port G Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port G Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port G Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port G Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port G Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port G Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port G Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port G Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port G Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port G Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port G Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO H"
|
|
base ad:0x40021400
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOH_MODER,GPIO port H mode register"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOH_OTYPER,GPIO port H mode register"
|
|
bitfld.long 0x04 1. " OT1 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOH_OSPEEDR,GPIO port H output speed register"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOH_PUPDR,GPIO port H pull-up/pull-down register"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOH_IDR,GPIO port H input data register"
|
|
bitfld.long 0x00 1. " IDR1 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port H input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOH_ODR,GPIO port H output data register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port H output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOH_LCKR,GPIO port H configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port H lock bit" "Not locked,Locked"
|
|
sif cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOH_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Port H Reset bit 1" "No action,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port H Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOH_MODER,GPIO port H mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOH_OTYPER,GPIO port H mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOH_OSPEEDR,GPIO port H output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port H output speed register" "Very low,Low,Medium,High"
|
|
line.long 0x0C "GPIOH_PUPDR,GPIO port H pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port H configuration bits" "Disabled,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOH_IDR,GPIO port H input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port H input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port H input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port H input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port H input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port H input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port H input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOH_ODR,GPIO port H output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port H output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port H output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port H output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port H output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port H output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port H output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOH_LCKR,GPIO port H configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK15 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port H lock bit" "Not locked,Locked"
|
|
textline " "
|
|
width 15.
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151UC")||cpuis("STM32L152CC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VC STM32L162RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VC")||cpuis("STM32L162RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151x6/8/B-A STM32L152x6/8/B-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151xE STM32L152xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151?E")||cpuis("STM32L152?E")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L151VD-X STM32L152VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162VD-X
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162VD-X")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L15xQC STM3215xRC-A STM32L15xVC-A STM32L15xZC
|
|
; --------------------------------------------------------------------------------
|
|
sif (cpuis("STM32L151RC-A")||cpuis("STM32L151VC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A"))
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162QC STM32L162VC-A STM32L162ZC STM32L162RC-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RC-A")||cpuis("STM32L162VC-A")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L162xE
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100RC
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100RC")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6 STM32L100R8 STM32L100RB
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")
|
|
endif
|
|
; --------------------------------------------------------------------------------
|
|
; STM32L100C6-A STM32L100R8-A STM32L100RB-A
|
|
; --------------------------------------------------------------------------------
|
|
sif cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
endif
|
|
width 0x0B
|
|
textline " "
|
|
width 15.
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOH_BRR,GPIO bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port H Reset bit 15" "No action,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port H Reset bit 14" "No action,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port H Reset bit 13" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port H Reset bit 12" "No action,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port H Reset bit 11" "No action,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port H Reset bit 10" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port H Reset bit 9" "No action,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port H Reset bit 8" "No action,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port H Reset bit 7" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port H Reset bit 6" "No action,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port H Reset bit 5" "No action,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port H Reset bit 4" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port H Reset bit 3" "No action,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port H Reset bit 2" "No action,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port H Reset bit 1" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port H Reset bit 0" "No action,Reset"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "GPIO (General-Purpose I/Os)"
|
|
tree "GPIO A"
|
|
base ad:0x40020000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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textline " "
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bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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textline " "
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bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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textline " "
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bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
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line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
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bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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textline " "
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bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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textline " "
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bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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textline " "
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bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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textline " "
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bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
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textline " "
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bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
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rgroup.long 0x10++0x3
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line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
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bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
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bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
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bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
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textline " "
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bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
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bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
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bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
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|
textline " "
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bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
textline " "
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bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
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bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
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bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
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bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
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bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
textline " "
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bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
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group.long 0x14++0x3
|
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line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
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setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
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setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
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setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
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textline " "
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setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
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setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
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setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
textline " "
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setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
textline " "
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setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
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setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
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bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,TIM3_CH2,TIM11_CH1,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,SEG4,Reserved,Reserved,COMP1_INP/TIMx_IC4_1/G2IO2,EVENTOUT"
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bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,TIM3_CH1,TIM10_CH1,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,SEG3,Reserved,Reserved,COMP1_INP/TIMx_IC3_1/G2IO1,EVENTOUT"
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bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC2_1,EVENTOUT"
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textline " "
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bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_NSS,SPI3_NSSI2S3_WS,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_1,EVENTOUT"
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bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,TIM2_CH4,TIM5_CH4,TIM9_CH2,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,SEG2,Reserved,Reserved,COMP1_INP/TIMx_IC4_0/G1IO4,EVENTOUT"
|
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bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,TIM2_CH3,TIM5_CH3,TIM9_CH1,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,SEG1,Reserved,Reserved,COMP1_INP/TIMx_IC3_0/G1IO3,EVENTOUT"
|
|
textline " "
|
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bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,TIM2_CH2,TIM5_CH2,Reserved,Reserved,Reserved,Reserved,USART2_RTS,Reserved,Reserved,Reserved,SEG0,Reserved,Reserved,COMP1_INP_TIMx_IC2_0/G1IO2,EVENTOUT"
|
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bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "WKUP1/TAMPER2,TIM2_CH1_ETR,TIM5_CH1,Reserved,Reserved,Reserved,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_0/G1IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,TIM3_CH2,TIM11_CH1,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,SEG4,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
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bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,TIM3_CH1,TIM10_CH1,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,SEG3,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
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bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,TIM2_CH4,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,SEG2,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,TIM2_CH3,Reserved,TIM9_CH1,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,SEG1,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
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textline " "
|
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bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,TIM2_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_TS,Reserved,Reserved,Reserved,SEG0,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "WKUP1,TIM2_CH1_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?C")||cpuis("STM32L151?D"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,TIM3_CH2,TIM11_CH1,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC4_1/G2IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,TIM3_CH1,TIM10_CH1,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC3_1/G2IO1,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC2_1,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_NSS,SPI3_NSSI2S3_WS,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,TIM2_CH4,TIM5_CH4,TIM9_CH2,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC4_0/G1IO4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,TIM2_CH3,TIM5_CH3,TIM9_CH1,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC3_0/G1IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,TIM2_CH2,TIM5_CH2,Reserved,Reserved,Reserved,Reserved,USART2_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP_TIMx_IC2_0/G1IO2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "WKUP1/TAMPER2,TIM2_CH1_ETR,TIM5_CH1,Reserved,Reserved,Reserved,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_0/G1IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,TIM3_CH2,TIM11_CH1,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,TIM3_CH1,TIM10_CH1,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,TIM2_CH4,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,TIM2_CH3,Reserved,TIM9_CH1,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,TIM2_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_TS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "WKUP1,TIM2_CH1_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
line.long 0x08 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_NSS,SPI3_NSSI2S3_WS,Reserved,Reserved,Reserved,Reserved,SEG17,Reserved,Reserved,TIMx_IC4_3/G5IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_3/G5IO2,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_3/G5IO1,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,USART1_RTS,Reserved,Reserved,USBDP,Reserved,Reserved,Reserved,TIMx_IC1_3,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,USART1_CTS,Reserved,Reserved,USBDM,Reserved,Reserved,Reserved,TIMx_IC4_2/G4IO4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,COM2,Reserved,Reserved,TIMx_IC3_2/G4IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,COM1,Reserved,Reserved,TIMx_IC2_2/G4IO2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_CK,Reserved,Reserved,Reserved,COM0,Reserved,Reserved,TIMx_IC1_2/G4IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,SEG17,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDAT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,USART1_RTS,Reserved,Reserved,DP,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,USART1_CTS,Reserved,Reserved,DM,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,COM2,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,COM1,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_CK,Reserved,Reserved,Reserved,COM0,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?C")||cpuis("STM32L151?D"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_NSS,SPI3_NSSI2S3_WS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_3/G5IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_3/G5IO2,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDIO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_3/G5IO1,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,USART1_RTS,Reserved,Reserved,USBDP,Reserved,Reserved,Reserved,TIMx_IC1_3,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,USART1_CTS,Reserved,Reserved,USBDM,Reserved,Reserved,Reserved,TIMx_IC4_2/G4IO4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_2/G4IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_2/G4IO2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_2/G4IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "JTDI,TIM2_CH1_ETR,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "JTCK-SWCLK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "JTMS-SWDAT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,USART1_RTS,Reserved,Reserved,DP,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,USART1_CTS,Reserved,Reserved,DM,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART1_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x40020400
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOB_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
sif (cpuis("STM32L152?C")||cpuis("STM32L1?2RD"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO4,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,LBAR,Reserved,G6IO4,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "Reserved,Reserved,TIM4_CH1,Reserved,I2C1_SCL,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "Reserved,Reserved,TIM3_CH2,Reserved,I2C1_SMBA,SPI1_MOSI,SPI3_MOSII2S3_SD,Reserved,Reserved,Reserved,Reserved,SEG9,Reserved,Reserved,G6IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "JTRST,Reserved,TIM3_CH1,Reserved,Reserved,SPI1_MISO,SPI3_MISO,Reserved,Reserved,Reserved,Reserved,SEG8,Reserved,Reserved,G6IO1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "JTDO,TIM2_CH2,Reserved,Reserved,Reserved,SPI1_SCK,SPI3_SCKI2S3_CK,Reserved,Reserved,Reserved,Reserved,SEG7,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G3IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG6,Reserved,Reserved,COMP1_INP/G3IO2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG5,Reserved,Reserved,COMP1_INP/G3IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "Reserved,Reserved,TIM4_CH1,Reserved,I2C1_SCL,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "Reserved,Reserved,TIM3_CH2,Reserved,I2C1_SMB Al,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,SEG9,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "JTRST,Reserved,TIM3_CH1,Reserved,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,SEG8,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "JTDO,TIM2_CH2,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,SEG7,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG6,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG5,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?C")||cpuis("STM32L151?D"))
|
|
sif (cpuis("STM32L151?C")||cpuis("STM32L151RD"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO4,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,LBAR,Reserved,G6IO4,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "Reserved,Reserved,TIM4_CH1,Reserved,I2C1_SCL,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "Reserved,Reserved,TIM3_CH2,Reserved,I2C1_SMBA,SPI1_MOSI,SPI3_MOSII2S3_SD,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "JTRST,Reserved,TIM3_CH1,Reserved,Reserved,SPI1_MISO,SPI3_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G6IO1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "JTDO,TIM2_CH2,Reserved,Reserved,Reserved,SPI1_SCK,SPI3_SCKI2S3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G3IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G3IO2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G3IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "Reserved,Reserved,TIM4_CH2,Reserved,I2C1_SDA,Reserved,Reserved,USART1_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "Reserved,Reserved,TIM4_CH1,Reserved,I2C1_SCL,Reserved,Reserved,USART1_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "Reserved,Reserved,TIM3_CH2,Reserved,I2C1_SMB Al,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "JTRST,Reserved,TIM3_CH1,Reserved,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "JTDO,TIM2_CH2,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" "BOOT1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
endif
|
|
endif
|
|
line.long 0x08 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "RTC 50/60 Hz,Reserved,Reserved,TIM11_CH1,Reserved,SPI2_MOSII2S2_SD,Reserved,Reserved,Reserved,Reserved,Reserved,SEG15,Reserved,Reserved,COMP1_INP/G7IO4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,SPI2_MISO,Reserved,USART3_RTS,Reserved,Reserved,Reserved,SEG14,Reserved,Reserved,COMP1_INP/G7IO3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_SCKI2S2_CK,Reserved,USART3_CTS,Reserved,Reserved,Reserved,SEG13,Reserved,Reserved,COMP1_INP/G7IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "Reserved,Reserved,Reserved,TIM10_CH1,I2C2_SMBA,SPI2_NSSI2S2_WS,Reserved,USART3_CK,Reserved,Reserved,Reserved,SEG12,Reserved,Reserved,COMP1_INP/G7IO1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port B bit 11 " "Reserved,TIM2_CH4,Reserved,Reserved,I2C2_SDA,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,SEG11,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port B bit 10 " "Reserved,TIM2_CH3,Reserved,Reserved,I2C2_SCL,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,SEG10,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM3,SDIO_D5,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG16,SDIO_D4,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM3,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG16,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "RTC 50/60 Hz,Reserved,Reserved,TIM11_CH1,Reserved,SPI2_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,SEG15,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,SPI2_MISO,Reserved,USART3_RTS,Reserved,Reserved,Reserved,SEG14,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_SCK,Reserved,USART3_CTS,Reserved,Reserved,Reserved,SEG13,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "Reserved,Reserved,Reserved,TIM10_CH1,I2C2_SMB Al,SPI2_NSS,Reserved,USART3_CK,Reserved,Reserved,Reserved,SEG12,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port B bit 11 " "Reserved,TIM2_CH4,Reserved,Reserved,I2C2_SDA,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,SEG11,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port B bit 10 " "Reserved,TIM2_CH3,Reserved,Reserved,I2C2_SCL,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,SEG10,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM3,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG16,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?C")||cpuis("STM32L151?D"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "RTC 50/60 Hz,Reserved,Reserved,TIM11_CH1,Reserved,SPI2_MOSII2S2_SD,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G7IO4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,SPI2_MISO,Reserved,USART3_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G7IO3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_SCKI2S2_CK,Reserved,USART3_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G7IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "Reserved,Reserved,Reserved,TIM10_CH1,I2C2_SMBA,SPI2_NSSI2S2_WS,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G7IO1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port B bit 11 " "Reserved,TIM2_CH4,Reserved,Reserved,I2C2_SDA,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port B bit 10 " "Reserved,TIM2_CH3,Reserved,Reserved,I2C2_SCL,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D"))
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_D5,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_D4,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "RTC 50/60 Hz,Reserved,Reserved,TIM11_CH1,Reserved,SPI2_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,SPI2_MISO,Reserved,USART3_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_SCK,Reserved,USART3_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "Reserved,Reserved,Reserved,TIM10_CH1,I2C2_SMB Al,SPI2_NSS,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port B bit 11 " "Reserved,TIM2_CH4,Reserved,Reserved,I2C2_SDA,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port B bit 10 " "Reserved,TIM2_CH3,Reserved,Reserved,I2C2_SCL,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "Reserved,Reserved,TIM4_CH4,TIM11_CH1,I2C1_SDA,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "Reserved,Reserved,TIM4_CH3,TIM10_CH1,I2C1_SCL,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO C"
|
|
base ad:0x40020800
|
|
sif (cpuis("STM32L15?C?"))
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port C output data" "Low,High"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" "OSC32_OUT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" "OSC32_IN,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" "RTC_AF1/WKUP2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
width 0x0B
|
|
else
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port C output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port C lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOC_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,I2S3_MCK,Reserved,Reserved,Reserved,Reserved,SEG25,SDIO7,Reserved,TIMx_IC4_5/G10IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,I2S2_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,SEG24,SDIO_D6,Reserved,TIMx_IC3_5/G10IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,I2S3_MCK,Reserved,Reserved,Reserved,Reserved,SEG25,Reserved,Reserved,TIMx_IC4_5/G10IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,I2S2_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,SEG24,Reserved,Reserved,TIMx_IC3_5/G10IO1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG23,Reserved,Reserved,TIMx_IC2_5/G9IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG22,Reserved,Reserved,COMP1_INP/TIMx_IC1_5/G9IO1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG21,Reserved,Reserved,COMP1_INP/TIMx_IC4_4/G8IO4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG20,Reserved,Reserved,COMP1_INP/TIMx_IC3_4/G8IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG19,Reserved,Reserved,COMP1_INP/TIMx_IC2_4/G8IO2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG18,Reserved,Reserved,COMP1_INP/TIMx_IC1_4/G8IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG25,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG24,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG23,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG22,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG21,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG20,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG19,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG18,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L151?C"))
|
|
sif (cpuis("STM32L151?D"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,I2S3_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO7,Reserved,TIMx_IC4_5/G10IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,I2S2_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_D6,Reserved,TIMx_IC3_5/G10IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,I2S3_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_5/G10IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,I2S2_MCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_5/G10IO1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_5/G9IO2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_5/G9IO1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC4_4/G8IO4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC3_4/G8IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC2_4/G8IO2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_4/G8IO1,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "Reserved,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "Reserved,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
line.long 0x08 "GPIOC_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" "OSC32_OUT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_7,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" "OSC32_IN,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_7,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" "WKUP2/TAMPER1/TIMESTAMP/ALARM_OUT/512HZ,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_7,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MOSII2S3_SD,USART3_CK,UART5_TX,Reserved,Reserved,COM6/SEG30/SEG42,SDIO_CK,Reserved,TIMx_IC1_7,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MISO,USART3_RX,UART4_RX,Reserved,Reserved,COM5/SEG29/SEG41,SDIO_D3,Reserved,TIMx_IC4_6,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_SCKI2S3_CK,USART3_TX,UART4_TX,Reserved,Reserved,COM4/SEG28/SEG40,SDIO_D2,Reserved,TIMx_IC3_6/G5IO4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG27,SDIO_D1,Reserved,TIMx_IC2_6/G10IO4,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG26,SDIO_D0,Reserved,TIMx_IC1_6/G10IO3,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MOSII2S3_SD,USART3_CK,Reserved,Reserved,Reserved,COM6/SEG30/SEG42,Reserved,Reserved,TIMx_IC1_7,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MISO,USART3_RX,Reserved,Reserved,Reserved,COM5/SEG29/SEG41,Reserved,Reserved,TIMx_IC4_6,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_SCKI2S3_CK,USART3_TX,Reserved,Reserved,Reserved,COM4/SEG28/SEG40,Reserved,Reserved,TIMx_IC3_6/G5IO4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG27,Reserved,Reserved,TIMx_IC2_6/G10IO4,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG26,Reserved,Reserved,TIMx_IC1_6/G10IO3,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" "OSC32_OUT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" "OSC32_IN,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" "RTC_AF1/WKUP2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,COM6/SEG30/SEG42,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,COM5/SEG29/SEG41,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,COM4/SEG28/SEG40,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG27,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG26,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L151?C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" "OSC32_OUT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_7,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" "OSC32_IN,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_7,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" "WKUP2/TAMPER1/TIMESTAMP/ALARM_OUT/512HZ,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_7,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L151?D"))
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MOSII2S3_SD,USART3_CK,UART5_TX,Reserved,Reserved,Reserved,SDIO_CK,Reserved,TIMx_IC1_7,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MISO,USART3_RX,UART4_RX,Reserved,Reserved,Reserved,SDIO_D3,Reserved,TIMx_IC4_6,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_SCKI2S3_CK,USART3_TX,UART4_TX,Reserved,Reserved,Reserved,SDIO_D2,Reserved,TIMx_IC3_6/G5IO4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_D1,Reserved,TIMx_IC2_6/G10IO4,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_D0,Reserved,TIMx_IC1_6/G10IO3,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MOSII2S3_SD,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_7,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_MISO,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_6,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SPI3_SCKI2S3_CK,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_6/G5IO4,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,TIM3_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_6/G10IO4,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_6/G10IO3,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port C bit 15" "OSC32_OUT,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port C bit 14" "OSC32_IN,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port C bit 13" "RTC_AF1/WKUP2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port C bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port C bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "Reserved,Reserved,TIM3_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("STM32L15?C?"))
|
|
tree "GPIO D"
|
|
base ad:0x40020C00
|
|
width 15.
|
|
sif (cpuis("STM32L1*R?"))
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOD_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1?2R?"))
|
|
sif (cpuis("STM32L1?2RD")||cpuis("STM32L152RC"))
|
|
sif (cpuis("STM32L1?2RD"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,UART5_RX,Reserved,Reserved,COM7/SEG31/SEG43,SDIO_CMD,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM7/SEG31/SEG43,Reserved,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM7/SEG31/SEG43,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151RD")||cpuis("STM32L151RC"))
|
|
sif (cpuis("STM32L151RD"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,UART5_RX,Reserved,Reserved,Reserved,SDIO_CMD,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOD_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1*D")||cpuis("STM32L1*C"))
|
|
sif (cpuis("STM32L1*C"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_9,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_9,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_9,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MOSI,Reserved,USART2_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_9,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MISO,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_8,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM7/SEG31/SEG43,Reserved,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_8,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_8,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,USART2_CK,Reserved,Reserved,Reserved,Reserved,EBAR0,Reserved,TIMx_IC4_9,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,Reserved,WAITN,Reserved,TIMx_IC3_9,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,Reserved,WEN,Reserved,TIMx_IC2_9,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MOSI,Reserved,USART2_RTS,Reserved,Reserved,Reserved,Reserved,OEN,Reserved,TIMx_IC1_9,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MISO,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,CLK,Reserved,TIMx_IC4_8,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM7/SEG31/SEG43,SDIO_CMD,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SDIO_CMD,Reserved,TIMx_IC3_8,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D3/DA3,Reserved,TIMx_IC2_8,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D2/DA2,Reserved,TIMx_IC1_8,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "Reserved,Reserved,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,USART2_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART2_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MOSI,Reserved,USART2_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_MISO,Reserved,USART2_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1?2*"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COM7/SEG31/SEG43,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "Reserved,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI2_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "Reserved,Reserved,Reserved,TIM9_CH1,Reserved,SPI2_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
line.long 0x08 "GPIOD_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG35,D1/DA1,Reserved,TIMx_IC4_11,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG34,D0/DA0,Reserved,TIMx_IC3_11,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG33,A18,Reserved,TIMx_IC2_11,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,SEG32,A17,Reserved,TIMx_IC1_11,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,SEG31,A16,Reserved,TIMx_IC4_10,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,SEG30,D15/DA15,Reserved,TIMx_IC3_10,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,SEG29,D14/DA14,Reserved,TIMx_IC2_10,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,SEG28,D13/DA13,Reserved,TIMx_IC1_10,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG35,Reserved,Reserved,TIMx_IC4_11,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG34,Reserved,Reserved,TIMx_IC3_11,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG33,Reserved,Reserved,TIMx_IC2_11,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,SEG32,Reserved,Reserved,TIMx_IC1_11,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,SEG31,Reserved,Reserved,TIMx_IC4_10,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,SEG30,Reserved,Reserved,TIMx_IC3_10,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,SEG29,Reserved,Reserved,TIMx_IC2_10,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,SEG28,Reserved,Reserved,TIMx_IC1_10,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG35,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG34,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG33,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,SEG32,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,SEG31,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,SEG30,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,SEG29,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,SEG28,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif (cpuis("STM32L151?D")||cpuis("STM32L151?C"))
|
|
sif (cpuis("STM32L151?C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D1/DA1,Reserved,TIMx_IC4_11,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D0/DA0,Reserved,TIMx_IC3_11,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A18,Reserved,TIMx_IC2_11,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,Reserved,A17,Reserved,TIMx_IC1_11,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,Reserved,A16,Reserved,TIMx_IC4_10,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,D15/DA15,Reserved,TIMx_IC3_10,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,D14/DA14,Reserved,TIMx_IC2_10,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,D13/DA13,Reserved,TIMx_IC1_10,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_11,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_11,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_11,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_11,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_10,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_10,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_10,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_10,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "Reserved,Reserved,TIM4_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "Reserved,Reserved,TIM4_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "Reserved,Reserved,TIM4_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "Reserved,Reserved,TIM4_CH1,Reserved,Reserved,Reserved,Reserved,USART3_RTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port D bit 11 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CTS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port D bit 10 " "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_CK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_RX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,USART3_TX,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif ((!cpuis("STM32L15?C?"))&&(!cpuis("STM32L1??R?")))
|
|
tree "GPIO E"
|
|
base ad:0x40021000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOE_ODR,GPIO port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port E output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOE_AFRL,GPIO alternate function low register"
|
|
sif ((cpuis("STM32L1???C"))||(cpuis("STM32L1???D")))
|
|
sif (cpuis("STM32L1???D"))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D4/DA4,Reserved,COMP1_INP/TIMx_IC4_13,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC4_13,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3/WKUP3,Reserved,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_13,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1???D"))
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,Reserved,Reserved,TIM9_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A21,Reserved,TIMx_IC2_13,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TRACED1,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A20,Reserved,TIMx_IC1_13,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,Reserved,Reserved,TIM9_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_13,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TRACED1,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_13,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3/WKUP3,Reserved,Reserved,TIM9_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,Reserved,Reserved,TIM9_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TRACED1,Reserved,TIM3_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L1?2*"))
|
|
sif ((cpuis("STM32L152?C"))||(cpuis("STM32L1?2?D")))
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 39,A19,Reserved,TIMx_IC4_12,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 38,A23,Reserved,TIMx_IC3_12,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 37,BLN1,Reserved,TIMx_IC2_12,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG36,BLN0,Reserved,TIMx_IC1_12,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 39,Reserved,Reserved,TIMx_IC4_12,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 38,Reserved,Reserved,TIMx_IC3_12,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 37,Reserved,Reserved,TIMx_IC2_12,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG36,Reserved,Reserved,TIMx_IC1_12,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 39,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 38,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG 37,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SEG36,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
sif ((cpuis("STM32L151?C"))||(cpuis("STM32L151?D")))
|
|
sif (cpuis("STM32L1?1?D"))
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A19,Reserved,TIMx_IC4_12,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A23,Reserved,TIMx_IC3_12,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BLN1,Reserved,TIMx_IC2_12,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BLN0,Reserved,TIMx_IC1_12,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_12,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_12,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_12,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_12,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,Reserved,TIM3_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,Reserved,TIM3_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "Reserved,Reserved,Reserved,TIM11_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "Reserved,Reserved,TIM4_ETR,TIM10_CH1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
endif
|
|
line.long 0x08 "GPIOE_AFRH,GPIO alternate function high register"
|
|
sif ((cpuis("STM32L1???C"))||(cpuis("STM32L1???D")))
|
|
sif (cpuis("STM32L1???D"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D12/DA12,Reserved,TIMx_IC4_15,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D11/DA11,Reserved,TIMx_IC3_15,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D10/DA10,Reserved,TIMx_IC2_15,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "Reserved,TIM2_CH4,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D9/DA9,Reserved,TIMx_IC1_15,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port E bit 11 " "Reserved,TIM2_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D8/DA8,Reserved,TIMx_IC4_14,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port E bit 10 " "Reserved,TIM2_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D7/DA7,Reserved,COMP1_INP/TIMx_IC3_14,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "Reserved,TIM2_CH1_ ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D6/DA6,Reserved,COMP1_INP/TIMx_IC2_14,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,D5/DA5,Reserved,COMP1_INP/TIMx_IC1_14,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_15,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3_15,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2_15,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "Reserved,TIM2_CH4,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1_15,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port E bit 11 " "Reserved,TIM2_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4_14,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port E bit 10 " "Reserved,TIM2_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC3_14,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "Reserved,TIM2_CH1_ ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC2_14,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/TIMx_IC1_14,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MOSI,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_MISO,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,SPI1_SCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "Reserved,TIM2_CH4,Reserved,Reserved,Reserved,SPI1_NSS,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port E bit 11 " "Reserved,TIM2_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC4,EVENTOUT"
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port E bit 10 " "Reserved,TIM2_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "Reserved,TIM2_CH1_ ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC2,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TIMx_IC1,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32L1??QD")||cpuis("STM32L1??QC")||cpuis("STM32L1??ZC")||cpuis("STM32L1??ZD"))
|
|
tree "GPIO F"
|
|
base ad:0x40021800
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port F output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,TIM5_CH2,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G11IO2,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,TIM5_CH1_ETR,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G11IO1,EVENTOUT"
|
|
textline " "
|
|
sif (cpuis("STM32L1???C"))
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A5,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A4,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A3,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A2,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A1,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A0,Reserved,Reserved,EVENTOUT"
|
|
endif
|
|
line.long 0x08 "GPIOF_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32L1???C"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port F bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G2IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port F bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G9IO4,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port F bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G9IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port F bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G3IO5,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port F bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A9,Reserved,G2IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port F bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A8,Reserved,G9IO4,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port F bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A7,Reserved,G9IO3,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port F bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A6,Reserved,G3IO5,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port F bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G3IO4,EVENTOUT"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G11IO5,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "Reserved,Reserved,TIM5_CH4,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G11IO4,EVENTOUT"
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port F bit 8" "Reserved,Reserved,TIM5_CH3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,COMP1_INP/G11IO3,EVENTOUT"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO G"
|
|
base ad:0x40021C00
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOG_MODER,GPIO port G mode register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOG_OTYPER,GPIO port G mode register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x04 15. " OT15 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " OT14 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x04 11. " OT11 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 10. " OT10 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x04 8. " OT8 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " OT5 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOG_OSPEEDR,GPIO port G output speed register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port G output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOG_PUPDR,GPIO port G pull-up/pull-down register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOG_IDR,GPIO port G input data register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 15. " IDR15 ,Port G input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port G input data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 11. " IDR11 ,Port G input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " IDR10 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port G input data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 8. " IDR8 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port G input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " IDR5 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port G input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOG_ODR,GPIO port G output data register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port G output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port G output data" "Low,High"
|
|
group.long 0x1C++0xB
|
|
line.long 0x00 "GPIOG_LCKR,GPIO port G configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 15. " LCK15 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 11. " LCK11 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " LCK10 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x00 8. " LCK8 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " LCK5 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port G lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port G lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port G lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L1???C"))
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G7IO7,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G7IO6,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G7IO5,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G2IO5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,G2IO4,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A15,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A14,Reserved,G7IO7,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A13,Reserved,G7IO6,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A12,Reserved,G7IO5,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A11,Reserved,G2IO5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A10,Reserved,G2IO4,EVENTOUT"
|
|
endif
|
|
line.long 0x08 "GPIOG_AFRH,GPIO alternate function high register"
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port G bit 15" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L1???C"))
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port G bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port G bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port G bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port G bit 14" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A25,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port G bit 13" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A24,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port G bit 12" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EBAR3,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port G bit 11" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L1???C"))
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port G bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port G bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port G bit 10" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EBAR2,Reserved,Reserved,EVENTOUT"
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port G bit 9" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EBAR1,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32L1??ZD"))||(cpuis("STM32L1??ZC")))
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port G bit 8" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO H"
|
|
base ad:0x40021400
|
|
width 15.
|
|
sif ((cpuis("STM32L1*Q?"))||(cpuis("STM32L1*Z?"))||(cpuis("STM32L1*V?")))
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOH_MODER,GPIO port H mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOH_OTYPER,GPIO port H mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOH_OSPEEDR,GPIO port H output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port H output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port H output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port H output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOH_PUPDR,GPIO port H pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOH_IDR,GPIO port H input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port H input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOH_ODR,GPIO port H output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port H output data" "Low,High"
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "GPIOH_LCKR,GPIO port H configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port H lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOH_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32L1?2?D")||cpuis("STM32L152?C"))
|
|
sif (cpuis("STM32L1?2?D"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port H bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,A22,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port H bit 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port H bit 1" "OSC_OUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port H bit 0" "OSC_IN,?..."
|
|
else
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOH_MODER,GPIO port H mode register"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOH_OTYPER,GPIO port H mode register"
|
|
bitfld.long 0x04 1. " OT1 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOH_OSPEEDR,GPIO port H output speed register"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port H output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port H output speed register" "400 kHz,2 MHz,10 MHz,40 MHz"
|
|
line.long 0x0C "GPIOH_PUPDR,GPIO port H pull-up/pull-down register"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOH_IDR,GPIO port H input data register"
|
|
bitfld.long 0x00 1. " IDR1 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port H input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOH_ODR,GPIO port H output data register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port H output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port H output data" "Low,High"
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "GPIOH_LCKR,GPIO port H configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port H lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port H lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOH_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port H bit 1" "OSC_OUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port H bit 0" "OSC_IN,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree "RI (Routing Interface)"
|
|
base ad:0x40007C00
|
|
width 11.
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "RI_ICR,RI input capture register"
|
|
bitfld.long 0x00 21. " IC4 ,Routing selection for IC 4" "AF,IC4IOS"
|
|
bitfld.long 0x00 20. " IC3 ,Routing selection for IC 3" "AF,IC3IOS"
|
|
bitfld.long 0x00 19. " IC2 ,Routing selection for IC 2" "AF,IC2IOS"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IC1 ,Routing selection for IC 1" "AF,IC1IOS"
|
|
bitfld.long 0x00 16.--17. " TIM ,Timer select bits" "No timer,TIM2,TIM3,TIM4"
|
|
textline " "
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,,,,PC15,?..."
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,,,,PC14,?..."
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,,,,PC13,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,PC3,PC7,PC11,PC15,?..."
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,PC2,PC6,PC10,PC14,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,PC1,PC5,PC9,PC13,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,PC0,PC4,PC8,PC12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,PC3,PC7,PC11,PC15,PD3,PD7,PD11,PD15,PE3,PE7,PE11,PE15"
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,PC2,PC6,PC10,PC14,PD2,PD6,PD10,PD14,PE2,PE6,PE10,PE14"
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,PC1,PC5,PC9,PC13,PD1,PD5,PD9,PD13,PE1,PE5,PE9,PE13"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,PC0,PC4,PC8,PC12,PD0,PD4,PD8,PD12,PE0,PE4,PE8,PE12"
|
|
endif
|
|
line.long 0x04 "RI_ASCR1,RI analog switches control register"
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x04 31. " SCM ,Switch control mode" "Opened|ADC,Closed|I/O"
|
|
bitfld.long 0x04 30. " CH30 ,Analog I/O switch control of channel 30" "Opened,Closed"
|
|
bitfld.long 0x04 29. " CH29 ,Analog I/O switch control of channel 29" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 28. " CH28 ,Analog I/O switch control of channel 28" "Opened,Closed"
|
|
bitfld.long 0x04 27. " CH27 ,Analog I/O switch control of channel 27" "Opened,Closed"
|
|
bitfld.long 0x04 26. " VCOMP ,ADC analog switch selection for internal node to comparator 1" "Opened,Closed"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 31. " SCM ,Switch control mode" "Opened|ADC,Closed|I/O"
|
|
bitfld.long 0x04 26. " VCOMP ,ADC analog switch selection for internal node to comparator 1" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " CH25 ,Analog I/O switch control of channel 25" "Opened,Closed"
|
|
bitfld.long 0x04 24. " CH24 ,Analog I/O switch control of channel 24" "Opened,Closed"
|
|
bitfld.long 0x04 23. " CH23 ,Analog I/O switch control of channel 23" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CH22 ,Analog I/O switch control of channel 22" "Opened,Closed"
|
|
bitfld.long 0x04 21. " CH21 ,Analog I/O switch control of channel 21" "Opened,Closed"
|
|
bitfld.long 0x04 20. " CH20 ,Analog I/O switch control of channel 20" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CH19 ,Analog I/O switch control of channel 19" "Opened,Closed"
|
|
bitfld.long 0x04 18. " CH18 ,Analog I/O switch control of channel 18" "Opened,Closed"
|
|
textline " "
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x04 16. " CH31 , Analog I/O switch control of channel 16" "Opened,Closed"
|
|
bitfld.long 0x04 15. " CH15 ,Analog I/O switch control of channel 15" "Opened,Closed"
|
|
bitfld.long 0x04 14. " CH14 ,Analog I/O switch control of channel 14" "Opened,Closed"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 15. " CH15 ,Analog I/O switch control of channel 15" "Opened,Closed"
|
|
bitfld.long 0x04 14. " CH14 ,Analog I/O switch control of channel 14" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 13. " CH13 ,Analog I/O switch control of channel 13" "Opened,Closed"
|
|
bitfld.long 0x04 12. " CH12 ,Analog I/O switch control of channel 12" "Opened,Closed"
|
|
bitfld.long 0x04 11. " CH11 ,Analog I/O switch control of channel 11" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CH10 ,Analog I/O switch control of channel 10" "Opened,Closed"
|
|
bitfld.long 0x04 9. " CH9 ,Analog I/O switch control of channel 9" "Opened,Closed"
|
|
bitfld.long 0x04 8. " CH8 ,Analog I/O switch control of channel 8" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7 ,Analog I/O switch control of channel 7" "Opened,Closed"
|
|
bitfld.long 0x04 6. " CH6 ,Analog I/O switch control of channel 6" "Opened,Closed"
|
|
bitfld.long 0x04 5. " CH5 ,Comparator 1 analog switch" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CH4 ,Analog I/O switch control of channel 4" "Opened,Closed"
|
|
bitfld.long 0x04 3. " CH3 ,Analog I/O switch control of channel 3" "Opened,Closed"
|
|
bitfld.long 0x04 2. " CH2 ,Analog I/O switch control of channel 2" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CH1 ,Analog I/O switch control of channel 1" "Opened,Closed"
|
|
bitfld.long 0x04 0. " CH0 ,Analog I/O switch control of channel 0" "Opened,Closed"
|
|
line.long 0x08 "RI_ASCR2,RI analog switch control register 2"
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x08 28. " GR6-4 ,GR6-4 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 27. " GR6-3 ,GR6-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 26. " GR7-7 ,GR7-7 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 25. " GR7-6 ,GR7-6 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 24. " GR7-5 ,GR7-5 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 23. " GR2-5 ,GR2-5 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 22. " GR2-4 ,GR2-4 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 21. " GR2-3 ,GR2-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 20. " GR9-4 ,GR9-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 19. " GR9-3 ,GR9-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 18. " GR3-5 ,GR3-5 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 17. " GR3-4 ,GR3-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 16. " GR13-3 ,GR3-3 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " GR4-3 ,GR4-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 10. " GR4-2 ,GR4-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 9. " GR4-1 ,GR4-1 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 8. " GR5-3 ,GR5-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 7. " GR5-2 ,GR5-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 6. " GR5-1 ,GR5-1 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GR6-2 ,GR6-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 4. " GR6-1 ,GR6-1 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 3. " GR10-4 ,GR10-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 2. " GR10-3 ,GR10-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 1. " GR10-2 ,GR10-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 0. " GR10-1 ,GR10-1 analog switch control" "Opened,Closed"
|
|
line.long 0x0C "RI_HYSCR1,RI hysteresis control register for ports A and B"
|
|
bitfld.long 0xC 31. " PB15 ,Port B hysteresis control 15" "On,Off"
|
|
bitfld.long 0xC 30. " PB14 ,Port B hysteresis control 14" "On,Off"
|
|
bitfld.long 0xC 29. " PB13 ,Port B hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 28. " PB12 ,Port B hysteresis control 12" "On,Off"
|
|
bitfld.long 0xC 27. " PB11 ,Port B hysteresis control 11" "On,Off"
|
|
bitfld.long 0xC 26. " PB10 ,Port B hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 25. " PB9 ,Port B hysteresis control 9" "On,Off"
|
|
bitfld.long 0xC 24. " PB8 ,Port B hysteresis control 8" "On,Off"
|
|
bitfld.long 0xC 23. " PB7 ,Port B hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 22. " PB6 ,Port B hysteresis control 6" "On,Off"
|
|
bitfld.long 0xC 21. " PB5 ,Port B hysteresis control 5" "On,Off"
|
|
bitfld.long 0xC 20. " PB4 ,Port B hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PB3 ,Port B hysteresis control 3" "On,Off"
|
|
bitfld.long 0xC 18. " PB2 ,Port B hysteresis control 2" "On,Off"
|
|
bitfld.long 0xC 17. " PB1 ,Port B hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 16. " PB0 ,Port B hysteresis control 0" "On,Off"
|
|
bitfld.long 0xC 15. " PA15 ,Port A hysteresis control 15" "On,Off"
|
|
bitfld.long 0xC 14. " PA14 ,Port A hysteresis control 14" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 13. " PA13 ,Port A hysteresis control 13" "On,Off"
|
|
bitfld.long 0xC 12. " PA12 ,Port A hysteresis control 12" "On,Off"
|
|
bitfld.long 0xC 11. " PA11 ,Port A hysteresis control 11" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 10. " PA10 ,Port A hysteresis control 10" "On,Off"
|
|
bitfld.long 0xC 9. " PA9 ,Port A hysteresis control 9" "On,Off"
|
|
bitfld.long 0xC 8. " PA8 ,Port A hysteresis control 8" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 7. " PA7 ,Port A hysteresis control 7" "On,Off"
|
|
bitfld.long 0xC 6. " PA6 ,Port A hysteresis control 6" "On,Off"
|
|
bitfld.long 0xC 5. " PA5 ,Port A hysteresis control 5" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PA4 ,Port A hysteresis control 4" "On,Off"
|
|
bitfld.long 0xC 3. " PA3 ,Port A hysteresis control 3" "On,Off"
|
|
bitfld.long 0xC 2. " PA2 ,Port A hysteresis control 2" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 1. " PA1 ,Port A hysteresis control 1" "On,Off"
|
|
bitfld.long 0xC 0. " PA0 ,Port A hysteresis control 0" "On,Off"
|
|
line.long 0x10 "RI_HYSCR2,RI hysteresis control register for ports C and D"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control 15" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control 14" "On,Off"
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control 13" "On,Off"
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.long 0x10 18. " PD2 ,Port D hysteresis control 2" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control 15" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control 14" "On,Off"
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 12. " PC12 ,Port C hysteresis control 12" "On,Off"
|
|
bitfld.long 0x10 11. " PC11 ,Port C hysteresis control 11" "On,Off"
|
|
bitfld.long 0x10 10. " PC10 ,Port C hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 9. " PC9 ,Port C hysteresis control 9" "On,Off"
|
|
bitfld.long 0x10 8. " PC8 ,Port C hysteresis control 8" "On,Off"
|
|
bitfld.long 0x10 7. " PC7 ,Port C hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 6. " PC6 ,Port C hysteresis control 6" "On,Off"
|
|
bitfld.long 0x10 5. " PC5 ,Port C hysteresis control 5" "On,Off"
|
|
bitfld.long 0x10 4. " PC4 ,Port C hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PC3 ,Port C hysteresis control 3" "On,Off"
|
|
bitfld.long 0x10 2. " PC2 ,Port C hysteresis control 2" "On,Off"
|
|
bitfld.long 0x10 1. " PC1 ,Port C hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PC0 ,Port C hysteresis control 0" "On,Off"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 31. " PD15 ,Port D hysteresis control 15" "On,Off"
|
|
bitfld.long 0x10 30. " PD14 ,Port D hysteresis control 14" "On,Off"
|
|
bitfld.long 0x10 29. " PD13 ,Port D hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 28. " PD12 ,Port D hysteresis control 12" "On,Off"
|
|
bitfld.long 0x10 27. " PD11 ,Port D hysteresis control 11" "On,Off"
|
|
bitfld.long 0x10 26. " PD10 ,Port D hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PD9 ,Port D hysteresis control 9" "On,Off"
|
|
bitfld.long 0x10 24. " PD8 ,Port D hysteresis control 8" "On,Off"
|
|
bitfld.long 0x10 23. " PD7 ,Port D hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 22. " PD6 ,Port D hysteresis control 6" "On,Off"
|
|
bitfld.long 0x10 21. " PD5 ,Port D hysteresis control 5" "On,Off"
|
|
bitfld.long 0x10 20. " PD4 ,Port D hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PD3 ,Port D hysteresis control 3" "On,Off"
|
|
bitfld.long 0x10 18. " PD2 ,Port D hysteresis control 2" "On,Off"
|
|
bitfld.long 0x10 17. " PD1 ,Port D hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 16. " PD0 ,Port D hysteresis control 0" "On,Off"
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control 15" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control 14" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control 13" "On,Off"
|
|
bitfld.long 0x10 12. " PC12 ,Port C hysteresis control 12" "On,Off"
|
|
bitfld.long 0x10 11. " PC11 ,Port C hysteresis control 11" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 10. " PC10 ,Port C hysteresis control 10" "On,Off"
|
|
bitfld.long 0x10 9. " PC9 ,Port C hysteresis control 9" "On,Off"
|
|
bitfld.long 0x10 8. " PC8 ,Port C hysteresis control 8" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 7. " PC7 ,Port C hysteresis control 7" "On,Off"
|
|
bitfld.long 0x10 6. " PC6 ,Port C hysteresis control 6" "On,Off"
|
|
bitfld.long 0x10 5. " PC5 ,Port C hysteresis control 5" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PC4 ,Port C hysteresis control 4" "On,Off"
|
|
bitfld.long 0x10 3. " PC3 ,Port C hysteresis control 3" "On,Off"
|
|
bitfld.long 0x10 2. " PC2 ,Port C hysteresis control 2" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PC1 ,Port C hysteresis control 1" "On,Off"
|
|
bitfld.long 0x10 0. " PC0 ,Port C hysteresis control 0" "On,Off"
|
|
endif
|
|
sif cpuis("STM32L162ZE")||cpuis("STM32L151QE")||cpuis("STM32L152QE")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RI_HYSCR3,RI hysteresis control register for port E and F"
|
|
bitfld.long 0x00 31. " PF15 ,Port F hysteresis control 15" "On,Off"
|
|
bitfld.long 0x00 30. " PF14 ,Port F hysteresis control 14" "On,Off"
|
|
bitfld.long 0x00 29. " PF13 ,Port F hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PF12 ,Port F hysteresis control 12" "On,Off"
|
|
bitfld.long 0x00 27. " PF11 ,Port F hysteresis control 11" "On,Off"
|
|
textline " "
|
|
sif cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 26. " PF10 ,Port F hysteresis control 10" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " PF9 ,Port F hysteresis control 9" "On,Off"
|
|
bitfld.long 0x00 24. " PF8 ,Port F hysteresis control 8" "On,Off"
|
|
bitfld.long 0x00 23. " PF7 ,Port F hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PF6 ,Port F hysteresis control 6" "On,Off"
|
|
bitfld.long 0x00 21. " PF5 ,Port F hysteresis control 5" "On,Off"
|
|
bitfld.long 0x00 20. " PF4 ,Port F hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PF3 ,Port F hysteresis control 3" "On,Off"
|
|
bitfld.long 0x00 18. " PF2 ,Port F hysteresis control 2" "On,Off"
|
|
bitfld.long 0x00 17. " PF1 ,Port F hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PF0 ,Port F hysteresis control 0" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PE15 ,Port E hysteresis control 15" "On,Off"
|
|
bitfld.long 0x00 14. " PE14 ,Port E hysteresis control 14" "On,Off"
|
|
bitfld.long 0x00 13. " PE13 ,Port E hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PE12 ,Port E hysteresis control 12" "On,Off"
|
|
bitfld.long 0x00 11. " PE11 ,Port E hysteresis control 11" "On,Off"
|
|
bitfld.long 0x00 10. " PE10 ,Port E hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PE9 ,Port E hysteresis control 9" "On,Off"
|
|
bitfld.long 0x00 8. " PE8 ,Port E hysteresis control 8" "On,Off"
|
|
bitfld.long 0x00 7. " PE7 ,Port E hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PE6 ,Port E hysteresis control 6" "On,Off"
|
|
bitfld.long 0x00 5. " PE5 ,Port E hysteresis control 5" "On,Off"
|
|
bitfld.long 0x00 4. " PE4 ,Port E hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PE3 ,Port E hysteresis control 3" "On,Off"
|
|
bitfld.long 0x00 2. " PE2 ,Port E hysteresis control 2" "On,Off"
|
|
bitfld.long 0x00 1. " PE1 ,Port E hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE0 ,Port E hysteresis control 0" "On,Off"
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RI_HYSCR3,RI hysteresis control register for port E and F"
|
|
bitfld.long 0x00 15. " PE15 ,Port E hysteresis control 15" "On,Off"
|
|
bitfld.long 0x00 14. " PE14 ,Port E hysteresis control 14" "On,Off"
|
|
bitfld.long 0x00 13. " PE13 ,Port E hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PE12 ,Port E hysteresis control 12" "On,Off"
|
|
bitfld.long 0x00 11. " PE11 ,Port E hysteresis control 11" "On,Off"
|
|
bitfld.long 0x00 10. " PE10 ,Port E hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PE9 ,Port E hysteresis control 9" "On,Off"
|
|
bitfld.long 0x00 8. " PE8 ,Port E hysteresis control 8" "On,Off"
|
|
bitfld.long 0x00 7. " PE7 ,Port E hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PE6 ,Port E hysteresis control 6" "On,Off"
|
|
bitfld.long 0x00 5. " PE5 ,Port E hysteresis control 5" "On,Off"
|
|
bitfld.long 0x00 4. " PE4 ,Port E hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PE3 ,Port E hysteresis control 3" "On,Off"
|
|
bitfld.long 0x00 2. " PE2 ,Port E hysteresis control 2" "On,Off"
|
|
bitfld.long 0x00 1. " PE1 ,Port E hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE0 ,Port E hysteresis control 0" "On,Off"
|
|
endif
|
|
sif cpuis("STM32L162ZE")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RI_HYSCR4,RI hysteresis control register for port G"
|
|
bitfld.long 0x00 15. " PG15 ,Port G hysteresis control 15" "On,Off"
|
|
bitfld.long 0x00 14. " PG14 ,Port G hysteresis control 14" "On,Off"
|
|
bitfld.long 0x00 13. " PG13 ,Port G hysteresis control 13" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PG12 ,Port G hysteresis control 12" "On,Off"
|
|
bitfld.long 0x00 11. " PG11 ,Port G hysteresis control 11" "On,Off"
|
|
bitfld.long 0x00 10. " PG10 ,Port G hysteresis control 10" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PG9 ,Port G hysteresis control 9" "On,Off"
|
|
bitfld.long 0x00 8. " PG8 ,Port G hysteresis control 8" "On,Off"
|
|
bitfld.long 0x00 7. " PG7 ,Port G hysteresis control 7" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PG6 ,Port G hysteresis control 6" "On,Off"
|
|
bitfld.long 0x00 5. " PG5 ,Port G hysteresis control 5" "On,Off"
|
|
bitfld.long 0x00 4. " PG4 ,Port G hysteresis control 4" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PG3 ,Port G hysteresis control 3" "On,Off"
|
|
bitfld.long 0x00 2. " PG2 ,Port G hysteresis control 2" "On,Off"
|
|
bitfld.long 0x00 1. " PG1 ,Port G hysteresis control 1" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PG0 ,Port G hysteresis control 0" "On,Off"
|
|
textline " "
|
|
elif cpuis("STM32L151QE")||cpuis("STM32L152QE")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RI_HYSCR4,RI hysteresis control register for port G"
|
|
bitfld.long 0x00 14. " PG14 ,Port G hysteresis control 14" "On,Off"
|
|
bitfld.long 0x00 13. " PG13 ,Port G hysteresis control 13" "On,Off"
|
|
bitfld.long 0x00 12. " PG12 ,Port G hysteresis control 12" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PG10 ,Port G hysteresis control 10" "On,Off"
|
|
bitfld.long 0x00 9. " PG9 ,Port G hysteresis control 9" "On,Off"
|
|
bitfld.long 0x00 5. " PG5 ,Port G hysteresis control 5" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PG4 ,Port G hysteresis control 4" "On,Off"
|
|
bitfld.long 0x00 3. " PG3 ,Port G hysteresis control 3" "On,Off"
|
|
bitfld.long 0x00 2. " PG2 ,Port G hysteresis control 2" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PG1 ,Port G hysteresis control 1" "On,Off"
|
|
bitfld.long 0x00 0. " PG0 ,Port G hysteresis control 0" "On,Off"
|
|
endif
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "RI_ASMR1,Analog switch mode register for port A"
|
|
bitfld.long 0x00 15. " PA15 ,Port A analog siwtch mode selection 15" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 14. " PA14 ,Port A analog siwtch mode selection 14" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 13. " PA13 ,Port A analog siwtch mode selection 13" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PA10 ,Port A analog siwtch mode selection 10" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 9. " PA9 ,Port A analog siwtch mode selection 9" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 8. " PA8 ,Port A analog siwtch mode selection 8" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PA7 ,Port A analog siwtch mode selection 7" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 6. " PA6 ,Port A analog siwtch mode selection 6" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 5. " PA5 ,Port A analog siwtch mode selection 5" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PA4 ,Port A analog siwtch mode selection 4" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 3. " PA3 ,Port A analog siwtch mode selection 3" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 2. " PA2 ,Port A analog siwtch mode selection 2" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PA1 ,Port A analog siwtch mode selection 1" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 0. " PA0 ,Port A analog siwtch mode selection 0" "ADC/RI_ASCR1,Timer"
|
|
line.long 0x04 "RI_CMR1,Channel mask register for port A"
|
|
bitfld.long 0x04 15. " PA15 ,Port A channel masking 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PA14 ,Port A channel masking 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PA13 ,Port A channel masking 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PA12 ,Port A channel masking" "Masked,Not masked 12"
|
|
bitfld.long 0x04 11. " PA11 ,Port A channel masking 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " PA10 ,Port A channel masking 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PA9 ,Port A channel masking 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PA8 ,Port A channel masking 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PA7 ,Port A channel masking 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PA6 ,Port A channel masking 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PA5 ,Port A channel masking 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PA4 ,Port A channel masking 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PA3 ,Port A channel masking 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PA2 ,Port A channel masking 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PA1 ,Port A channel masking 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PA0 ,Port A channel masking 0" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR1,Channel identification for capture register for port A"
|
|
bitfld.long 0x08 15. " PA15 ,Port A channel identification for capture 15" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PA14 ,Port A channel identification for capture 14" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PA13 ,Port A channel identification for capture 13" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PA12 ,Port A channel identification for capture 12" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PA11 ,Port A channel identification for capture 11" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 10. " PA10 ,Port A channel identification for capture 10" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PA9 ,Port A channel identification for capture 9" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PA8 ,Port A channel identification for capture 8" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PA7 ,Port A channel identification for capture 7" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PA6 ,Port A channel identification for capture 6" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PA5 ,Port A channel identification for capture 5" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PA4 ,Port A channel identification for capture 4" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PA3 ,Port A channel identification for capture 3" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PA2 ,Port A channel identification for capture 2" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PA1 ,Port A channel identification for capture 1" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PA0 ,Port A channel identification for capture 0" "Channel I/O,Sampling capacitor I/O"
|
|
group.long 0x2C++0x0B
|
|
line.long 0x00 "RI_ASMR2,Analog switch mode register for port B"
|
|
bitfld.long 0x00 15. " PB15 ,Port B analog siwtch mode selection 15" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 14. " PB14 ,Port B analog siwtch mode selection 14" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 13. " PB13 ,Port B analog siwtch mode selection 13" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PB12 ,Port B analog siwtch mode selection 12" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 7. " PB7 ,Port B analog siwtch mode selection 7" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PB6 ,Port B analog siwtch mode selection 6" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 5. " PB5 ,Port B analog siwtch mode selection 5" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 4. " PB4 ,Port B analog siwtch mode selection 4" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PB2 ,Port B analog siwtch mode selection 2" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 1. " PB1 ,Port B analog siwtch mode selection 1" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PB0 ,Port B analog siwtch mode selection 0" "ADC/RI_ASCR1,Timer"
|
|
line.long 0x04 "RI_CMR2,Channel mask register for port B"
|
|
bitfld.long 0x04 15. " PB15 ,Port B channel masking 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PB14 ,Port B channel masking 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PB13 ,Port B channel masking 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PB12 ,Port B channel masking" "Masked,Not masked 12"
|
|
bitfld.long 0x04 11. " PB11 ,Port B channel masking 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " PB10 ,Port B channel masking 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PB9 ,Port B channel masking 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PB8 ,Port B channel masking 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PB7 ,Port B channel masking 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PB6 ,Port B channel masking 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PB5 ,Port B channel masking 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PB4 ,Port B channel masking 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PB3 ,Port B channel masking 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PB2 ,Port B channel masking 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PB1 ,Port B channel masking 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PB0 ,Port B channel masking 0" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR2,Channel identification for capture register for port B"
|
|
bitfld.long 0x08 15. " PB15 ,Port B channel identification for capture 15" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PB14 ,Port B channel identification for capture 14" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PB13 ,Port B channel identification for capture 13" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PB12 ,Port B channel identification for capture 12" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PB11 ,Port B channel identification for capture 11" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 10. " PB10 ,Port B channel identification for capture 10" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PB9 ,Port B channel identification for capture 9" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PB8 ,Port B channel identification for capture 8" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PB7 ,Port B channel identification for capture 7" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PB6 ,Port B channel identification for capture 6" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PB5 ,Port B channel identification for capture 5" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PB4 ,Port B channel identification for capture 4" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PB3 ,Port B channel identification for capture 3" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PB2 ,Port B channel identification for capture 2" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PB1 ,Port B channel identification for capture 1" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PB0 ,Port B channel identification for capture 0" "Channel I/O,Sampling capacitor I/O"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "RI_ASMR3,Analog switch mode register for port C"
|
|
bitfld.long 0x00 9. " PC9 ,Port C analog siwtch mode selection 9" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 8. " PC8 ,Port C analog siwtch mode selection 8" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 7. " PC7 ,Port C analog siwtch mode selection 7" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PC6 ,Port C analog siwtch mode selection 6" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 5. " PC5 ,Port C analog siwtch mode selection 5" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 4. " PC4 ,Port C analog siwtch mode selection 4" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PC3 ,Port C analog siwtch mode selection 3" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 2. " PC2 ,Port C analog siwtch mode selection 2" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 1. " PC1 ,Port C analog siwtch mode selection 1" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PC0 ,Port C analog siwtch mode selection 0" "ADC/RI_ASCR1,Timer"
|
|
line.long 0x04 "RI_CMR3,Channel mask register for port C"
|
|
bitfld.long 0x04 15. " PC15 ,Port C channel masking 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PC14 ,Port C channel masking 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PC13 ,Port C channel masking 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PC12 ,Port C channel masking" "Masked,Not masked 12"
|
|
bitfld.long 0x04 11. " PC11 ,Port C channel masking 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " PC10 ,Port C channel masking 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PC9 ,Port C channel masking 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PC8 ,Port C channel masking 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PC7 ,Port C channel masking 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PC6 ,Port C channel masking 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PC5 ,Port C channel masking 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PC4 ,Port C channel masking 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PC3 ,Port C channel masking 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PC2 ,Port C channel masking 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PC1 ,Port C channel masking 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PC0 ,Port C channel masking 0" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR3,Channel identification for capture register for port C"
|
|
bitfld.long 0x08 15. " PC15 ,Port C channel identification for capture 15" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PC14 ,Port C channel identification for capture 14" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PC13 ,Port C channel identification for capture 13" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PC12 ,Port C channel identification for capture 12" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PC11 ,Port C channel identification for capture 11" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 10. " PC10 ,Port C channel identification for capture 10" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PC9 ,Port C channel identification for capture 9" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PC8 ,Port C channel identification for capture 8" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PC7 ,Port C channel identification for capture 7" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PC6 ,Port C channel identification for capture 6" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PC5 ,Port C channel identification for capture 5" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PC4 ,Port C channel identification for capture 4" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PC3 ,Port C channel identification for capture 3" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PC2 ,Port C channel identification for capture 2" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PC1 ,Port C channel identification for capture 1" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PC0 ,Port C channel identification for capture 0" "Channel I/O,Sampling capacitor I/O"
|
|
sif !cpuis("STM32L100RC")
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "RI_ASMR4,Analog switch mode register for port F"
|
|
bitfld.long 0x00 15. " PF15 ,Port F analog siwtch mode selection 15" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 14. " PF14 ,Port F analog siwtch mode selection 14" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 13. " PF13 ,Port F analog siwtch mode selection 13" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PF12 ,Port F analog siwtch mode selection 12" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 11. " PF11 ,Port F analog siwtch mode selection 11" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 10. " PF10 ,Port F analog siwtch mode selection 10" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PF9 ,Port F analog siwtch mode selection 9" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 8. " PF8 ,Port F analog siwtch mode selection 8" "ADC/RI_ASCR1,Timer"
|
|
bitfld.long 0x00 7. " PF7 ,Port F analog siwtch mode selection 7" "ADC/RI_ASCR1,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PF6 ,Port F analog siwtch mode selection 6" "ADC/RI_ASCR1,Timer"
|
|
line.long 0x04 "RI_CMR4,Channel mask register for port F"
|
|
bitfld.long 0x04 15. " PF15 ,Port F channel masking 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PF14 ,Port F channel masking 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PF13 ,Port F channel masking 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PF12 ,Port F channel masking" "Masked,Not masked 12"
|
|
bitfld.long 0x04 11. " PF11 ,Port F channel masking 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " PF10 ,Port F channel masking 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PF9 ,Port F channel masking 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PF8 ,Port F channel masking 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PF7 ,Port F channel masking 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PF6 ,Port F channel masking 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PF5 ,Port F channel masking 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PF4 ,Port F channel masking 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PF3 ,Port F channel masking 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PF2 ,Port F channel masking 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PF1 ,Port F channel masking 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PF0 ,Port F channel masking 0" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR4,Channel identification for capture register for port F"
|
|
bitfld.long 0x08 15. " PF15 ,Port F channel identification for capture 15" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PF14 ,Port F channel identification for capture 14" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PF13 ,Port F channel identification for capture 13" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PF12 ,Port F channel identification for capture 12" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PF11 ,Port F channel identification for capture 11" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 10. " PF10 ,Port F channel identification for capture 10" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PF9 ,Port F channel identification for capture 9" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PF8 ,Port F channel identification for capture 8" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PF7 ,Port F channel identification for capture 7" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PF6 ,Port F channel identification for capture 6" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PF5 ,Port F channel identification for capture 5" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PF4 ,Port F channel identification for capture 4" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PF3 ,Port F channel identification for capture 3" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PF2 ,Port F channel identification for capture 2" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PF1 ,Port F channel identification for capture 1" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PF0 ,Port F channel identification for capture 0" "Channel I/O,Sampling capacitor I/O"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "RI_ASMR5,Analog switch mode register for port G"
|
|
bitfld.long 0x00 4. " PG4 ,Port G analog siwtch mode selection 4" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 3. " PG3 ,Port G analog siwtch mode selection 3" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 2. " PG2 ,Port G analog siwtch mode selection 2" "ADC/RI_ASCR2,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PG1 ,Port G analog siwtch mode selection 1" "ADC/RI_ASCR2,Timer"
|
|
bitfld.long 0x00 0. " PG0 ,Port G analog siwtch mode selection 0" "ADC/RI_ASCR2,Timer"
|
|
line.long 0x04 "RI_CMR5,Channel mask register for port G"
|
|
bitfld.long 0x04 15. " PG15 ,Port G channel masking 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PG14 ,Port G channel masking 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PG13 ,Port G channel masking 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PG12 ,Port G channel masking" "Masked,Not masked 12"
|
|
bitfld.long 0x04 11. " PG11 ,Port G channel masking 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " PG10 ,Port G channel masking 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PG9 ,Port G channel masking 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PG8 ,Port G channel masking 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PG7 ,Port G channel masking 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PG6 ,Port G channel masking 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PG5 ,Port G channel masking 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PG4 ,Port G channel masking 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PG3 ,Port G channel masking 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PG2 ,Port G channel masking 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PG1 ,Port G channel masking 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PG0 ,Port G channel masking 0" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR5,Channel identification for capture register for port G"
|
|
bitfld.long 0x08 15. " PG15 ,Port G channel identification for capture 15" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PG14 ,Port G channel identification for capture 14" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PG13 ,Port G channel identification for capture 13" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PG12 ,Port G channel identification for capture 12" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PG11 ,Port G channel identification for capture 11" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 10. " PG10 ,Port G channel identification for capture 10" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 9. " PG9 ,Port G channel identification for capture 9" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PG8 ,Port G channel identification for capture 8" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PG7 ,Port G channel identification for capture 7" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PG6 ,Port G channel identification for capture 6" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PG5 ,Port G channel identification for capture 5" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PG4 ,Port G channel identification for capture 4" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PG3 ,Port G channel identification for capture 3" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PG2 ,Port G channel identification for capture 2" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PG1 ,Port G channel identification for capture 1" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PG0 ,Port G channel identification for capture 0" "Channel I/O,Sampling capacitor I/O"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "RI (Routing Interface)"
|
|
base ad:0x40007C00
|
|
width 11.
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "RI_ICR,RI input capture register"
|
|
bitfld.long 0x00 21. " IC4 ,Routing selection for IC 4" "AF,IC4IOS"
|
|
bitfld.long 0x00 20. " IC3 ,Routing selection for IC 3" "AF,IC3IOS"
|
|
bitfld.long 0x00 19. " IC2 ,Routing selection for IC 2" "AF,IC2IOS"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IC1 ,Routing selection for IC 1" "AF,IC1IOS"
|
|
bitfld.long 0x00 16.--17. " TIM ,Timer select bits" "No timer,TIM2,TIM3,TIM4"
|
|
textline " "
|
|
sif (cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162VD")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,PC3,PC7,PC11,PC15,PD3,PD7,PD11,PD15,PE3,PE7,PE11,PE15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,PC2,PC6,PC10,PC14,PD2,PD6,PD10,PD14,PE2,PE6,PE10,PE14"
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,PC1,PC5,PC9,PC13,PD1,PD5,PD9,PD13,PE1,PE5,PE9,PE13"
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,PC0,PC4,PC8,PC12,PD0,PD4,PD8,PD12,PE0,PE4,PE8,PE12"
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?"))
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,PC3,PC7,PC11,PC15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,PC2,PC6,PC10,PC14,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,PC1,PC5,PC9,PC13,?..."
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,PC0,PC4,PC8,PC12,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12.--15. " IC4IOS ,Input capture 4 select bits" "PA3,PA7,PA11,PA15,Reserved,Reserved,Reserved,PC15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " IC3IOS ,Input capture 3 select bits" "PA2,PA6,PA10,PA14,Reserved,Reserved,Reserved,PC14,?..."
|
|
bitfld.long 0x00 4.--7. " IC2IOS ,Input capture 2 select bits" "PA1,PA5,PA9,PA13,Reserved,Reserved,Reserved,PC13,?..."
|
|
bitfld.long 0x00 0.--3. " IC1IOS ,Input capture 1 select bits" "PA0,PA4,PA8,PA12,?..."
|
|
endif
|
|
line.long 0x04 "RI_ASCR1,RI analog switches control register"
|
|
bitfld.long 0x04 31. " SCM ,Switch control mode" "Opened|ADC,Closed|I/O"
|
|
textline " "
|
|
sif ((cpuis("STM32L151Z?"))||(cpuis("STM32L152Z?"))||(cpuis("STM32L162ZD"))||(cpuis("STM32L162QD"))||(cpuis("STM32L151Q?"))||(cpuis("STM32L152Q?")))
|
|
bitfld.long 0x04 30. " CH30 ,Analog I/O switch control of channel 30" "Opened,Closed"
|
|
bitfld.long 0x04 29. " CH29 ,Analog I/O switch control of channel 29" "Opened,Closed"
|
|
bitfld.long 0x04 28. " CH28 ,Analog I/O switch control of channel 28" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CH27 ,Analog I/O switch control of channel 27" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 26. " VCOMP ,ADC analog switch selection for internal node to comparator 1" "Opened,Closed"
|
|
textline " "
|
|
sif ((!cpuis("STM32L162VD"))&&(!cpuis("STM32L15?V?"))&&(!cpuis("STM32L15?R?"))&&(!cpuis("STM32L15?C?"))&&(!cpuis("STM32L162RD")))
|
|
bitfld.long 0x04 25. " CH25 ,Analog I/O switch control of channel 25" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("STM32L15?V?"))&&(!cpuis("STM32L15?R?"))&&(!cpuis("STM32L15?C?"))&&(!cpuis("STM32L162RD")))
|
|
bitfld.long 0x04 24. " CH24 ,Analog I/O switch control of channel 24" "Opened,Closed"
|
|
bitfld.long 0x04 23. " CH23 ,Analog I/O switch control of channel 23" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("STM32L15?R?"))&&(!cpuis("STM32L15?C?"))&&(!cpuis("STM32L162RD")))
|
|
bitfld.long 0x04 22. " CH22 ,Analog I/O switch control of channel 22" "Opened,Closed"
|
|
bitfld.long 0x04 21. " CH21 ,Analog I/O switch control of channel 21" "Opened,Closed"
|
|
bitfld.long 0x04 20. " CH20 ,Analog I/O switch control of channel 20" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " CH19 ,Analog I/O switch control of channel 19" "Opened,Closed"
|
|
bitfld.long 0x04 18. " CH18 ,Analog I/O switch control of channel 18" "Opened,Closed"
|
|
bitfld.long 0x04 15. " CH15 ,Analog I/O switch control of channel 15" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 14. " CH14 ,Analog I/O switch control of channel 14" "Opened,Closed"
|
|
bitfld.long 0x04 13. " CH13 ,Analog I/O switch control of channel 13" "Opened,Closed"
|
|
bitfld.long 0x04 12. " CH12 ,Analog I/O switch control of channel 12" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11 ,Analog I/O switch control of channel 11" "Opened,Closed"
|
|
bitfld.long 0x04 10. " CH10 ,Analog I/O switch control of channel 10" "Opened,Closed"
|
|
bitfld.long 0x04 9. " CH9 ,Analog I/O switch control of channel 9" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CH8 ,Analog I/O switch control of channel 8" "Opened,Closed"
|
|
bitfld.long 0x04 7. " CH7 ,Analog I/O switch control of channel 7" "Opened,Closed"
|
|
bitfld.long 0x04 6. " CH6 ,Analog I/O switch control of channel 6" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CH5 ,Analog I/O switch control of channel 5" "Opened,Closed"
|
|
bitfld.long 0x04 4. " CH4 ,Analog I/O switch control of channel 4" "Opened,Closed"
|
|
bitfld.long 0x04 3. " CH3 ,Analog I/O switch control of channel 3" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CH2 ,Analog I/O switch control of channel 2" "Opened,Closed"
|
|
bitfld.long 0x04 1. " CH1 ,Analog I/O switch control of channel 1" "Opened,Closed"
|
|
bitfld.long 0x04 0. " CH0 ,Analog I/O switch control of channel 0" "Opened,Closed"
|
|
line.long 0x08 "RI_ASCR2,RI analog switch control register 2"
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x08 28. " GR6-4 ,GR6-4 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 27. " GR6-3 ,GR6-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 26. " GR7-7 ,GR7-7 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 25. " GR7-6 ,GR7-6 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 24. " GR7-5 ,GR7-5 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 23. " GR2-5 ,GR2-5 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 22. " GR2-4 ,GR2-4 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 21. " GR2-3 ,GR2-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 20. " GR9-4 ,GR9-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 19. " GR9-3 ,GR9-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 18. " GR3-5 ,GR3-5 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 17. " GR3-4 ,GR3-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 16. " GR13-3 ,GR3-3 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " GR4-3 ,GR4-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 10. " GR4-2 ,GR4-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 9. " GR4-1 ,GR4-1 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 8. " GR5-3 ,GR5-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 7. " GR5-2 ,GR5-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 6. " GR5-1 ,GR5-1 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 5. " GR6-2 ,GR6-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 4. " GR6-1 ,GR6-1 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 3. " GR10-4 ,GR10-4 analog switch control" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 2. " GR10-3 ,GR10-3 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 1. " GR10-2 ,GR10-2 analog switch control" "Opened,Closed"
|
|
bitfld.long 0x08 0. " GR10-1 ,GR10-1 analog switch control" "Opened,Closed"
|
|
line.long 0xC "RI_HYSCR1,RI hysteresis control register for ports A and B"
|
|
bitfld.long 0xC 31. " PB15 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 30. " PB14 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 29. " PB13 ,Port B hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 28. " PB12 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 27. " PB11 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 26. " PB10 ,Port B hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 25. " PB9 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 24. " PB8 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 23. " PB7 ,Port B hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 22. " PB6 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 21. " PB5 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 20. " PB4 ,Port B hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PB3 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 18. " PB2 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 17. " PB1 ,Port B hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 16. " PB0 ,Port B hysteresis control" "On,Off"
|
|
bitfld.long 0xC 15. " PA15 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 14. " PA14 ,Port A hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 13. " PA13 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 12. " PA12 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 11. " PA11 ,Port A hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 10. " PA10 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 9. " PA9 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 8. " PA8 ,Port A hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 7. " PA7 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 6. " PA6 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 5. " PA5 ,Port A hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PA4 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 3. " PA3 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 2. " PA2 ,Port A hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0xC 1. " PA1 ,Port A hysteresis control" "On,Off"
|
|
bitfld.long 0xC 0. " PA0 ,Port A hysteresis control" "On,Off"
|
|
line.long 0x10 "RI_HYSCR2,RI hysteresis control register for ports C and D"
|
|
sif (cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162VD")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
bitfld.long 0x10 31. " PD15 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 30. " PD14 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 29. " PD13 ,Port D hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 28. " PD12 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 27. " PD11 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 26. " PD10 ,Port D hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PD9 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 24. " PD8 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 23. " PD7 ,Port D hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 22. " PD6 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 21. " PD5 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 20. " PD4 ,Port D hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PD3 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 18. " PD2 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 17. " PD1 ,Port D hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 16. " PD0 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 12. " PC12 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 11. " PC11 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 10. " PC10 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 9. " PC9 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 8. " PC8 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 7. " PC7 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 6. " PC6 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 5. " PC5 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PC4 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 3. " PC3 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 2. " PC2 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PC1 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 0. " PC0 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L162RD"))
|
|
bitfld.long 0x10 18. " PD2 ,Port D hysteresis control" "On,Off"
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 12. " PC12 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 11. " PC11 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 10. " PC10 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 9. " PC9 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 8. " PC8 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 7. " PC7 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 6. " PC6 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 5. " PC5 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PC4 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 3. " PC3 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 2. " PC2 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x10 1. " PC1 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 0. " PC0 ,Port C hysteresis control" "On,Off"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 15. " PC15 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 14. " PC14 ,Port C hysteresis control" "On,Off"
|
|
bitfld.long 0x10 13. " PC13 ,Port C hysteresis control" "On,Off"
|
|
endif
|
|
sif (cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162VD")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RI_HYSCR3,RI hysteresis control register for port E and F"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
bitfld.long 0x00 31. " PF15 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 30. " PF14 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 29. " PF13 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PF12 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 27. " PF11 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 26. " PF10 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " PF9 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 24. " PF8 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 23. " PF7 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PF6 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 21. " PF5 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 20. " PF4 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PF3 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 18. " PF2 ,Port F hysteresis control" "On,Off"
|
|
bitfld.long 0x00 17. " PF1 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PF0 ,Port F hysteresis control" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " PE15 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 14. " PE14 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 13. " PE13 ,Port E hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PE12 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 11. " PE11 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 10. " PE10 ,Port E hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PE9 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 8. " PE8 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 7. " PE7 ,Port E hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PE6 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 5. " PE5 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 4. " PE4 ,Port E hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PE3 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 2. " PE2 ,Port E hysteresis control" "On,Off"
|
|
bitfld.long 0x00 1. " PE1 ,Port E hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE0 ,Port E hysteresis control" "On,Off"
|
|
endif
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RI_HYSCR4,RI hysteresis control register for port G"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 15. " PG15 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " PG14 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 13. " PG13 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 12. " PG12 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 11. " PG11 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " PG10 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 9. " PG9 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 8. " PG8 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 7. " PG7 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 6. " PG6 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PG5 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 4. " PG4 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 3. " PG3 ,Port G hysteresis control" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PG2 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 1. " PG1 ,Port G hysteresis control" "On,Off"
|
|
bitfld.long 0x00 0. " PG0 ,Port G hysteresis control" "On,Off"
|
|
endif
|
|
sif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
group.long 0x20++0x23
|
|
line.long 0x0 "RI_ASMR1,Analog switch mode register for port A"
|
|
bitfld.long 0x0 15. " PA15 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 14. " PA14 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 13. " PA13 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x0 12. " PA12 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 11. " PA11 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 10. " PA10 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x0 9. " PA9 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 8. " PA8 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 7. " PA7 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x0 6. " PA6 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 5. " PA5 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 4. " PA4 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PA3 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 2. " PA2 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x0 1. " PA1 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PA0 ,Select the mode of controlling the analog switches for port A" "ADC/RI_ASCRx,Timer"
|
|
line.long 0x0+0x04 "RI_CMR1,Channel mask register for port A"
|
|
bitfld.long 0x0+0x04 15. " PA15 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 14. " PA14 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 13. " PA13 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0+0x04 12. " PA12 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 11. " PA11 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 10. " PA10 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0+0x04 9. " PA9 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 8. " PA8 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 7. " PA7 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0+0x04 6. " PA6 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 5. " PA5 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 4. " PA4 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0+0x04 3. " PA3 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 2. " PA2 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x0+0x04 1. " PA1 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0+0x04 0. " PA0 ,Port 0x0 channel masking" "Masked,Not masked"
|
|
line.long 0x0+0x08 "RI_CICR1,Channel identification for capture register for port A"
|
|
bitfld.long 0x0+0x08 15. " PA15 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 14. " PA14 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 13. " PA13 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x0+0x08 12. " PA12 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 11. " PA11 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 10. " PA10 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x0+0x08 9. " PA9 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 8. " PA8 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 7. " PA7 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x0+0x08 6. " PA6 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 5. " PA5 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 4. " PA4 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x0+0x08 3. " PA3 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 2. " PA2 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x0+0x08 1. " PA1 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x0+0x08 0. " PA0 ,Port A channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
line.long 0xC "RI_ASMR2,Analog switch mode register for port B"
|
|
bitfld.long 0xC 15. " PB15 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 14. " PB14 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 13. " PB13 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0xC 12. " PB12 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 11. " PB11 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 10. " PB10 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0xC 9. " PB9 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 8. " PB8 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 7. " PB7 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0xC 6. " PB6 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 5. " PB5 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 4. " PB4 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PB3 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 2. " PB2 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0xC 1. " PB1 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0xC 0. " PB0 ,Select the mode of controlling the analog switches for port B" "ADC/RI_ASCRx,Timer"
|
|
line.long 0xC+0x04 "RI_CMR2,Channel mask register for port B"
|
|
bitfld.long 0xC+0x04 15. " PB15 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 14. " PB14 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 13. " PB13 ,Port 0xC channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0xC+0x04 12. " PB12 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 11. " PB11 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 10. " PB10 ,Port 0xC channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0xC+0x04 9. " PB9 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 8. " PB8 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 7. " PB7 ,Port 0xC channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0xC+0x04 6. " PB6 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 5. " PB5 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 4. " PB4 ,Port 0xC channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0xC+0x04 3. " PB3 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 2. " PB2 ,Port 0xC channel masking" "Masked,Not masked"
|
|
bitfld.long 0xC+0x04 1. " PB1 ,Port 0xC channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0xC+0x04 0. " PB0 ,Port 0xC channel masking" "Masked,Not masked"
|
|
line.long 0xC+0x08 "RI_CICR2,Channel identification for capture register for port B"
|
|
bitfld.long 0xC+0x08 15. " PB15 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 14. " PB14 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 13. " PB13 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0xC+0x08 12. " PB12 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 11. " PB11 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 10. " PB10 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0xC+0x08 9. " PB9 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 8. " PB8 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 7. " PB7 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0xC+0x08 6. " PB6 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 5. " PB5 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 4. " PB4 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0xC+0x08 3. " PB3 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 2. " PB2 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0xC+0x08 1. " PB1 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0xC+0x08 0. " PB0 ,Port B channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
line.long 0x18 "RI_ASMR3,Analog switch mode register for port C"
|
|
bitfld.long 0x18 15. " PC15 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 14. " PC14 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 13. " PC13 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x18 12. " PC12 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 11. " PC11 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 10. " PC10 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x18 9. " PC9 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 8. " PC8 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 7. " PC7 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x18 6. " PC6 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 5. " PC5 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 4. " PC4 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PC3 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 2. " PC2 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x18 1. " PC1 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x18 0. " PC0 ,Select the mode of controlling the analog switches for port C" "ADC/RI_ASCRx,Timer"
|
|
line.long 0x18+0x04 "RI_CMR3,Channel mask register for port C"
|
|
bitfld.long 0x18+0x04 15. " PC15 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 14. " PC14 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 13. " PC13 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x18+0x04 12. " PC12 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 11. " PC11 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 10. " PC10 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x18+0x04 9. " PC9 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 8. " PC8 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 7. " PC7 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x18+0x04 6. " PC6 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 5. " PC5 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 4. " PC4 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x18+0x04 3. " PC3 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 2. " PC2 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
bitfld.long 0x18+0x04 1. " PC1 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x18+0x04 0. " PC0 ,Port 0x18 channel masking" "Masked,Not masked"
|
|
line.long 0x18+0x08 "RI_CICR3,Channel identification for capture register for port C"
|
|
bitfld.long 0x18+0x08 15. " PC15 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 14. " PC14 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 13. " PC13 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x18+0x08 12. " PC12 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 11. " PC11 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 10. " PC10 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x18+0x08 9. " PC9 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 8. " PC8 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 7. " PC7 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x18+0x08 6. " PC6 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 5. " PC5 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 4. " PC4 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x18+0x08 3. " PC3 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 2. " PC2 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x18+0x08 1. " PC1 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x18+0x08 0. " PC0 ,Port C channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "RI_ASMR4,Analog switch mode register for port F"
|
|
bitfld.long 0x00 15. " PF15 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 14. " PF14 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 13. " PF13 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PF12 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 11. " PF11 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 10. " PF10 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PF9 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 8. " PF8 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 7. " PF7 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PF6 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 5. " PF5 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 4. " PF4 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PF3 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 2. " PF2 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 1. " PF1 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PF0 ,Select the mode of controlling the analog switches for port F" "ADC/RI_ASCRx,Timer"
|
|
line.long 0x04 "RI_CMR4,Channel mask register for port F"
|
|
bitfld.long 0x04 15. " PF15 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " PF14 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PF13 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PF12 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " PF11 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x04 10. " PF10 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " PF9 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " PF8 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PF7 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PF6 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PF5 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PF4 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PF3 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " PF2 ,Port F channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PF1 ,Port F channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PF0 ,Port F channel masking" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR4,Channel identification for capture register for port F"
|
|
bitfld.long 0x08 15. " PF15 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 14. " PF14 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PF13 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PF12 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 11. " PF11 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x08 10. " PF10 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 9. " PF9 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 8. " PF8 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PF7 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PF6 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 5. " PF5 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PF4 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PF3 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 2. " PF2 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PF1 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PF0 ,Port F channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "RI_ASMR5,Analog switch mode register for port G"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 15. " PG15 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " PG14 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 13. " PG13 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 12. " PG12 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 11. " PG11 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " PG10 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 9. " PG9 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x00 8. " PG8 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 7. " PG7 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 6. " PG6 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " PG5 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 4. " PG4 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 3. " PG3 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PG2 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 1. " PG1 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
bitfld.long 0x00 0. " PG0 ,Select the mode of controlling the analog switches for port G" "ADC/RI_ASCRx,Timer"
|
|
line.long 0x04 "RI_CMR5,Channel mask register for port G"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x04 15. " PG15 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " PG14 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " PG13 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " PG12 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x04 11. " PG11 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 10. " PG10 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " PG9 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x04 8. " PG8 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " PG7 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " PG6 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " PG5 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " PG4 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " PG3 ,Port G channel masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PG2 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " PG1 ,Port G channel masking" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " PG0 ,Port G channel masking" "Masked,Not masked"
|
|
line.long 0x08 "RI_CICR5,Channel identification for capture register for port G"
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x08 15. " PG15 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 14. " PG14 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 13. " PG13 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 12. " PG12 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x08 11. " PG11 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 10. " PG10 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 9. " PG9 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
sif (cpuis("STM32L15?Z?")||cpuis("STM32L162ZD"))
|
|
bitfld.long 0x08 8. " PG8 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 7. " PG7 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 6. " PG6 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 5. " PG5 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 4. " PG4 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 3. " PG3 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PG2 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 1. " PG1 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
bitfld.long 0x08 0. " PG0 ,Port G channel identification for capture" "Channel I/O,Sampling capacitor I/O"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "SYSCFG_MEMRMP,SYSCFG memory remap register"
|
|
rbitfld.long 0x00 8.--9. " BOOT_MODE ,Boot mode selected by the boot pins" "Main Flash,System Flash,,SRAM"
|
|
bitfld.long 0x00 0.--1. " MEM_MODE ,Memory mapping selection" "Main Flash,System Flash,FSMC,SRAM"
|
|
line.long 0x04 "SYSCFG_PMC,SYSCFG peripheral mode configuration register"
|
|
bitfld.long 0x04 5. " LCD_CAPA[4] ,Decoupling capacitance connection of V_LCDrail3 on PE12/LCD_VCAP3" "Not connected,Connected"
|
|
bitfld.long 0x04 4. " LCD_CAPA[3] ,Decoupling capacitance connection of V_LCDrail1 on PE11/LCD_VCAP1" "Not connected,Connected"
|
|
bitfld.long 0x04 3. " LCD_CAPA[2] ,Decoupling capacitance connection of V_LCDrail3 on PB0/LCD_VCAP3" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " LCD_CAPA[1] ,Decoupling capacitance connection of V_LCDrail1 on PB12/LCD_VCAP1" "Not connected,Connected"
|
|
bitfld.long 0x04 1. " LCD_CAPA[0] ,Decoupling capacitance connection of V_LCDrail2 on PB2/LCD_VCAP2" "Not connected,Connected"
|
|
bitfld.long 0x04 0. " USB_PU ,USB pull-up enable on DP line" "No pull-up,Pull-up"
|
|
sif cpuis("STM32L162ZE")
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,PF3,PG3,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PH2,PF2,PG2,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PH1,PF3,PG1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PH0,PF0,PG0,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,PF7,PG7,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,,PF6,PG6,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,PF5,PG5,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,,PF4,PG4,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,,PF11,PG11,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,,PF10,PG10,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,,PF9,PG9,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,PF8,PG8,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,PF15,PG15,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,PF14,PG14,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,PF13,PG13,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,PF12,PG12,?..."
|
|
elif cpuis("STM32L151QE")||cpuis("STM32L152QE")
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,PF3,PG3,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PH2,PF2,PG2,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PH1,PF3,PG1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PH0,PF0,PG0,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,PF7,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,,PF6,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,PF5,PG5,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,,PF4,PG4,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,,PF11,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,,,PG10,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,,PF9,PG9,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,PF8,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,PF15,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,PF14,PG14,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,PF13,PG13,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,PF12,PG12,?..."
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PH2,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PH0,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PH0,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PH1,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PH0,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "SYSCFG_MEMRMP,SYSCFG memory remap register"
|
|
bitfld.long 0x00 8.--9. " BOOT_MODE ,Boot mode selected by the boot pins" "Main Flash,System Flash,Reserved,SRAM"
|
|
bitfld.long 0x00 0.--1. " MEM_MODE ,Memory mapping selection" "Main Flash,System Flash,Reserved,SRAM"
|
|
line.long 0x04 "SYSCFG_PMC,SYSCFG peripheral mode configuration register"
|
|
bitfld.long 0x04 0. " USB_PU ,USB pull-up enable on DP line" "No pull-up,Pull-up"
|
|
sif (cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L162VD")||cpuis("STM32L162ZD")||cpuis("STM32L162QD"))
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3 pin,PB3 pin,PC3 pin,PD3 pin,PE3 pin,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2 pin,PB2 pin,PC2 pin,PD2 pin,PE2 pin,PH2 pin,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1 pin,PB1 pin,PC1 pin,PD1 pin,PE1 pin,PH1 pin,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0 pin,PB0 pin,PC0 pin,PD0 pin,PE0 pin,PH0 pin,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7 pin,PB7 pin,PC7 pin,PD7 pin,PE7 pin,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6 pin,PB6 pin,PC6 pin,PD6 pin,PE6 pin,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5 pin,PB5 pin,PC5 pin,PD5 pin,PE5 pin,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4 pin,PB4 pin,PC4 pin,PD4 pin,PE4 pin,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11 pin,PB11 pin,PC11 pin,PD11 pin,PE11 pin,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10 pin,PB10 pin,PC10 pin,PD10 pin,PE10 pin,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9 pin,PB9 pin,PC9 pin,PD9 pin,PE9 pin,?..."
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8 pin,PB8 pin,PC8 pin,PD8 pin,PE8 pin,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15 pin,PB15 pin,PC15 pin,PD15 pin,PE15 pin,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14 pin,PB14 pin,PC14 pin,PD14 pin,PE14 pin,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13 pin,PB13 pin,PC13 pin,PD13 pin,PE13 pin,?..."
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12 pin,PB12 pin,PC12 pin,PD12 pin,PE12 pin,?..."
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L162RD"))
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3 pin,PB3 pin,PC3 pin,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2 pin,PB2 pin,PC2 pin,PD2 pin,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1 pin,PB1 pin,PC1 pin,Reserved,Reserved,PH1 pin,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0 pin,PB0 pin,PC0 pin,Reserved,Reserved,PH0 pin,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7 pin,PB7 pin,PC7 pin,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6 pin,PB6 pin,PC6 pin,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5 pin,PB5 pin,PC5 pin,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4 pin,PB4 pin,PC4 pin,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11 pin,PB11 pin,PC11 pin,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10 pin,PB10 pin,PC10 pin,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9 pin,PB9 pin,PC9 pin,?..."
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8 pin,PB8 pin,PC8 pin,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15 pin,PB15 pin,PC15 pin,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14 pin,PB14 pin,PC14 pin,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13 pin,PB13 pin,PC13 pin,?..."
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12 pin,PB12 pin,PC12 pin,?..."
|
|
else
|
|
line.long 0x08 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3 pin,PB3 pin,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2 pin,PB2 pin,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1 pin,PB1 pin,Reserved,Reserved,Reserved,PH1 pin,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0 pin,PB0 pin,Reserved,Reserved,Reserved,PH0 pin,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7 pin,PB7 pin,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6 pin,PB6 pin,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5 pin,PB5 pin,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4 pin,PB4 pin,?..."
|
|
line.long 0x10 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11 pin,PB11 pin,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10 pin,PB10 pin,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9 pin,PB9 pin,?..."
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8 pin,PB8 pin,?..."
|
|
line.long 0x14 "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15 pin,PB15 pin,PC15 pin,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14 pin,PB14 pin,PC14 pin,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13 pin,PB13 pin,PC13 pin,?..."
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12 pin,PB12 pin,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "EXTI (External interrupt/event controller)"
|
|
base ad:0x40010400
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "EXTI_IMR,EXTI Interrupt Mask Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 24. " MR24 , Interrupt mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 23. " MR23 , Interrupt mask on line 23" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " MR22 , Interrupt mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " MR21 , Interrupt mask on line 21" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x00 20. " MR20 , Interrupt mask on line 20" "Masked,Not masked"
|
|
bitfld.long 0x00 19. " MR19 , Interrupt mask on line 19" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " MR18 , Interrupt mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " MR17 , Interrupt mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " MR16 , Interrupt mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " MR15 , Interrupt mask on line 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MR14 , Interrupt mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " MR13 , Interrupt mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " MR12 , Interrupt mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " MR11 , Interrupt mask on line 11" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MR10 , Interrupt mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " MR9 , Interrupt mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " MR8 , Interrupt mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " MR7 , Interrupt mask on line 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MR6 , Interrupt mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " MR5 , Interrupt mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " MR4 , Interrupt mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " MR3 , Interrupt mask on line 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR2 , Interrupt mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR1 , Interrupt mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " MR0 , Interrupt mask on line 0" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_EMR,EXTI Event Mask Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 24. " MR24 , Event mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x04 23. " MR23 ,Event mask on line 23" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " MR22 ,Event mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " MR21 ,Event mask on line 21" "Masked,Not masked"
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 20. " MR20 ,Event mask on line 20" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MR19 ,Event mask on line 19" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 18. " MR18 ,Event mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " MR17 ,Event mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " MR16 ,Event mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x04 15. " MR15 ,Event mask on line 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " MR14 ,Event mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " MR13 ,Event mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " MR12 ,Event mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " MR11 ,Event mask on line 11" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MR10 ,Event mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " MR9 ,Event mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " MR8 ,Event mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " MR7 ,Event mask on line 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MR6 ,Event mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " MR5 ,Event mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MR4 ,Event mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " MR3 ,Event mask on line 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MR2 ,Event mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " MR1 ,Event mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MR0 ,Event mask on line 0" "Masked,Not masked"
|
|
line.long 0x08 "EXTI_RTSR,EXTI Rising Edge Trigger Selection Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x08 24. " MR24 , Interrupt mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x08 24. " TR24 ,Rising edge trigger event configuration bit of line 24" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " TR23 ,Rising edge trigger event configuration bit of line 23" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 22. " TR22 ,Rising edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TR21 ,Rising edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
elif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " TR19 ,Rising edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " TR18 ,Rising edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TR17 ,Rising edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " TR16 ,Rising edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " TR15 ,Rising edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " TR14 ,Rising edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " TR13 ,Rising edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " TR12 ,Rising edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TR11 ,Rising edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TR10 ,Rising edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TR9 ,Rising edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TR8 ,Rising edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TR7 ,Rising edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " TR6 ,Rising edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TR5 ,Rising edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TR4 ,Rising edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TR3 ,Rising edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TR2 ,Rising edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TR1 ,Rising edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR0 ,Rising edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR,Falling Edge Trigger Selection Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x0C 24. " TR24 ,Falling edge trigger event configuration bit of line 24" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x0C 23. " TR23 ,Falling edge trigger event configuration bit of line 23" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 22. " TR22 ,Falling edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TR21 ,Falling edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
elif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " TR19 ,Falling edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 18. " TR18 ,Falling edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " TR17 ,Falling edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " TR16 ,Falling edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " TR15 ,Falling edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " TR14 ,Falling edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " TR13 ,Falling edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TR12 ,Falling edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " TR11 ,Falling edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " TR10 ,Falling edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " TR9 ,Falling edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " TR8 ,Falling edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " TR7 ,Falling edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " TR6 ,Falling edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TR5 ,Falling edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TR4 ,Falling edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " TR3 ,Falling edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " TR2 ,Falling edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " TR1 ,Falling edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR0 ,Falling edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "EXTI_SWIER,EXTI Software Interrupt Event Register"
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x10 23. " SWIER23 ,Software interrupt on line 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 22. " SWIER22 ,Software interrupt on line 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " SWIER21 ,Software interrupt on line 21" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x10 20. " SWIER20 ,Software interrupt on line 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 19. " SWIER19 ,Software interrupt on line 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " SWIER18 ,Software interrupt on line 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " SWIER17 ,Software interrupt on line 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " SWIER16 ,Software interrupt on line 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 15. " SWIER15 ,Software interrupt on line 15" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SWIER14 ,Software interrupt on line 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " SWIER13 ,Software interrupt on line 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " SWIER12 ,Software interrupt on line 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 11. " SWIER11 ,Software interrupt on line 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 10. " SWIER10 ,Software interrupt on line 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " SWIER9 ,Software interrupt on line 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " SWIER8 ,Software interrupt on line 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 7. " SWIER7 ,Software interrupt on line 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 6. " SWIER6 ,Software interrupt on line 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " SWIER5 ,Software interrupt on line 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " SWIER4 ,Software interrupt on line 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 3. " SWIER3 ,Software interrupt on line 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SWIER2 ,Software interrupt on line 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " SWIER1 ,Software interrupt on line 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " SWIER0 ,Software interrupt on line 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "EXTI_PR,EXTI Pending Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 24. " PR24 ,Pending bit 24" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 23. " PR23 ,Pending bit 23" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " PR22 ,Pending bit 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " PR21 ,Pending bit 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " PR20 ,Pending bit 20" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " PR19 ,Pending bit 19" "Not pending,Pending"
|
|
textline " "
|
|
else
|
|
sif (cpuis("STM32F7*"))
|
|
eventfld.long 0x00 23. " PR23 ,Pending bit 23" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 22. " PR22 ,Pending bit 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " PR21 ,Pending bit 21" "Not pending,Pending"
|
|
textline " "
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
eventfld.long 0x00 20. " PR20 ,Pending bit 20" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " PR19 ,Pending bit 19" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
endif
|
|
eventfld.long 0x00 18. " PR18 ,Pending bit 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " PR17 ,Pending bit 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " PR16 ,Pending bit 16" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " PR15 ,Pending bit 15" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 14. " PR14 ,Pending bit 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " PR13 ,Pending bit 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " PR12 ,Pending bit 12" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " PR11 ,Pending bit 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " PR10 ,Pending bit 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " PR9 ,Pending bit 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " PR8 ,Pending bit 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " PR7 ,Pending bit 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " PR6 ,Peanding bit 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " PR5 ,Pending bit 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " PR4 ,Pending bit 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " PR3 ,Pending bit 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PR2 ,Pending bit 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " PR1 ,Pending bit 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " PR0 ,Pending bit 0" "Not pending,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "DMA (Direct memory access)"
|
|
tree "DMA 1"
|
|
base ad:0x40026000
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 27. " TEIF7 ,Channel 7 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 26. " HTIF7 ,Channel 7 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCIF7 ,Channel 7 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " GIF7 ,Channel 7 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEIF6 ,Channel 6 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 22. " HTIF6 ,Channel 6 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCIF6 ,Channel 6 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " GIF6 ,Channel 6 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA channel 6 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA channel 6 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA channel 7 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA channel 7 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
tree "DMA 2"
|
|
base ad:0x40026400
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "ADC (Analog/Digital Converter)"
|
|
base ad:0x40012400
|
|
width 11.
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
rbitfld.long 0x00 9. " JCNR ,Injected channel not ready" "Ready,Not ready"
|
|
rbitfld.long 0x00 8. " RCNR ,Regular channel not ready" "Ready,Not ready"
|
|
rbitfld.long 0x00 6. " ADONS ,ADC ON status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 9. " JCNR ,Injected channel not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 8. " RCNR ,Regular channel not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 6. " ADONS ,ADC ON status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
if (((per.l(ad:0x40012400+0x08))&0x05)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PDI ,Power down during the idle phase" "Powered up,Powered down"
|
|
bitfld.long 0x00 16. " PDD ,Power down during the delay phase" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0b,ADC_IN1b,ADC_IN2b,ADC_IN3b,,,ADC_IN6b,ADC_IN7b,ADC_IN8b,ADC_IN9b,ADC_IN10b,ADC_IN11b,ADC_12b,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L162VD-X")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L151CC")||cpuis("STM32L152CC")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0b,?..."
|
|
textline " "
|
|
endif
|
|
elif (((per.l(ad:0x40012400+0x08))&0x05)==0x05)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " PDI ,Power down during the idle phase" "Powered up,Powered down"
|
|
rbitfld.long 0x00 16. " PDD ,Power down during the delay phase" "Powered up,Powered down"
|
|
textline " "
|
|
rbitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
rbitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
rbitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0b,ADC_IN1b,ADC_IN2b,ADC_IN3b,,,ADC_IN6b,ADC_IN7b,ADC_IN8b,ADC_IN9b,ADC_IN10b,ADC_IN11b,ADC_12b,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L162VD-X")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L151CC")||cpuis("STM32L152CC")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0b,?..."
|
|
textline " "
|
|
endif
|
|
elif (((per.l(ad:0x40012400+0x08))&0x05)==0x01)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " PDI ,Power down during the idle phase" "Powered up,Powered down"
|
|
rbitfld.long 0x00 16. " PDD ,Power down during the delay phase" "Powered up,Powered down"
|
|
textline " "
|
|
rbitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
rbitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
rbitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,ADC_IN25,,ADC_IN27,ADC_IN28,ADC_IN29,ADC_IN30,ADC_IN31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,ADC_IN25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,,,,,,,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PDI ,Power down during the idle phase" "Powered up,Powered down"
|
|
bitfld.long 0x00 16. " PDD ,Power down during the delay phase" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,ADC_IN25,,ADC_IN27,ADC_IN28,ADC_IN29,ADC_IN30,ADC_IN31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,ADC_IN25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_15,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,,,,,,,,,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PDI ,Power down during the idle phase" "Powered up,Powered down"
|
|
bitfld.long 0x00 16. " PDD ,Power down during the delay phase" "Powered up,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L1??V?"))
|
|
sif (cpuis("STM32L15?VD")||cpuis("STM32L15?VC")||cpuis("STM32L162VD"))
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..."
|
|
textline " "
|
|
endif
|
|
elif (cpuis("STM32L1??R?"))
|
|
sif (cpuis("STM32L15?RC")||cpuis("STM32L15?RD")||cpuis("STM32L162RD"))
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..."
|
|
textline " "
|
|
endif
|
|
elif (cpuis("STM32L15??C?"))
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,ADC_IN24,ADC_IN25,ADC_IN26,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
if (((per.l(ad:0x40012400))&0x340)==0x340)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
rbitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x300)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x240)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
rbitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x200)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x140)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
rbitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x100)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x040)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
rbitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012400))&0x340)==0x000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM9_CC2,TIM9_TRGO,TIM2_CC3,TIM2_CC2,TIM3_TRGO,TIM4_CC4,TIM2_TRGO,TIM3_CC1,TIM3_CC3,TIM4_TRGO,TIM6_TRGO,,,,,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 22. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM9_CC1,TIM9_TRGO,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM10_CC1,TIM7_TRGO,,,,,EXTI15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " DELS ,Delay selection" "No delay,EoC,7APB after EoC,15APB after EoC,31APB after EoC,63APB after EoC,127APB after EoC,255APB after EoC"
|
|
bitfld.long 0x00 2. " ADC_CFG ,Selects the bank of channels to be converted" "Bank A,Bank B"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP29 ,Channel 29 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP28 ,Channel 28 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 21.--23. " SMP27 ,Channel 27 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP25 ,Channel 25 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 12.--14. " SMP24 ,Channel 24 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP23 ,Channel 23 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " SMP22 ,Channel 22 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP29 ,Channel 29 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP28 ,Channel 28 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 21.--23. " SMP27 ,Channel 27 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP25 ,Channel 25 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 12.--14. " SMP24 ,Channel 24 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP23 ,Channel 23 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " SMP22 ,Channel 22 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 15.--17. " SMP25 ,Channel 25 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 12.--14. " SMP24 ,Channel 24 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP23 ,Channel 23 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " SMP22 ,Channel 22 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 15.--17. " SMP25 ,Channel 25 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 12.--14. " SMP24 ,Channel 24 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP23 ,Channel 23 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " SMP22 ,Channel 22 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
elif (!cpuis("STM32L15?C?")&&!cpuis("STM32L15?R6")&&!cpuis("STM32L15?R8")&&!cpuis("STM32L15?RB"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
sif (cpuis("STM32L15?QC")||cpuis("STM32L15?ZC")||cpuis("STM32L15?QD")||cpuis("STM32L15?ZD")||cpu()=="STM32L162QD"||cpu()=="STM32L162ZD")
|
|
bitfld.long 0x00 27.--29. " SMP29 ,Channel 29 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP28 ,Channel 28 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 21.--23. " SMP27 ,Channel 27 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP26 ,Channel 26 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 15.--17. " SMP25 ,Channel 25 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L15?VC")||cpuis("STM32L15?VD")||cpu()=="STM32L162VC")
|
|
bitfld.long 0x00 12.--14. " SMP24 ,Channel 24 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32L15?V?")||cpu()=="STM32L162VC"||cpu()=="STM32L162VD")
|
|
bitfld.long 0x00 9.--11. " SMP23 ,Channel 23 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 6.--8. " SMP22 ,Channel 22 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP21 ,Channel 21 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--2. " SMP20 ,Channel 20 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
endif
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP19 ,Channel 19 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
line.long 0x04 "ADC_SMPR3,ADC sample time register 3"
|
|
bitfld.long 0x04 27.--29. " SMP9 ,Channel 9 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 24.--26. " SMP8 ,Channel 8 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 21.--23. " SMP7 ,Channel 7 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMP6 ,Channel 6 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 15.--17. " SMP5 ,Channel 5 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 12.--14. " SMP4 ,Channel 4 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " SMP3 ,Channel 3 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 6.--8. " SMP2 ,Channel 2 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 3.--5. " SMP1 ,Channel 1 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SMP0 ,Channel 0 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
else
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP19 ,Channel 19 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
line.long 0x04 "ADC_SMPR3,ADC sample time register 3"
|
|
bitfld.long 0x04 27.--29. " SMP9 ,Channel 9 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 24.--26. " SMP8 ,Channel 8 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 21.--23. " SMP7 ,Channel 7 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMP6 ,Channel 6 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 15.--17. " SMP5 ,Channel 5 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 12.--14. " SMP4 ,Channel 4 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " SMP3 ,Channel 3 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 6.--8. " SMP2 ,Channel 2 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 3.--5. " SMP1 ,Channel 1 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SMP0 ,Channel 0 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP19 ,Channel 19 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
line.long 0x04 "ADC_SMPR3,ADC sample time register 3"
|
|
bitfld.long 0x04 27.--29. " SMP9 ,Channel 9 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 24.--26. " SMP8 ,Channel 8 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 21.--23. " SMP7 ,Channel 7 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMP6 ,Channel 6 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 15.--17. " SMP5 ,Channel 5 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 12.--14. " SMP4 ,Channel 4 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " SMP3 ,Channel 3 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 6.--8. " SMP2 ,Channel 2 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 3.--5. " SMP1 ,Channel 1 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SMP0 ,Channel 0 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
else
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP19 ,Channel 19 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
line.long 0x04 "ADC_SMPR3,ADC sample time register 3"
|
|
bitfld.long 0x04 27.--29. " SMP9 ,Channel 9 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 24.--26. " SMP8 ,Channel 8 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 21.--23. " SMP7 ,Channel 7 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMP6 ,Channel 6 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 15.--17. " SMP5 ,Channel 5 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 12.--14. " SMP4 ,Channel 4 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " SMP3 ,Channel 3 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 6.--8. " SMP2 ,Channel 2 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 3.--5. " SMP1 ,Channel 1 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SMP0 ,Channel 0 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
endif
|
|
else
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
sif (!cpuis("STM32L15?C?"))
|
|
bitfld.long 0x00 27.--29. " SMP19 ,Channel 19 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
line.long 0x04 "ADC_SMPR3,ADC sample time register 3"
|
|
bitfld.long 0x04 27.--29. " SMP9 ,Channel 9 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 24.--26. " SMP8 ,Channel 8 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 21.--23. " SMP7 ,Channel 7 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " SMP6 ,Channel 6 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 15.--17. " SMP5 ,Channel 5 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 12.--14. " SMP4 ,Channel 4 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " SMP3 ,Channel 3 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 6.--8. " SMP2 ,Channel 2 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x04 3.--5. " SMP1 ,Channel 1 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SMP0 ,Channel 0 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x0 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x0 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x4 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0x8 "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0xC "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x10 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x10 0.--11. 1. " HT ,Analog watchdog high threshold"
|
|
line.long 0x14 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " LT ,Analog watchdog low threshold"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "ADC_SQR1,ADC regular sequence register 1"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x00 20.--24. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
bitfld.long 0x00 15.--19. " SQ28 ,28th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L100RC")
|
|
bitfld.long 0x00 20.--24. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
bitfld.long 0x00 15.--19. " SQ28 ,28th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--24. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x00 10.--14. " SQ27 ,27th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " SQ26 ,26th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " SQ25 ,25th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x00 10.--14. " SQ27 ,27th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x00 5.--9. " SQ26 ,26th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x00 0.--4. " SQ25 ,25th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 10.--14. " SQ27 ,27th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x00 5.--9. " SQ26 ,26th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x00 0.--4. " SQ25 ,25th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x00 10.--14. " SQ27 ,27th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x00 5.--9. " SQ26 ,26th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x00 0.--4. " SQ25 ,25th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
line.long 0x04 "ADC_SQR2,ADC regular sequence register 2"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x04 25.--29. " SQ24 ,24th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x04 20.--24. " SQ23 ,23th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x04 15.--19. " SQ22 ,22th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " SQ21 ,21th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x04 5.--9. " SQ20 ,20th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " SQ19 ,19th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x04 25.--29. " SQ24 ,24th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x04 20.--24. " SQ23 ,23th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x04 15.--19. " SQ22 ,22th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " SQ21 ,21th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x04 5.--9. " SQ20 ,20th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x04 0.--4. " SQ19 ,19th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x04 25.--29. " SQ24 ,24th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 20.--24. " SQ23 ,23th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 15.--19. " SQ22 ,22th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " SQ21 ,21th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 5.--9. " SQ20 ,20th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 0.--4. " SQ19 ,19th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x04 25.--29. " SQ24 ,24th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 20.--24. " SQ23 ,23th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 15.--19. " SQ22 ,22th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " SQ21 ,21th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 5.--9. " SQ20 ,20th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x04 0.--4. " SQ19 ,19th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
line.long 0x08 "ADC_SQR3,ADC regular sequence register 3"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x08 25.--29. " SQ18 ,18th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x08 20.--24. " SQ17 ,17th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x08 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x08 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x08 25.--29. " SQ18 ,18th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x08 20.--24. " SQ17 ,17th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x08 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x08 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x08 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x08 25.--29. " SQ18 ,18th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 20.--24. " SQ17 ,17th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x08 25.--29. " SQ18 ,18th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 20.--24. " SQ17 ,17th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x08 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
line.long 0x0C "ADC_SQR4,ADC regular sequence register 4"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x0C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x0C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x0C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x0C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x0C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x0C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x0C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x0C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x0C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x0C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x0C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
line.long 0x10 "ADC_SQR5,ADC regular sequence register 5"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x10 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x10 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x10 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x10 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x10 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x10 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x10 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
bitfld.long 0x10 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x10 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x10 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x10 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x10 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x10 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x10 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x10 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
line.long 0x14 "ADC_JSQR,ADC injected sequence register"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
bitfld.long 0x14 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x14 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x14 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
bitfld.long 0x14 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,,27,28,29,30,31"
|
|
textline " "
|
|
elif cpuis("STM32L151VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L162VC")||cpuis("STM32L151VC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L151VE")||cpuis("STM32L152VE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VC-A")||cpuis("STM32L162VE")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")
|
|
bitfld.long 0x14 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x14 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x14 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
bitfld.long 0x14 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,22,23,24,25,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RE")||cpuis("STM32L151RC-A")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L151RE")||cpuis("STM32L152RE")||cpuis("STM32L151UC")||cpuis("STM32L162RC")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100RC")
|
|
bitfld.long 0x14 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x14 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x14 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
bitfld.long 0x14 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,,18,19,20,21,?..."
|
|
textline " "
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L152CC")||cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L100C6-A")||cpuis("STM32L100C6")
|
|
bitfld.long 0x14 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x14 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x14 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
bitfld.long 0x14 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,,,18,19,20,21,?..."
|
|
endif
|
|
else
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "ADC_SQR1,ADC regular sequence register 1"
|
|
sif cpuis("STM32L151?D")||cpuis("STM32L152?D")||cpuis("STM32L162?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L15??C-A")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x00 20.--24. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,?..."
|
|
bitfld.long 0x00 15.--19. " SQ28 ,28th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20.--24. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10.--14. " SQ27 ,27th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x00 5.--9. " SQ26 ,26th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x00 0.--4. " SQ25 ,25th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x04 "ADC_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 25.--29. " SQ24 ,24th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x04 20.--24. " SQ23 ,23th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x04 15.--19. " SQ22 ,22th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " SQ21 ,21th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x04 5.--9. " SQ20 ,20th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x04 0.--4. " SQ19 ,19th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x08 "ADC_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 25.--29. " SQ18 ,18th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x08 20.--24. " SQ17 ,17th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x08 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x08 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x08 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x0C "ADC_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x0C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x0C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x0C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x10 "ADC_SQR5,ADC regular sequence register 5"
|
|
bitfld.long 0x10 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x10 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x10 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
textline " "
|
|
bitfld.long 0x10 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x10 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
bitfld.long 0x10 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,?..."
|
|
line.long 0x14 "ADC_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x14 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x14 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x14 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x14 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x14 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
rgroup.long 0x48++0xF
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x00 "ADC_DR,ADC regular data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L152QE")||cpuis("STM32L162ZE")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ADC_SMPR0,ADC sample time register 0"
|
|
bitfld.long 0x00 3.--5. " SMP31 ,Channel 31 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
bitfld.long 0x00 0.--2. " SMP30 ,Channel 30 Sample time selection" "4,9,16,24,48,96,192,384"
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x00 "ADC_CSR,ADC common status register"
|
|
bitfld.long 0x00 6. " ADONS1 ,ADON Status" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " OVR1 ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT1 ,Regular channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 3. " JSTRT1 ,Injected channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC1 ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC1 ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD1 ,Analog watchdog flag" "Not occurred,Occurred"
|
|
else
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x00 "ADC_CSR,ADC common status register"
|
|
bitfld.long 0x00 7. " ADONS1 ,ADON Status" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " OVR1 ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT1 ,Regular channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 3. " JSTRT1 ,Injected channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC1 ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC1 ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD1 ,Analog watchdog flag" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x304++0x3
|
|
line.long 0x00 "ADC_CCR,ADC common control register"
|
|
bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and Vrefint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "HSI,HSI/2,HSI/4,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 9 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 9 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 9 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 9 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,DAC channel2 software trigger" "Disable,Enable"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel1 software trigger" "Disable,Enable"
|
|
group.long 0x8++0x23
|
|
line.long 0x00 "DAC_DHR12R1,DAC channel1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC_DHR12L1,DAC channel1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit Left aligned data"
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit Right aligned data"
|
|
line.long 0x0c "DAC_DHR12R2,DAC channel2 12-bit Right aligned Data Holding Register"
|
|
hexmask.long.word 0x0c 0.--11. 1. " DACC2DHR ,DAC channel2 12-bit Right aligned data"
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DACC2DHR ,DAC channel2 12-bit Left aligned data"
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit Right-aligned Data Holding Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DACC2DHR ,DAC channel2 8-bit Right aligned data"
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DACC2DHR ,DAC channel2 12-bit Right aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit Right aligned data"
|
|
line.long 0x1c "DAC_DHR12LD,DUAL DAC 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x1c 20.--31. 1. " DACC2DHR ,DAC channel2 12-bit Left aligned data"
|
|
hexmask.long.word 0x1c 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit Left aligned data"
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DACC2DHR ,DAC channel2 8-bit Right aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC_DOR1,DAC channel1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel1 data output"
|
|
line.long 0x04 "DAC_DOR2,DAC channel2 Data Output Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,DAC channel2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,DAC channel2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "COMP (Comparators)"
|
|
base ad:0x40007C00
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "COMP_CSR,COMP comparator control and status register"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.long 0x00 31. " TSUSP ,Suspend Timer Mode" "Enabled,Not used"
|
|
bitfld.long 0x00 30. " CAIF ,Channel acquisition interrupt flag" "Ongoing or not started,Completed"
|
|
bitfld.long 0x00 29. " CAIE ,Channel Acquisition Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FCH8 ,Select GPIO port PB0 by the ADC interface" "Slow,Fast"
|
|
bitfld.long 0x00 26. " FCH3 ,Select GPIO port PA3 by the ADC interface" "Slow,Fast"
|
|
textline " "
|
|
elif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x00 31. " TSUSP ,Suspend Timer Mode" "Enabled,Not used"
|
|
bitfld.long 0x00 30. " CAIF ,Channel acquisition interrupt flag" "Ongoing or not started,Completed"
|
|
bitfld.long 0x00 29. " CAIE ,Channel Acquisition Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RCH13 ,Select GPIO port PC3 by the ADC interface" "Slow,Re-routed"
|
|
bitfld.long 0x00 27. " FCH8 ,Select GPIO port PB0 by the ADC interface" "Slow,Fast"
|
|
bitfld.long 0x00 26. " FCH3 ,Select GPIO port PA3 by the ADC interface" "Slow,Fast"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--23. " OUTSEL ,Comparator 2 output selection" "TIM2 IC 4,TIM2 OCREF_CLR,TIM3 IC 4,TIM3 OCREF_CLR,TIM4 IC 4,TIM4 OCREF_CLR,TIM10 IC 1,No effect"
|
|
bitfld.long 0x00 18.--20. " INSEL ,Inverted input selection" "No effect,PB3,V_refint,3/4 V_refint,1/2 V_refint,1/4 V_refint,DAC_OUT1,DAC_OUT2"
|
|
bitfld.long 0x00 17. " WNDWE ,Window mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VREFOUTEN ,Vrefint output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CMP2OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 12. " SPEED ,Comparator 2 speed mode" "Slow,Fast"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
bitfld.long 0x00 7. " CMP1OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 4. " CMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif ((cpuis("STM32L151?D"))||(cpuis("STM32L152?D"))||(cpuis("STM32L162?D"))||(cpuis("STM32L151?C"))||(cpuis("STM32L152?C")))
|
|
bitfld.long 0x00 7. " CMP1OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 5. " SW1 ,SW1 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 4. " CMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " CMP1OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 4. " CMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " 400KPD ,400 kohm pull-down resistor" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " 10KPD ,10 kohm pull-down resistor" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " 400KPU ,400 kohm pull-up resistor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " 10KPU ,10 kohm pull-up resistor" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
tree "OPAMP (Operational amplifiers)"
|
|
base ad:0x40007C5C
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "OPAMP_CSR,OPAMP control/status register"
|
|
rbitfld.long 0x00 30. " OPA2CALOUT ,OPAMP3 calibration output" "Low,High"
|
|
rbitfld.long 0x00 29. " OPA1CALOUT ,OPAMP1 calibration output" "Low,High"
|
|
bitfld.long 0x00 28. " OPA_RANGE ,Power range selection" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S7SEL2 ,Switch 7 for OPAMP2 enable" "Opened,Closed"
|
|
bitfld.long 0x00 25. " ANASWEL2 ,Switch SanA enable for OPAMP2" "Opened,Closed"
|
|
bitfld.long 0x00 24. " ANASWEL1 ,Switch SanA enable for OPAMP1" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OPA2LPM ,OPAMP2 low power mode" "Off,On"
|
|
bitfld.long 0x00 14. " OPA2CAL_H , OPAMP2 offset calibration for N differential pair" "Off,On"
|
|
bitfld.long 0x00 13. " OPA2CAL_L ,OPAMP2 offset Calibration for P differential pair" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S6SEL2 ,Switch 6 for OPAMP 2 enable" "Opened,Closed"
|
|
bitfld.long 0x00 11. " S5SEL2 ,Switch 5 for OPAMP 2 enable" "Opened,Closed"
|
|
bitfld.long 0x00 10. " S4SEL2 ,Switch 4 for OPAMP 2 enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " S3SEL2 ,Switch 3 for OPAMP 2 enable" "Opened,Closed"
|
|
bitfld.long 0x00 8. " OPA2PD ,OPAMP2 power down" "No,Yes"
|
|
bitfld.long 0x00 7. " OPA1LPM ,OPAMP1 low power mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OPA1CAL_H ,OPAMP1 offset calibration for N differential pair" "Off,On"
|
|
bitfld.long 0x00 5. " OPA1CAL_L ,OPAMP1 offset calibration for P differential pair" "Off,On"
|
|
bitfld.long 0x00 4. " S6SEL1 ,Switch 6 for OPAMP1 enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S5SEL1 ,Switch 5 for OPAMP1 enable" "Opened,Closed"
|
|
bitfld.long 0x00 2. " S4SEL1 ,Switch 4 for OPAMP1 enable" "Opened,Closed"
|
|
bitfld.long 0x00 1. " S3SEL1 ,Switch 3 for OPAMP1 enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPA1PD ,OPAMP1 power down" "No,Yes"
|
|
line.long 0x04 "OPAMP_OTR,OPAMP offset trimming register for normal mode"
|
|
bitfld.long 0x04 31. " OT_USER ,Select user or factory trimming value" "Default,User"
|
|
textline " "
|
|
bitfld.long 0x04 25.--29. " OA3_OPT_OFFSET_TRIM_HIGH ,OPAMP3 normal mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 20.--24. " OA3_OPT_OFFSET_TRIM_LOW ,OPAMP3 normal mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 15.--19. " OA2_OPT_OFFSET_TRIM_HIGH ,OPAMP2 normal mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 10.--14. " OA2_OPT_OFFSET_TRIM_LOW ,OPAMP2 normal mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 5.--9. " OA1_OPT_OFFSET_TRIM_HIGH ,OPAMP1 normal mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " OA1_OPT_OFFSET_TRIM_LOW ,OPAMP1 normal mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "OPAMP_LPOTR,OPAMP offset trimming register for low power mode"
|
|
bitfld.long 0x08 25.--29. " OA3_OPT_OFFSET_TRIM_LP_HIGH ,OPAMP3 low power mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 20.--24. " OA3_OPT_OFFSET_TRIM_LP_LOW ,OPAMP3 low power mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 15.--19. " OA2_OPT_OFFSET_TRIM_LP_HIGH ,OPAMP2 low power mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 10.--14. " OA2_OPT_OFFSET_TRIM_LP_LOW ,OPAMP2 low power mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 5.--9. " OA1_OPT_OFFSET_TRIM_LP_HIGH ,OPAMP1 low power mode 5-bit offset trim value for NMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " OA1_OPT_OFFSET_TRIM_LP_LOW ,OPAMP1 low power mode 5-bit offset trim value for PMOS pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree "LCD"
|
|
base ad:0x40002400
|
|
width 9.
|
|
if (((d.l((ad:0x40002400+0x08)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LCD_CR,LCD control register"
|
|
sif cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152CC")
|
|
bitfld.long 0x00 5.--6. " BIAS ,Bias selector" "Bias/4,Bias/2,Bias/3,"
|
|
bitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External"
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " MUX_SEG ,Mux segment enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " BIAS ,Bias selector" "Bias/4,Bias/2,Bias/3,"
|
|
bitfld.long 0x00 2.--4. " DUTY ,Duty selection" "Static,Duty/2,Duty/3,Duty/4,Duty/8,,,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External"
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LCD_CR,LCD control register"
|
|
sif cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152CC")
|
|
rbitfld.long 0x00 5.--6. " BIAS ,Bias selector" "Bias/4,Bias/2,Bias/3,"
|
|
rbitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External"
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 7. " MUX_SEG ,Mux segment enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " BIAS ,Bias selector" "Bias/4,Bias/2,Bias/3,"
|
|
rbitfld.long 0x00 2.--4. " DUTY ,Duty selection" "Static,Duty/2,Duty/3,Duty/4,Duty/8,,,"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External"
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LCD_FCR,LCD frame control register"
|
|
bitfld.long 0x00 22.--25. " PS ,PS 16-bit prescaler" "LCDCLK,LCDCLK/2,LCDCLK/4,LCDCLK/8,LCDCLK/16,LCDCLK/32,LCDCLK/64,LCDCLK/128,LCDCLK/256,LCDCLK/512,LCDCLK/1024,LCDCLK/2048,LCDCLK/4096,LCDCLK/8192,LCDCLK/16384,LCDCLK/32768"
|
|
bitfld.long 0x00 18.--21. " DIV ,DIV clock divider" "ck_ps/16,ck_ps/17,ck_ps/18,ck_ps/19,ck_ps/20,ck_ps/21,ck_ps/22,ck_ps/23,ck_ps/24,ck_ps/25,ck_ps/26,ck_ps/27,ck_ps/28,ck_ps/29,ck_ps/30,ck_ps/31"
|
|
bitfld.long 0x00 16.--17. " BLINK ,Blink mode selection" "Disabled,SEG[0]/COM[0],SEG[0]/all COMs,All SEGs/COMs"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " BLINKF ,Blink frequency selection" "Flcd/8,Flcd/16,Flcd/32,Flcd/64,Flcd/128,Flcd/256,Flcd/512,Flcd/1024"
|
|
bitfld.long 0x00 10.--12. " CC ,Contrast control" "VLCD0,VLCD1,VLCD2,VLCD3,VLCD4,VLCD5,VLCD6,VLCD7"
|
|
bitfld.long 0x00 7.--9. " DEAD ,Dead time duration" "No dead time,1 phase,2 phase,3 phase,4 phase,5 phase,6 phase,7 phase"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PON ,Pulse ON duration" "0,1/ck_ps,2/ck_ps,3/ck_ps,4/ck_ps,5/ck_ps,6/ck_ps,7/ck_ps"
|
|
bitfld.long 0x00 3. " UDDIE ,Update display done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFIE ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HD ,High drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "LCD_SR,LCD status register"
|
|
bitfld.long 0x00 5. " FCRSF ,LCD Frame Control Register Synchronization flag" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 4. " RDY ,Ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 3. " UDD ,Update Display Done" "No event,Done"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UDR ,Update display request" "No effect,Requested"
|
|
bitfld.long 0x00 1. " SOF ,Start of frame flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ENS ,LCD enabled status" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "LCD_CLR,LCD clear register"
|
|
bitfld.long 0x00 3. " UDDC ,Update display done clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " SOFC ,Start of frame flag clear" "No effect,Clear"
|
|
sif cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152CC")||cpuis("STM32L100C6")||cpuis("STM32L100C6-A")
|
|
group.long 0x14++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
sif cpuis("STM32L152CC")
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
elif cpuis("STM32L100C6")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x1C++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
sif cpuis("STM32L152CC")
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
elif cpuis("STM32L100C6")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x24++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
sif cpuis("STM32L152CC")
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
elif cpuis("STM32L100C6")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x2C++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
sif cpuis("STM32L152CC")
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
elif cpuis("STM32L100C6")||cpuis("STM32L100C6-A")
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
elif cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L162RC")||cpuis("STM32L152RE")||cpuis("STM32L152RC-A")||cpuis("STM32L162RC-A")||cpuis("STM32L162RE")||cpuis("STM32L100RC")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x14++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x1C++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x24++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x2C++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x34++0x3 "COM4"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM4"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x3C++0x3 "COM5"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM5"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x44++0x3 "COM6"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM6"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x4C++0x3 "COM7"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM7"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
else
|
|
group.long 0x14++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x14+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x1C++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x1C+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x24++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x24+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x2C++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x34++0x3 "COM4"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM4"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x34+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM4"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x3C++0x3 "COM5"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM5"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x3C+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM5"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x44++0x3 "COM6"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM6"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x44+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM6"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x4C++0x3 "COM7"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM7"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long (0x4C+0x04)++0x3
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM7"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32L152*")||cpuis("STM32L162?D"))
|
|
tree "LCD"
|
|
base ad:0x40002400
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "LCD_CR,LCD control register"
|
|
bitfld.long 0x00 7. " MUX_SEG ,Mux segment enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " BIAS ,Bias selector" "Bias/4,Bias/2,Bias/3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " DUTY ,Duty selection" "Static,Duty/2,Duty/3,Duty/4,Duty/8,?..."
|
|
bitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
line.long 0x04 "LCD_FCR,LCD frame control register"
|
|
bitfld.long 0x04 22.--25. " PS ,PS 16-bit prescaler" "LCDCLK,LCDCLK/2,LCDCLK/4,LCDCLK/8,LCDCLK/16,LCDCLK/32,LCDCLK/64,LCDCLK/128,LCDCLK/256,LCDCLK/512,LCDCLK/1024,LCDCLK/2048,LCDCLK/4096,LCDCLK/8192,LCDCLK/16384,LCDCLK/65536"
|
|
bitfld.long 0x04 18.--21. " DIV ,DIV clock divider" "ck_ps/16,ck_ps/17,ck_ps/18,ck_ps/19,ck_ps/20,ck_ps/21,ck_ps/22,ck_ps/23,ck_ps/24,ck_ps/25,ck_ps/26,ck_ps/27,ck_ps/28,ck_ps/29,ck_ps/30,ck_ps/31"
|
|
bitfld.long 0x04 16.--17. " BLINK ,Blink mode selection" "Disabled,SEG[0]/COM[0],SEG[0]/all COMs,All SEGs/COMs"
|
|
textline " "
|
|
bitfld.long 0x04 13.--15. " BLINKF ,Blink frequency selection" "Flcd/8,Flcd/16,Flcd/32,Flcd/64,Flcd/128,Flcd/256,Flcd/512,Flcd/1024"
|
|
bitfld.long 0x04 10.--12. " CC ,Contrast control" "2.6V,2.7V,2.8V,2.9V,3V,3.1V,3.2V,3.3V"
|
|
bitfld.long 0x04 7.--9. " DEAD ,Dead time duration" "No dead time,1 phase,2 phase,3 phase,4 phase,5 phase,6 phase,7 phase"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " PON ,Pulse ON duration" "0us,244us,488us,782us,976us,1.22ms,1.46ms,1.71ms"
|
|
bitfld.long 0x04 3. " UDDIE ,Update display done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SOFIE ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HD ,High drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "LCD_SR,LCD status register"
|
|
bitfld.long 0x00 5. " FCRSF ,LCD Frame Control Register Synchronization flag" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 4. " RDY ,Ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 3. " UDD ,Update Display Done" "No event,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UDR ,Update display request" "No effect,Enable"
|
|
bitfld.long 0x00 1. " SOF ,Start of frame flag" "No event,Interrupt"
|
|
bitfld.long 0x00 0. " ENS ,LCD enabled status" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "LCD_CLR,LCD clear register"
|
|
bitfld.long 0x00 3. " UDDC ,Update display done clear" "No effect,UDD flag cleared"
|
|
bitfld.long 0x00 1. " SOFC ,Start of frame flag clear" "No effect,SOF flag cleared"
|
|
width 11.
|
|
tree "LCD RAM (Display memory)"
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
group.long 0x14++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM0 (lower pixels)"
|
|
sif (cpuis("STM32L15*R*")||cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM0 (higher pixels)"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x1C++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM1 (lower pixels)"
|
|
sif (cpuis("STM32L15*R*")||cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM1 (higher pixels)"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x24++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM2 (lower pixels)"
|
|
sif (cpuis("STM32L15*R*")||cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM2 (higher pixels)"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x2C++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM3 (lower pixels)"
|
|
sif (cpuis("STM32L15*R*")||cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM3 (higher pixels)"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
sif (cpuis("STM32L15*R*")||cpuis("STM32L15*V*"))
|
|
if ((per.l(ad:0x40002400)&0x10)==0x10)
|
|
group.long 0x34++0x3 "COM4"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM4 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM4 (higher pixels)"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x3C++0x3 "COM5"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM5 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM5 (higher pixels)"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x44++0x3 "COM6"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM6 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM6 (higher pixels)"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
group.long 0x4C++0x3 "COM7"
|
|
line.long 0x00 "LCD_RAM_L,LCD display memory for COM7 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
sif (cpuis("STM32L15*V*"))
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "LCD_RAM_H,LCD display memory for COM7 (higher pixels)"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
else
|
|
hgroup.long 0x34++0x3 "COM4"
|
|
hide.long 0x00 "LCD_RAM_L,LCD display memory for COM4 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "LCD_RAM_H,LCD display memory for COM4 (higher pixels)"
|
|
endif
|
|
hgroup.long 0x3C++0x3 "COM5"
|
|
hide.long 0x00 "LCD_RAM_L,LCD display memory for COM5 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "LCD_RAM_H,LCD display memory for COM5 (higher pixels)"
|
|
endif
|
|
hgroup.long 0x44++0x3 "COM6"
|
|
hide.long 0x00 "LCD_RAM_L,LCD display memory for COM6 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "LCD_RAM_H,LCD display memory for COM6 (higher pixels)"
|
|
endif
|
|
hgroup.long 0x4C++0x3 "COM7"
|
|
hide.long 0x00 "LCD_RAM_L,LCD display memory for COM7 (lower pixels)"
|
|
sif (cpuis("STM32L15*V*"))
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "LCD_RAM_H,LCD display memory for COM7 (higher pixels)"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
group.long 0x14++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x18++0x3 "COM0"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM0"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x1C++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x20++0x3 "COM1"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM1"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x24++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x28++0x3 "COM2"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM2"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x2C++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x30++0x3 "COM3"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM3"
|
|
bitfld.long 0x00 11. " S43 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S42 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S41 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S40 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x34++0x3 "COM4"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM4"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x38++0x3 "COM4"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM4"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x3C++0x3 "COM5"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM5"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x40++0x3 "COM5"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM5"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x44++0x3 "COM6"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM6"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x48++0x3 "COM6"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM6"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
group.long 0x4C++0x3 "COM7"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM7"
|
|
bitfld.long 0x00 31. " S31 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 30. " S30 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 29. " S29 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 28. " S28 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " S27 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 26. " S26 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 25. " S25 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 24. " S24 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " S23 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 22. " S22 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 21. " S21 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 20. " S20 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S19 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 18. " S18 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 17. " S17 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 16. " S16 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S15 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 14. " S14 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 13. " S13 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 12. " S12 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " S11 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 10. " S10 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 9. " S9 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 8. " S8 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S7 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S6 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S5 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S4 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S3 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S2 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S1 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S0 ,Segment data" "Inactive,Active"
|
|
group.long 0x50++0x3 "COM7"
|
|
line.long 0x00 "LCD_RAM,LCD display memory for COM7"
|
|
bitfld.long 0x00 7. " S39 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 6. " S38 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 5. " S37 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 4. " S36 ,Segment data" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " S35 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 2. " S34 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S33 ,Segment data" "Inactive,Active"
|
|
bitfld.long 0x00 0. " S32 ,Segment data" "Inactive,Active"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree.open "General-purpose timers"
|
|
tree "TIM 2"
|
|
base ad:0x40000000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,TIM2 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,TIM2 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC2,Update"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,TIM2 Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,TIM2 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,TIM2 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,TIM2 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((d.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000000+0x18)))&0x003)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((d.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000000+0x1C)))&0x003)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
if ((((d.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000000+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM2_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM2_DMAR,DMA address for full transfer"
|
|
if cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 0. " ITR1_RMP ,Timer 2 Internal trigger 1 remap" "TIM2 ITR1 input connected to TIM10 OC,TIM2 ITR1 input connected to TIM5 TGO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 3"
|
|
base ad:0x40000400
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,TIM3 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC3,Update"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,TIM3 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,TIM3 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((d.w((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000400+0x18)))&0x003)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000400+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((d.w((ad:0x40000400+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000400+0x1C)))&0x003)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000400+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
if ((((d.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000400+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM3_DMAR,DMA address for full transfer"
|
|
if cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM3_OR,TIM3 option register"
|
|
bitfld.word 0x00 0. " ITR2_RMP ,Timer 3 Internal trigger 2 remap" "TIM3 ITR2 input connected to TIM11 OC,TIM3 ITR2 input connected to TIM5 TGO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 4"
|
|
base ad:0x40000800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,TIM4 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,TIM4 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC4,Update"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,TIM4 Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,TIM4 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,TIM4 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,TIM4 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((d.w((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000800+0x18)))&0x003)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((d.w((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000800+0x1C)))&0x003)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
if ((((d.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000800+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM4_DMAR,DMA address for full transfer"
|
|
if cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 5"
|
|
base ad:0x40000C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,TIM5 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM5_CR2,TIM5 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC5,Update"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,TIM5 Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM5_DIER,TIM5 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM5_SR,TIM5 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM5_EGR,TIM5 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((d.w((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000C00+0x18)))&0x003)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40000C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((d.w((ad:0x40000C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000C00+0x1C)))&0x003)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Disbled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((d.w((ad:0x40000C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Disbled,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
if ((((d.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x003)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((d.w((ad:0x40000C00+0x18)))&0x003)==0x000)&&(((d.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM5_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TIM5_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIM5_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM5_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM5_DMAR,DMA address for full transfer"
|
|
if cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 9"
|
|
base ad:0x40010800
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM9_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32L15??6-A")&&!cpuis("STM32L15??8-A")&&!cpuis("STM32L15??B-A")&&!cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")&&!cpuis("STM32L100C6-A")&&!cpuis("STM32L100R8-A")||!cpuis("STM32L100RB-A")
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM9_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM9_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM9_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x40010800+0x18)))&0x303)==0x000)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 Interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update Interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation" "No action,Compare"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Compare"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x003)==0x000)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 Interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update Interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation" "No action,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Compare"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x300)==0x000)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 0. " UIF ,Update Interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation" "No action,Compare"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 Interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation" "No action,Capture"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
endif
|
|
if (((d.w((ad:0x40010800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x003)==0x000)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Enabled"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Enabled"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((d.w((ad:0x40010800+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((d.w((ad:0x40010800+0x18)))&0x300)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM9_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM9_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM9_ARR,Auto-reload register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM9_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM9_CCR2,Capture/compare register 2"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM9_OR,TIM9 option register 1"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 10"
|
|
base ad:0x40010C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM10_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM10_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM10_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x40010C00+0x18)))&0x03)==0x00)
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM10_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM10_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Compare"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
else
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM10_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM10_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
endif
|
|
if (((d.w((ad:0x40010C00+0x18)))&0x03)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,,"
|
|
endif
|
|
if (((d.w((ad:0x40010C00+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM10_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM10_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM10_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM10_CCR1,Capture/compare register 1"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM10_OR,TIM10 option register 1"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer10 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer10 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 Input 1 remapping capability" "TIM10CH1->GPIO,LSI->TIM10CH1,LSE->TIM10CH1,RTC->TIM10CH1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 11"
|
|
base ad:0x40011000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM11_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM11_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM11_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x40011000+0x18)))&0x03)==0x00)
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM11_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 Interrupt Flag" "No match,Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM11_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Compare"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
else
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM11_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag" "No input,Captured"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM11_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation" "No action,Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generate"
|
|
endif
|
|
if (((d.w((ad:0x40011000+0x18)))&0x03)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,,"
|
|
endif
|
|
if (((d.w((ad:0x40011000+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM11_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM11_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM11_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM11_CCR1,Capture/compare register 1"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer11 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer11 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,MSI->TIM11CH1,HSE_RTC->TIM9CH1,TIM11CH1->GPIO"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Basic Timers"
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM6_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM6_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM6_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM6_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM7_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM7_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM7_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001400)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM7_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "General-purpose timers"
|
|
tree "TIM 2"
|
|
base ad:0x40000000
|
|
width 12.
|
|
if (((per.l(ad:0x40000000))&0x60)!=0x00)||(((per.l(ad:0x40000000+0x08))&0x03)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,TIM2 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,TIM2 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,TIM2 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC2,Update"
|
|
if (((per.w(ad:0x40000000+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,TIM2 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,TIM2 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,TIM2 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,TIM2 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,TIM2 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000000+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000000+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
if (((per.l(ad:0x40000000+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)!=0x0)
|
|
if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif (cpuis("STM32F4*"))
|
|
if ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F2*")||cpuis("STM32F4*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Low counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM2_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value"
|
|
line.long 0x08 "TIM2_CCR3,Capture/compare register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value"
|
|
hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value"
|
|
line.long 0x0C "TIM2_CCR4,Capture/compare register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM2_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
endif
|
|
textline " "
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for full transfer"
|
|
textline ""
|
|
sif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input"
|
|
textline " "
|
|
elif (cpuis("STM32F401*")||cpuis("STM32F411*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" ",PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input"
|
|
textline " "
|
|
elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input"
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input"
|
|
else
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input"
|
|
endif
|
|
textline " "
|
|
elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 0. " TR1_RMP ,Timer 2 Internal trigger 1 remap" "TIM2 ITR1 input is connected to TIM10 OC,TIM2 ITR1 input is connected to TIM5 TGO"
|
|
textline " "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 3"
|
|
base ad:0x40000400
|
|
width 12.
|
|
if (((per.l(ad:0x40000400))&0x60)!=0x00)||(((per.l(ad:0x40000400+0x08))&0x03)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,TIM3 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC3,Update"
|
|
if (((per.w(ad:0x40000400+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,TIM3 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,TIM3 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000400+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000400+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x300)==0x000)
|
|
if (((per.l(ad:0x40000400+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000400+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)!=0x0)
|
|
if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif (cpuis("STM32F4*"))
|
|
if ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F2*")||cpuis("STM32F4*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM3_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0x34++0xF
|
|
line.long 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM3_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value"
|
|
line.long 0x08 "TIM3_CCR3,Capture/compare register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR3 ,Low Capture/Compare 3 value"
|
|
line.long 0x0C "TIM3_CCR4,Capture/compare register 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR4 ,Low Capture/Compare 4 value"
|
|
else
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM3_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
endif
|
|
textline " "
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for full transfer"
|
|
textline ""
|
|
sif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM3_OR,TIM3 option register"
|
|
elif (cpuis("STM32F401*")||cpuis("STM32F411*"))
|
|
elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*"))
|
|
elif (cpuis("STM32F4*"))
|
|
elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM3_OR,TIM3 option register"
|
|
bitfld.word 0x00 0. " TR1_RMP ,Timer 2 Internal trigger 1 remap" "TIM3 ITR2 input is connected to TIM11 OC,TIM3 ITR2 input is connected to TIM5 TGO"
|
|
textline " "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 4"
|
|
base ad:0x40000800
|
|
width 12.
|
|
if (((per.l(ad:0x40000800))&0x60)!=0x00)||(((per.l(ad:0x40000800+0x08))&0x03)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,TIM4 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,TIM4 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,TIM4 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC4,Update"
|
|
if (((per.w(ad:0x40000800+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,TIM4 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,TIM4 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,TIM4 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,TIM4 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,TIM4 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
if (((per.l(ad:0x40000800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)!=0x0)
|
|
if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif (cpuis("STM32F4*"))
|
|
if ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F2*")||cpuis("STM32F4*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM4_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0x34++0xF
|
|
line.long 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM4_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value"
|
|
line.long 0x08 "TIM4_CCR3,Capture/compare register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR3 ,Low Capture/Compare 3 value"
|
|
line.long 0x0C "TIM4_CCR4,Capture/compare register 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR4 ,Low Capture/Compare 4 value"
|
|
else
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM4_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
endif
|
|
textline " "
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for full transfer"
|
|
textline ""
|
|
sif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM4_OR,TIM4 option register"
|
|
elif (cpuis("STM32F401*")||cpuis("STM32F411*"))
|
|
elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*"))
|
|
elif (cpuis("STM32F4*"))
|
|
elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
tree "TIM 5"
|
|
base ad:0x40000C00
|
|
width 12.
|
|
if (((per.l(ad:0x40000C00))&0x60)!=0x00)||(((per.l(ad:0x40000C00+0x08))&0x03)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,TIM5 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,TIM5 control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM5_CR2,TIM5 Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC5,Update"
|
|
if (((per.w(ad:0x40000C00+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,TIM5 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,TIM5 Slave mode control register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
else
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*"))
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM5_DIER,TIM5 DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM5_SR,TIM5 Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM5_EGR,TIM5 Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
sif !cpuis("STM32F410*")
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)!=0x0)
|
|
if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
else
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif (cpuis("STM32F4*"))
|
|
if ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F2*")||cpuis("STM32F4*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM5_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Low counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM5_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value"
|
|
line.long 0x04 "TIM5_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value"
|
|
line.long 0x08 "TIM5_CCR3,Capture/compare register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value"
|
|
hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value"
|
|
line.long 0x0C "TIM5_CCR4,Capture/compare register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM5_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
endif
|
|
textline " "
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM5_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM5_DMAR,DMA address for full transfer"
|
|
textline ""
|
|
sif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM5_OR,TIM5 option register"
|
|
bitfld.word 0x00 6.--7. " ITR1_RMP ,Internal trigger 1 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input"
|
|
textline " "
|
|
elif (cpuis("STM32F401*")||cpuis("STM32F411*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM5_OR,TIM5 option register"
|
|
bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input"
|
|
textline " "
|
|
elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM5_OR,TIM5 option register"
|
|
bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input"
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
group.word 0x50++0x3
|
|
line.word 0x00 "TIM5_OR,TIM5 option register"
|
|
bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input"
|
|
textline " "
|
|
elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "TIM 9"
|
|
base ad:0x40010800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM9_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
sif !cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM9_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
endif
|
|
if (((per.l(ad:0x40010800+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM9_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM9_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM9_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40010800+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40010800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40010800+0x18)))&0x300)!=0x0)&&(((per.w((ad:0x40010800+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40010800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40010800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010800+0x18)))&0x03)!=0x00)
|
|
if (((per.l(ad:0x40010800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40010800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40010800+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40010800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010800+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40010800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010800+0x18)))&0x3)!=0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM9_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM9_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM9_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM9_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM9_CCR2,Capture/compare register 2"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM9_OR,TIM9 option register 1"
|
|
bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 10"
|
|
base ad:0x40010C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM10_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM10_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM10_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM10_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM10_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM10_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM10_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40010C00+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40010C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40010C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40010C00+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM10_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM10_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM10_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM10_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM10_OR,TIM10 option register 1"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer10 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer10 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 Input 1 remapping capability" "TIM10CH1->GPIO,LSE EC->TIM10CH1,LSE EC->TIM10CH1,RTC OE->TIM10CH1"
|
|
elif (cpuis("STM32F2*"))
|
|
elif (cpuis("STM32F4*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 11"
|
|
base ad:0x40011000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM11_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM11_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM11_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM11_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM11_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM11_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM11_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40011000+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40011000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40011000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40011000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM11_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM11_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM11_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM11_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer11 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer11 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,MSI IC->TIM11CH1,HSE EC->TIM9CH1,TIM11CH1->GPIO"
|
|
elif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE IC->TIM11CH1,TIM11CH1->GPIO"
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE RTC->TIM11CH1,TIM11CH1->GPIO"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "Basic Timers"
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM6_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM6_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM6_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM6_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM7_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM7_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM7_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001400)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM7_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
width 14.
|
|
if (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800)&0x300000)!=0x200000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800)&0x300000)==0x200000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x40)&&((d.l(ad:0x40002800)&0x300000)==0x100000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
if (((d.l(ad:0x40002800+0x04)&0x30)==0x30)&&((d.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0x40002800+0x04)&0x30)==0x30)&&((d.l(ad:0x40002800+0x04)&0x1000)==0x0000))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((d.l(ad:0x40002800+0x04)&0x30)!=0x30)&&((d.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x08++0xF
|
|
line.long 0x00 "RTC_CR,RTC control register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarb B,Enabled"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Enable"
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enable"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DCE ,Digital calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hours,AM/PM"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "From shadow registers,From the calendar counters"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " REFCKON ,Reference clock detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,Ck_spre,Ck_spre,Ck_spre/WUT+=0x10000,Ck_spre/WUT+=0x10000"
|
|
line.long 0x04 "RTC_ISR,RTC initialization and status register"
|
|
rbitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 15. " TAMP3F ,RTC_TAMP3 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "Not overflow,Overf"
|
|
bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WUTF ,Wakeup timer flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ALRBF ,Aladam B flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ALRAF ,Alarm A flag enable" "Diasbled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
rbitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
rbitfld.long 0x04 3. " SHPF ,Shift operation pending " "Not pending,Pending"
|
|
rbitfld.long 0x04 2. " WUTWF ,Wakeup timer write flag" "Not allowed,Allowed"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed"
|
|
rbitfld.long 0x04 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed"
|
|
line.long 0x08 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x08 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
line.long 0xC "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0xC 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
if ((d.l((ad:0x40002800)+0x18)&0x80)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RTC_CALIBR,RTC calibration register"
|
|
bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative"
|
|
bitfld.long 0x00 0.--4. " DC ,Digital calibration" "+0 ppm,+4 ppm,+8 ppm,+12 ppm,+16 ppm,+20 ppm,+24 ppm,+28 ppm,+33 ppm,+37 ppm,+41 ppm,+45 ppm,+49 ppm,+53 ppm,+57 ppm,+61 ppm,+65 ppm,+69 ppm,+73 ppm,+77 ppm,+81 ppm,+85 ppm,+90 ppm,+94 ppm,+98 ppm,+102 ppm,+106 ppm,+110 ppm,+114 ppm,+118 ppm,+122 ppm,+126 ppm"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RTC_CALIBR,RTC calibration register"
|
|
bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative"
|
|
bitfld.long 0x00 0.--4. " DC ,Digital calibration" "-0 ppm,-2 ppm,-4 ppm,-6 ppm,-8 ppm,-10 ppm,-12 ppm,-14 ppm,-16 ppm,-18 ppm,-20 ppm,-22 ppm,-24 ppm,-26 ppm,-28 ppm,-31 ppm,-33 ppm,-35 ppm,-37 ppm,-39 ppm,-41 ppm,-43 ppm,-45 ppm,-47 ppm,-49 ppm,-51 ppm,-53 ppm,-55 ppm,-57 ppm,-59 ppm,-61 ppm,-63 ppm"
|
|
endif
|
|
if (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800+0x1C)&0x300000)!=0x200000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800+0x1C)&0x300000)==0x200000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x40)&&((d.l(ad:0x40002800+0x1C)&0x300000)==0x100000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
if (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800+0x20)&0x300000)!=0x200000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x00)&&((d.l(ad:0x40002800+0x20)&0x300000)==0x200000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((d.l(ad:0x40002800+0x8)&0x40)==0x40)&&((d.l(ad:0x40002800+0x20)&0x300000)==0x100000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key"
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
endif
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x00 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Add"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second"
|
|
endif
|
|
if ((d.l((ad:0x40002800)+0x0C)&0x800)==0x0)
|
|
hgroup.long 0x30++0x7
|
|
hide.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
hide.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
elif (((d.l((ad:0x40002800)+0xC)&0x800)==0x800)&&((d.l(ad:0x40002800+0x8)&0x40)==0x0))
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
if ((d.l((ad:0x40002800)+0xC)&0x800)==0x800)
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
else
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
endif
|
|
endif
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No RTCCLK,One RTCCLK"
|
|
bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CALW16 ,Use a 16-second calibration cycle period" "Not used,Used"
|
|
hexmask.long.word 0x00 0.--8. 1. " CALM[8:0] ,Calibration minus"
|
|
endif
|
|
if ((d.l((ad:0x40002800)+0x40)&0x1800)==0x0000)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,TAMPFREQ Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "No save,Save"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 5. " TAMP3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for tamper 2" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 3. " TAMP2E ,Tamper 2 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "No save,Save"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Low,High"
|
|
bitfld.long 0x00 5. " TAMP3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for tamper 2" "Low,High"
|
|
bitfld.long 0x00 3. " TAMP2E ,Tamper 2 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32L100C6")&&!cpuis("STM32L100R8")&&!cpuis("STM32L100RB")
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS[3:0] ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS[14:0] ,Sub seconds value"
|
|
line.long 0x04 "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
bitfld.long 0x04 24.--27. " MASKSS[3:0] ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x04 0.--14. 1. " SS[14:0] ,Sub seconds value"
|
|
endif
|
|
tree "RTC backup registers"
|
|
sif cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTC_BKP0R,RTC backup register 0"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RTC_BKP1R,RTC backup register 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RTC_BKP2R,RTC backup register 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "RTC_BKP3R,RTC backup register 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RTC_BKP4R,RTC backup register 4"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RTC_BKP5R,RTC backup register 5"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RTC_BKP6R,RTC backup register 6"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RTC_BKP7R,RTC backup register 7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "RTC_BKP8R,RTC backup register 8"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "RTC_BKP9R,RTC backup register 9"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "RTC_BKP10R,RTC backup register 10"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "RTC_BKP11R,RTC backup register 11"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RTC_BKP12R,RTC backup register 12"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RTC_BKP13R,RTC backup register 13"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTC_BKP14R,RTC backup register 14"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RTC_BKP15R,RTC backup register 15"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RTC_BKP16R,RTC backup register 16"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RTC_BKP17R,RTC backup register 17"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RTC_BKP18R,RTC backup register 18"
|
|
elif cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTC_BKP0R,RTC backup register 0"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RTC_BKP1R,RTC backup register 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RTC_BKP2R,RTC backup register 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "RTC_BKP3R,RTC backup register 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RTC_BKP4R,RTC backup register 4"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RTC_BKP5R,RTC backup register 5"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RTC_BKP6R,RTC backup register 6"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RTC_BKP7R,RTC backup register 7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "RTC_BKP8R,RTC backup register 8"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "RTC_BKP9R,RTC backup register 9"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "RTC_BKP10R,RTC backup register 10"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "RTC_BKP11R,RTC backup register 11"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RTC_BKP12R,RTC backup register 12"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RTC_BKP13R,RTC backup register 13"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTC_BKP14R,RTC backup register 14"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RTC_BKP15R,RTC backup register 15"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RTC_BKP16R,RTC backup register 16"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RTC_BKP17R,RTC backup register 17"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RTC_BKP18R,RTC backup register 18"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "RTC_BKP19R,RTC backup register 19"
|
|
elif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTC_BKP0R,RTC backup register 0"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RTC_BKP1R,RTC backup register 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RTC_BKP2R,RTC backup register 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "RTC_BKP3R,RTC backup register 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RTC_BKP4R,RTC backup register 4"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RTC_BKP5R,RTC backup register 5"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RTC_BKP6R,RTC backup register 6"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "RTC_BKP7R,RTC backup register 7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "RTC_BKP8R,RTC backup register 8"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "RTC_BKP9R,RTC backup register 9"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "RTC_BKP10R,RTC backup register 10"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "RTC_BKP11R,RTC backup register 11"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RTC_BKP12R,RTC backup register 12"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RTC_BKP13R,RTC backup register 13"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTC_BKP14R,RTC backup register 14"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RTC_BKP15R,RTC backup register 15"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RTC_BKP16R,RTC backup register 16"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RTC_BKP17R,RTC backup register 17"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RTC_BKP18R,RTC backup register 18"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "RTC_BKP19R,RTC backup register 19"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RTC_BKP20R,RTC backup register 20"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RTC_BKP21R,RTC backup register 21"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RTC_BKP22R,RTC backup register 22"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "RTC_BKP23R,RTC backup register 23"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "RTC_BKP24R,RTC backup register 24"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "RTC_BKP25R,RTC backup register 25"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "RTC_BKP26R,RTC backup register 26"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "RTC_BKP27R,RTC backup register 27"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RTC_BKP28R,RTC backup register 28"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "RTC_BKP29R,RTC backup register 29"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "RTC_BKP30R,RTC backup register 30"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "RTC_BKP31R,RTC backup register 31"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTC_BKP0R,RTC backup register 0"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RTC_BKP1R,RTC backup register 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RTC_BKP2R,RTC backup register 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "RTC_BKP3R,RTC backup register 3"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
width 12.
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)!=0x200000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)==0x200000))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
elif ((per.l(ad:0x40002800)&0x300000)==0x100000)
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. ":,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. ":,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x0))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. ":,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. ":,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
elif (((per.l(ad:0x40002800+0x04)&0x30)!=0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12. ":,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. ":,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12. ":,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. ":,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
group.long 0x08++0xF
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
line.long 0x00 "RTC_CR,RTC control register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Enabled"
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hours,AM/PM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "From shadow registers,From the calendar counters"
|
|
bitfld.long 0x00 4. " REFCKON ,Reference clock detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
line.long 0x04 "RTC_ISR,RTC initialization and status register"
|
|
bitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 15. " TAMP3F ,RTC_TAMP3 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 8. " ALRAF ,Alarm A flag enable" "Diasbled,Enabled"
|
|
bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
bitfld.long 0x04 3. " SHPF ,Shift operation pending " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed"
|
|
else
|
|
line.long 0x00 "RTC_CR,RTC control register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DCE ,Digital calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hours,AM/PM"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REFCKON ,Reference clock detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,Ck_spre,Ck_spre,Ck_spre/WUT+=0x10000,Ck_spre/WUT+=0x10000"
|
|
line.long 0x04 "RTC_ISR,RTC initialization and status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 15. " TAMP3F ,TAMPER2 Tamper detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 14. " TAMP2F ,TAMPER2 Tamper detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 13. " TAMP1F ,Tamper detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " WUTF ,Wakeup timer flag enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ALRBF ,Aladam B flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ALRAF ,Alarm A flag enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
bitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
bitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WUTWF ,Wakeup timer write flag" "Not allowed,Allowed"
|
|
bitfld.long 0x04 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed"
|
|
endif
|
|
line.long 0x08 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x08 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
hexmask.long.word 0x08 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x08 0.--12. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
endif
|
|
sif (CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8"&&CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6")
|
|
line.long 0xC "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0xC 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
if ((per.l((ad:0x40002800)+0x18)&0x80)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RTC_CALIBR,RTC calibration register"
|
|
bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative"
|
|
bitfld.long 0x00 0.--4. " DC ,Digital calibration" "+0 ppm,+4 ppm,+8 ppm,+12 ppm,+16 ppm,+20 ppm,+24 ppm,+28 ppm,+32 ppm,+36 ppm,+40 ppm,+44 ppm,+48 ppm,+52 ppm,+56 ppm,+60 ppm,+64 ppm,+68 ppm,+72 ppm,+76 ppm,+80 ppm,+84 ppm,+88 ppm,+92 ppm,+96 ppm,+100 ppm,+104 ppm,+108 ppm,+112 ppm,+116 ppm,+120 ppm,+126 ppm"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "RTC_CALIBR,RTC calibration register"
|
|
bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative"
|
|
bitfld.long 0x00 0.--4. " DC ,Digital calibration" "-0 ppm,-2 ppm,-4 ppm,-6 ppm,-8 ppm,-10 ppm,-12 ppm,-14 ppm,-16 ppm,-18 ppm,-20 ppm,-22 ppm,-24 ppm,-26 ppm,-28 ppm,-30 ppm,-32 ppm,-34 ppm,-36 ppm,-38 ppm,-40 ppm,-42 ppm,-44 ppm,-46 ppm,-48 ppm,-50 ppm,-52 ppm,-54 ppm,-56 ppm,-58 ppm,-60 ppm,-63 ppm"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000))
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000))
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000))
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
sif (CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8"&&CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6")
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000))
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline ""
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "DU,DU/WD"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x00 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.byte 0x00 0.--15. 1. " SS ,Sub second value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Add one second to the clock/calendar"
|
|
hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second"
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.byte 0x00 0.--15. 1. " SS ,Sub second value"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x00 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Add one second to the clock/calendar"
|
|
hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second"
|
|
endif
|
|
if ((per.l((ad:0x40002800)+0x0C)&0x800)==0x0)
|
|
hgroup.long 0x30++0x7
|
|
hide.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
hide.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
elif (((per.l((ad:0x40002800)+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x0))
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
else
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "Forbidden,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
endif
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
if ((per.l((ad:0x40002800)+0xC)&0x800)==0x800)
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long 0x00 0.--15. 1. " SS ,Sub second value"
|
|
else
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
endif
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No RTCCLK,One RTCCLK"
|
|
bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CALW16 ,Use a 16-second calibration cycle period" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--8. 1. " CALM[8:0] ,Calibration minus"
|
|
endif
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
if ((per.l((ad:0x40002800)+0x10)&0x800)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
textline " "
|
|
sif (!cpuis("STM32L151?6")||(!cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH[1:0] ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
bitfld.long 0x00 11.--12. " AMPFLT[1:0] ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ[2:0] ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 5. " TAMPI3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32L151?6")&&(!cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for tamper 2" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 3. " TAMPI2E ,Tamper 2 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
textline " "
|
|
sif (!cpuis("STM32L151?6")&&(!cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH[1:0] ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
bitfld.long 0x00 11.--12. " AMPFLT[1:0] ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ[2:0] ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMPI3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for tamper 2" "Rising edge,Falling edge"
|
|
textline " "
|
|
sif (!cpuis("STM32L151?6")&&(!cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 3. " TAMPI2E ,Tamper 2 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
if ((per.l((ad:0x40002800)+0x08)&0x800)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH[1:0] ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " AMPFLT[1:0] ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ[2:0] ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384 ,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512 ,RTCCLK/256 "
|
|
textline " "
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMPI3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low/Rising edge,High/Falling edge"
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH[1:0] ,Tamper precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " AMPFLT[1:0] ,Tamper filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ[2:0] ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384 ,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512 ,RTCCLK/256 "
|
|
textline " "
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for tamper 3" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 5. " TAMPI3E ,Tamper 3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low/Rising edge,High/Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
sif (cpuis("STM32F2*"))
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 17. " TSINSEL ,TIMESTAMP mapping" "RTC_AF1 TIMESTAMP,RTC_AF2 TIMESTAMP"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TAMP1INSEL ,TAMPER1 mapping" "RTC_AF1 TAMPER,RTC_AF2 TAMPER"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Tamper 1 detection trigger" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0. " TAMP1E ,Tamper 1 detection enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS[3:0] ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS[14:0] ,Sub seconds value"
|
|
sif (CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8"&&CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6")
|
|
line.long 0x04 "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
bitfld.long 0x04 24.--27. " MASKSS[3:0] ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x04 0.--14. 1. " SS[14:0] ,Sub seconds value"
|
|
endif
|
|
endif
|
|
width 12.
|
|
base (ad:0x40002800+0x50)
|
|
tree "RTC backup registers"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
group.long 0x00++0x7F
|
|
line.long 0x0 "RTC_BKP0R,RTC backup register 0"
|
|
line.long 0x4 "RTC_BKP1R,RTC backup register 1"
|
|
line.long 0x8 "RTC_BKP2R,RTC backup register 2"
|
|
line.long 0xC "RTC_BKP3R,RTC backup register 3"
|
|
line.long 0x10 "RTC_BKP4R,RTC backup register 4"
|
|
line.long 0x14 "RTC_BKP5R,RTC backup register 5"
|
|
line.long 0x18 "RTC_BKP6R,RTC backup register 6"
|
|
line.long 0x1C "RTC_BKP7R,RTC backup register 7"
|
|
line.long 0x20 "RTC_BKP8R,RTC backup register 8"
|
|
line.long 0x24 "RTC_BKP9R,RTC backup register 9"
|
|
line.long 0x28 "RTC_BKP10R,RTC backup register 10"
|
|
line.long 0x2C "RTC_BKP11R,RTC backup register 11"
|
|
line.long 0x30 "RTC_BKP12R,RTC backup register 12"
|
|
line.long 0x34 "RTC_BKP13R,RTC backup register 13"
|
|
line.long 0x38 "RTC_BKP14R,RTC backup register 14"
|
|
line.long 0x3C "RTC_BKP15R,RTC backup register 15"
|
|
line.long 0x40 "RTC_BKP16R,RTC backup register 16"
|
|
line.long 0x44 "RTC_BKP17R,RTC backup register 17"
|
|
line.long 0x48 "RTC_BKP18R,RTC backup register 18"
|
|
line.long 0x4C "RTC_BKP19R,RTC backup register 19"
|
|
line.long 0x50 "RTC_BKP20R,RTC backup register 20"
|
|
line.long 0x54 "RTC_BKP21R,RTC backup register 21"
|
|
line.long 0x58 "RTC_BKP22R,RTC backup register 22"
|
|
line.long 0x5C "RTC_BKP23R,RTC backup register 23"
|
|
line.long 0x60 "RTC_BKP24R,RTC backup register 24"
|
|
line.long 0x64 "RTC_BKP25R,RTC backup register 25"
|
|
line.long 0x68 "RTC_BKP26R,RTC backup register 26"
|
|
line.long 0x6C "RTC_BKP27R,RTC backup register 27"
|
|
line.long 0x70 "RTC_BKP28R,RTC backup register 28"
|
|
line.long 0x74 "RTC_BKP29R,RTC backup register 29"
|
|
line.long 0x78 "RTC_BKP30R,RTC backup register 30"
|
|
line.long 0x7C "RTC_BKP31R,RTC backup register 31"
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "RTC_BKP0R,RTC backup register 0"
|
|
line.long 0x4 "RTC_BKP1R,RTC backup register 1"
|
|
line.long 0x8 "RTC_BKP2R,RTC backup register 2"
|
|
line.long 0xC "RTC_BKP3R,RTC backup register 3"
|
|
line.long 0x10 "RTC_BKP4R,RTC backup register 4"
|
|
else
|
|
group.long 0x00++0x4F
|
|
line.long 0x0 "RTC_BKP0R,RTC backup register 0"
|
|
line.long 0x4 "RTC_BKP1R,RTC backup register 1"
|
|
line.long 0x8 "RTC_BKP2R,RTC backup register 2"
|
|
line.long 0xC "RTC_BKP3R,RTC backup register 3"
|
|
line.long 0x10 "RTC_BKP4R,RTC backup register 4"
|
|
line.long 0x14 "RTC_BKP5R,RTC backup register 5"
|
|
line.long 0x18 "RTC_BKP6R,RTC backup register 6"
|
|
line.long 0x1C "RTC_BKP7R,RTC backup register 7"
|
|
line.long 0x20 "RTC_BKP8R,RTC backup register 8"
|
|
line.long 0x24 "RTC_BKP9R,RTC backup register 9"
|
|
line.long 0x28 "RTC_BKP10R,RTC backup register 10"
|
|
line.long 0x2C "RTC_BKP11R,RTC backup register 11"
|
|
line.long 0x30 "RTC_BKP12R,RTC backup register 12"
|
|
line.long 0x34 "RTC_BKP13R,RTC backup register 13"
|
|
line.long 0x38 "RTC_BKP14R,RTC backup register 14"
|
|
line.long 0x3C "RTC_BKP15R,RTC backup register 15"
|
|
line.long 0x40 "RTC_BKP16R,RTC backup register 16"
|
|
line.long 0x44 "RTC_BKP17R,RTC backup register 17"
|
|
line.long 0x48 "RTC_BKP18R,RTC backup register 18"
|
|
line.long 0x4C "RTC_BKP19R,RTC backup register 19"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "IWDG_KR,Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "IWDG_PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "IWDG_RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "IWDG_SR,Status Register"
|
|
sif ((cpu()=="STM32F050C4")||(cpu()=="STM32F050C6")||(cpu()=="STM32F050K4")||(cpu()=="STM32F050K6")||(cpu()=="STM32F051C4")||(cpu()=="STM32F051C6")||(cpu()=="STM32F051C8")||(cpu()=="STM32F051K4")||(cpu()=="STM32F051K6")||(cpu()=="STM32F051K8")||(cpu()=="STM32F051R4")||(cpu()=="STM32F051R6")||(cpu()=="STM32F051R8")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IWDG_WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WWDG (Window Watchdog)"
|
|
base ad:0x40002C00
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "WWDG_CR,Control Register"
|
|
bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter"
|
|
line.long 0x04 "WWDG_CFR,Configuration Register"
|
|
bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value"
|
|
line.long 0x08 "WWDG_SR,Status Register"
|
|
bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32L162*"))
|
|
tree "AES (Advanced Encryption Standard Hardware Accelerator)"
|
|
base ad:0x50060000
|
|
width 14.
|
|
if (((per.l(ad:0x50060000))&0x60)==0x40)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES control register"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " CCFC ,Computation Complete Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CHMOD[1:0] ,AES chaining mode" "EBC,CBC,CTR,?..."
|
|
bitfld.long 0x00 3.--4. " MODE[1:0] ,AES operating mode" "Encryption,Key derivation,Decryption,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DATATYPE[1:0] ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES control register"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " CCFC ,Computation Complete Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CHMOD[1:0] ,AES chaining mode" "EBC,CBC,CTR,?..."
|
|
bitfld.long 0x00 3.--4. " MODE[1:0] ,AES operating mode" "Encryption,Key derivation,Decryption,Key derivation + decryption"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DATATYPE[1:0] ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "AES_SR,AES status register"
|
|
bitfld.long 0x00 2. " WRERR , Write error flag" "No error,Error"
|
|
bitfld.long 0x00 1. " RDERR ,Read error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCF ,Computation complete flag" "Completed,Not completed"
|
|
if (((per.l((ad:0x50060000)))&0x18)==0x8)
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "AES_DINR,AES data input register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "AES_DOUTR,AES data output register"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "AES_DINR,AES data input register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "AES_DOUTR,AES data output register"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "AES_DOUTR,AES data output register"
|
|
group.long 0x10++0x0F
|
|
line.long 0x0 "AES_KEYR0,AES key register 0"
|
|
line.long 0x4 "AES_KEYR1,AES key register 1"
|
|
line.long 0x8 "AES_KEYR2,AES key register 2"
|
|
line.long 0xC "AES_KEYR3,AES key register 3"
|
|
group.long 0x20++0x0F
|
|
line.long 0x0 "AES_IVR0,AES initialization vector register 0"
|
|
line.long 0x4 "AES_IVR1,AES initialization vector register 1"
|
|
line.long 0x8 "AES_IVR2,AES initialization vector register 2"
|
|
line.long 0xC "AES_IVR3,AES initialization vector register 3"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "USB (USB Full Speed Device)"
|
|
base ad:0x40005C00
|
|
width 12.
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "USB_CNTR,USB control register"
|
|
bitfld.long 0x00 15. " CTRM ,Correct Transfer Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PMAOVRM ,Packet Memory Area Over / Underrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERRM ,Error Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WKUPM ,Wake-up Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSPM ,Suspend mode Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RESETM ,USB Reset Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SOFM ,Start Of Frame Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ESOFM ,Expected Start Of Frame Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Resume"
|
|
bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Enter"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Enter"
|
|
bitfld.long 0x00 1. " PDWN ,Power down" "Exit,Enter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRES ,Force USB Reset" "Clear,Reset"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
line.long 0x04 "USB_ISTR,USB interrupt status register"
|
|
rbitfld.long 0x04 15. " CTR ,Correct Transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet Memory Area Over / Underrun" "No Over/Underrun,Over/Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wake up" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Normal,Suspend"
|
|
bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SOF ,Start Of Frame" "No effect,Packet arrives"
|
|
bitfld.long 0x04 8. " ESOF ,Expected Start Of Frame" "No effect,Packet expected"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT"
|
|
rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
line.long 0x04 "USB_ISTR,USB interrupt status register"
|
|
bitfld.long 0x04 15. " CTR ,Correct Transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet Memory Area Over / Underrun" "No Over/Underrun,Over/Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wake up" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Normal,Suspend"
|
|
bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SOF ,Start Of Frame" "No effect,Packet arrives"
|
|
bitfld.long 0x04 8. " ESOF ,Expected Start Of Frame" "No effect,Packet expected"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT"
|
|
bitfld.long 0x04 0.--3. " EP_ID ,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x48++0x13
|
|
line.long 0x00 "USB_FNR,USB frame number register"
|
|
bitfld.long 0x00 15. " RXDP ,Receive Data + Line Status" "No data,Data"
|
|
bitfld.long 0x00 14. " RXDM ,Receive Data - Line Status" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked"
|
|
bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FN ,Frame Number"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "USB_DADDR,USB device address"
|
|
bitfld.long 0x00 7. " EF ,Enable Function" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ADD ,Device Address"
|
|
line.long 0x04 "USB_BTABLE,Buffer table address"
|
|
hexmask.long.word 0x04 3.--15. 0x8 " BTABLE ,Buffer Table"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "USB_EP0R,USB endpoint 0 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "USB_EP1R,USB endpoint 1 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "USB_EP2R,USB endpoint 2 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "USB_EP3R,USB endpoint 3 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_EP4R,USB endpoint 4 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_EP5R,USB endpoint 5 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_EP6R,USB endpoint 6 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "USB_EP7R,USB endpoint 7 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 14.
|
|
base ad:((per.l((ad:0x40005C00+0x50))&0xFFF8))+ad:0x40005C00
|
|
tree "Buffer descriptor table"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
if ((per.l((ad:0x40005C00)+0x0)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x0)&0x300)==0x000)
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "USB_ADDR0_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT0_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR0_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT0_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "USB_ADDR0_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT0_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR0_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT0_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x4)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x4)&0x300)==0x000)
|
|
group.long 0x4++0x0F
|
|
line.long 0x00 "USB_ADDR1_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT1_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR1_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT1_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x4++0x0F
|
|
line.long 0x00 "USB_ADDR1_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT1_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR1_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT1_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x8)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x8)&0x300)==0x000)
|
|
group.long 0x8++0x0F
|
|
line.long 0x00 "USB_ADDR2_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT2_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR2_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT2_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x8++0x0F
|
|
line.long 0x00 "USB_ADDR2_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT2_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR2_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT2_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0xC)&0x600)==0x400)||((per.l((ad:0x40005C00)+0xC)&0x300)==0x000)
|
|
group.long 0xC++0x0F
|
|
line.long 0x00 "USB_ADDR3_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT3_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR3_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT3_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0xC++0x0F
|
|
line.long 0x00 "USB_ADDR3_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT3_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR3_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT3_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x10)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x10)&0x300)==0x000)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "USB_ADDR4_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT4_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR4_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT4_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "USB_ADDR4_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT4_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR4_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT4_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x14)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x14)&0x300)==0x000)
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "USB_ADDR5_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT5_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR5_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT5_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "USB_ADDR5_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT5_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR5_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT5_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x18)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x18)&0x300)==0x000)
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "USB_ADDR6_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT6_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR6_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT6_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "USB_ADDR6_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT6_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR6_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT6_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x1C)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x1C)&0x300)==0x000)
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "USB_ADDR7_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT7_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR7_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT7_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "USB_ADDR7_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT7_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR7_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT7_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "USB_ADDR_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")||cpuis("STM32F103TB"))
|
|
line.long 0x04 "USB_COUNT_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
else
|
|
line.long 0x04 "USB_COUNT_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
endif
|
|
line.long 0x08 "USB_ADDR_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")||cpuis("STM32F103TB"))
|
|
line.long 0x0C "USB_COUNT_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
else
|
|
line.long 0x0C "USB_COUNT_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32L162ZD")||cpuis("STM32L162QD")||cpuis("STM32L162VD")||cpuis("STM32L151VD")||cpuis("STM32L152VD")||cpuis("STM32L151ZD")||cpuis("STM32L152ZD")||cpuis("STM32L151QD")||cpuis("STM32L152QD"))
|
|
tree "FSMC (Flexible Static Memory Controller)"
|
|
base ad:0xA0000000
|
|
width 12.
|
|
tree "NOR/PSRAM Controller Registers"
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "FSMC_BCR1,SRAM/NOR-Flash Chip-select Control Register 1"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 21. " WFDIS ,Write FIFO disable" "No,Yes"
|
|
bitfld.long 0x00 20. " CCLKEN ,Continuous clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x0+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR1,SRAM/NOR-Flash Chip-select Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x0+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR1,SRAM/NOR-Flash Write Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "FSMC_BCR2,SRAM/NOR-Flash Chip-select Control Register 2"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x8+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR2,SRAM/NOR-Flash Chip-select Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x8+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR2,SRAM/NOR-Flash Write Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "FSMC_BCR3,SRAM/NOR-Flash Chip-select Control Register 3"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x10+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR3,SRAM/NOR-Flash Chip-select Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x10+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR3,SRAM/NOR-Flash Write Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "FSMC_BCR4,SRAM/NOR-Flash Chip-select Control Register 4"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x18+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR4,SRAM/NOR-Flash Chip-select Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x18+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR4,SRAM/NOR-Flash Write Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE")&&!cpuis("STM32L15?R?")&&!cpuis("STM32L15?V?")&&!cpuis("STM32L15?Z?")&&!cpuis("STM32L15?Q?")&&!cpuis("STM32L15?C6")&&!cpuis("STM32L162?D")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
tree "NAND Flash/PC Card Controller Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FSMC_PCR2,PC Card/NAND Flash Control Registers 2"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR2,FIFO Status and Interrupt Register 2"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM2,Common Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ2 ,Common memory 2 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD2 ,Common memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT2 ,Common memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET2 ,Common memory 2 setup time"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT2,Attribute Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ2 ,Attribute memory 2 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD2 ,Attribute memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT2 ,Attribute memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET2 ,Attribute memory 2 setup time"
|
|
if (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x00)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x20000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x40000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--25. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x60000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--27. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x80000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--29. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
else
|
|
hgroup.long (0x60+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FSMC_PCR3,PC Card/NAND Flash Control Registers 3"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR3,FIFO Status and Interrupt Register 3"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM3,Common Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ3 ,Common memory 3 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD3 ,Common memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT3 ,Common memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET3 ,Common memory 3 setup time"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT3,Attribute Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ3 ,Attribute memory 3 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD3 ,Attribute memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT3 ,Attribute memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET3 ,Attribute memory 3 setup time"
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--25. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--27. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
else
|
|
hgroup.long (0x80+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "FSMC_PCR4,PC Card/NAND Flash Control Registers 4"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR4,FIFO Status and Interrupt Register 4"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM4,Common Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ4 ,Common memory 4 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD4 ,Common memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT4 ,Common memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET4 ,Common memory 4 setup time"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT4,Attribute Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ4 ,Attribute memory 4 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD4 ,Attribute memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT4 ,Attribute memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET4 ,Attribute memory 4 setup time"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "FSMC_PIO4,I/O Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IOHIZ4 ,I/O 4 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IOHOLD4 ,I/O 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " IOWAIT4 ,I/O 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSET4 ,I/O 4 setup time"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C 1"
|
|
base ad:0x40005400
|
|
width 11.
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start"
|
|
bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_CR2,Control Register 2"
|
|
bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last"
|
|
bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F2*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..."
|
|
endif
|
|
if (((per.w((ad:0x40005400+0x08)))&0x8000)==0x8000)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address"
|
|
endif
|
|
if (((per.w((ad:0x40005400+0x0C)))&0x1)==0x1)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
endif
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "I2C_DR,Data Register"
|
|
in
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "I2C_SR1,Status Register 1"
|
|
in
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header"
|
|
bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address"
|
|
textline " "
|
|
bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
endif
|
|
if (((per.l(ad:0x40005400))&0x1)==0x1)
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C 2"
|
|
base ad:0x40005800
|
|
width 11.
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start"
|
|
bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_CR2,Control Register 2"
|
|
bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last"
|
|
bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F2*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..."
|
|
endif
|
|
if (((per.w((ad:0x40005800+0x08)))&0x8000)==0x8000)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address"
|
|
endif
|
|
if (((per.w((ad:0x40005800+0x0C)))&0x1)==0x1)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
endif
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "I2C_DR,Data Register"
|
|
in
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "I2C_SR1,Status Register 1"
|
|
in
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header"
|
|
bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address"
|
|
textline " "
|
|
bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
endif
|
|
if (((per.l(ad:0x40005800))&0x1)==0x1)
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
rbitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
if (((d.l((ad:0x40013800+0x0C)))&0x8000)==0x8000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--2. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((d.l((ad:0x40013800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((d.l((ad:0x40013800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
rbitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
if (((d.l((ad:0x40004400+0x0C)))&0x8000)==0x8000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--2. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((d.l((ad:0x40004400+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((d.l((ad:0x40004400+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 3"
|
|
base ad:0x40004800
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
rbitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
if (((d.l((ad:0x40004800+0x0C)))&0x8000)==0x8000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--2. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((d.l((ad:0x40004800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((d.l((ad:0x40004800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
tree "USART 4"
|
|
base ad:0x40004C00
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
rbitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
if (((d.l((ad:0x40004C00+0x0C)))&0x8000)==0x8000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--2. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((d.l((ad:0x40004C00+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((d.l((ad:0x40004C00+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 5"
|
|
base ad:0x40005000
|
|
width 12.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
rbitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
if (((d.l((ad:0x40005000+0x0C)))&0x8000)==0x8000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--2. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((d.l((ad:0x40005000+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 bits,9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((d.l((ad:0x40005000+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40013800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40013800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004400+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40004400+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 3"
|
|
base ad:0x40004800
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40004800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D"))
|
|
tree "USART 4"
|
|
base ad:0x40004C00
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004C00+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,Reserved,2,Reseved"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 5"
|
|
base ad:0x40005000
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40005000+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,Reserved,2,Reseved"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
tree "SPI 1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
if ((d.w((ad:0x40013000+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SPI_SR,SPI status register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "SPI_DR,SPI data register"
|
|
in
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 2/I2S2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
if ((d.w((ad:0x40003800+0x1C))&0x800)==0x000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((d.w((ad:0x40003800+0x1C))&0x800)==0x000)
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
if ((d.w((ad:0x40003800+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,#"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SPI_SR,SPI status register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "SPI_DR,SPI data register"
|
|
in
|
|
if (((d.w((ad:0x40003800+0x1C)))&0x800)==0x000)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((d.w((ad:0x40003800+0x1C)))&0x800)==0x000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
elif (((d.w((ad:0x40003800+0x1C)))&0x830)==0x830)
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Philips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Philips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((d.w((ad:0x40003800+0x1C)))&0xB00)==0xA00)||(((d.w((ad:0x40003800+0x1C)))&0xB00)==0xB00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV*2,(I2SDIV*2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 3/I2S2"
|
|
base ad:0x40003C00
|
|
width 12.
|
|
if ((d.w((ad:0x40003C00+0x1C))&0x800)==0x000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((d.w((ad:0x40003C00+0x1C))&0x800)==0x000)
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
if ((d.w((ad:0x40003C00+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,#"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SPI_SR,SPI status register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "SPI_DR,SPI data register"
|
|
in
|
|
if (((d.w((ad:0x40003C00+0x1C)))&0x800)==0x000)
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((d.w((ad:0x40003C00+0x1C)))&0x800)==0x000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
elif (((d.w((ad:0x40003C00+0x1C)))&0x830)==0x830)
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Philips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Philips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((d.w((ad:0x40003C00+0x1C)))&0xB00)==0xA00)||(((d.w((ad:0x40003C00+0x1C)))&0xB00)==0xB00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV*2,(I2SDIV*2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SPI 1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
if ((d.w((ad:0x40013000+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SPI_SR,SPI status register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "SPI_DR,SPI data register"
|
|
in
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
sif cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
if ((d.w((ad:0x40003800+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SPI_SR,SPI status register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "SPI_DR,SPI data register"
|
|
in
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
tree "SPI 2/I2S2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif ((per.w((ad:0x40003800+0x1c))&0x830)==0x830)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x800)||(((per.w((ad:0x40003800+0x1c)))&0x800)==0x800))
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x1
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x00))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif ((((per.w((ad:0x40003800+0x1c)))&0x830)==0x830))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0xB00)==0xA00)||(((per.w((ad:0x40003800+0x1c)))&0xB00)==0xB00))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 3/I2S2"
|
|
base ad:0x40003C00
|
|
width 12.
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif ((per.w((ad:0x40003C00+0x1c))&0x830)==0x830)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x800)||(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x800))
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x1
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x00))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif ((((per.w((ad:0x40003C00+0x1c)))&0x830)==0x830))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0xB00)==0xA00)||(((per.w((ad:0x40003C00+0x1c)))&0xB00)==0xB00))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "SPI 2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D"))
|
|
tree.open "SDIO (Secure digital input/output interface)"
|
|
tree "SDIO"
|
|
base ad:0x40012C00
|
|
width 14.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "SDIO_POWER,SDIO Power Control Register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Power-off,,Power-up,Power-on"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Off,,,On"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "SDIO_CLKCR,SDI Clock Control Register"
|
|
bitfld.long 0x04 14. " HWFC_EN ,HW Flow Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " NEGEDGE ,SDIO_CK dephasing selection bit" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x04 11.--12. " WIDBUS ,Wide bus mode enable bit" "SDIO_D0,SDIO_D[3:0],SDIO_D[7:0],?..."
|
|
bitfld.long 0x04 10. " BYPASS ,Clock divider bypass enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled/bus active"
|
|
bitfld.long 0x04 8. " CLKEN ,Clock enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLKDIV ,Clock divide factor"
|
|
line.long 0x08 "SDIO_ARG,SDIO Argument Register"
|
|
line.long 0x0C "SDIO_CMD,SDIO Command Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x0C 14. " ATACMD ,CE-ATA command" "No transfer,CPSM transfers CMD61"
|
|
bitfld.long 0x0C 13. " NIEN ,not Interrupt Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " ENCMDCOMP1 ,Enable CMD completion" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 11. " SDIOSUSPEND ,SD I/O suspend command" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CPSMEN ,Command path state machine (CPSM) Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " WAITPEND ,CPSM Waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " WAITINT ,CPSM Waits for Interrupt Request" "Not requested,Requested"
|
|
bitfld.long 0x0C 6.--7. " WAITRESP ,Wait for response bits" "No response,Short response,No response,Long response"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " CMDINDEX ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "SDIO_RESPCMD,SDIO Command Response Register"
|
|
bitfld.long 0x00 0.--5. " RESPCMD ,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.l((ad:0x40012C00+0x0C))&0xC0)==0x40)
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status[31:0]"
|
|
hgroup.long 0x18++0x0B
|
|
hide.long 0x00 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hide.long 0x04 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hide.long 0x08 "SDIO_RESP4,SDIO Response 4 Register"
|
|
elif ((per.l((ad:0x40012C00+0x0C))&0xC0)==0xC0)
|
|
rgroup.long 0x14++0xF
|
|
line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status [127:96]"
|
|
line.long 0x04 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hexmask.long 0x04 0.--31. 1. " CARDSTATUS2 ,Card Status [95:64]"
|
|
line.long 0x08 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hexmask.long 0x08 0.--31. 1. " CARDSTATUS3 ,Card Status [63:32]"
|
|
line.long 0x0C "SDIO_RESP4,SDIO Response 4 Register"
|
|
hexmask.long 0x0C 0.--31. 1. " CARDSTATUS3 ,Card Status [31:0]"
|
|
else
|
|
hgroup.long 0x14++0xF
|
|
hide.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hide.long 0x04 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hide.long 0x08 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hide.long 0x0C "SDIO_RESP4,SDIO Response 4 Register"
|
|
endif
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "SDIO_DTIMER,SDIO Data Timer Register"
|
|
line.long 0x04 "SDIO_DLEN,SDIO Data Length Register"
|
|
hexmask.long 0x04 0.--24. 1. " DATALENGTH ,Data length value"
|
|
line.long 0x08 "SDIO_DCTRL,SDIO Data Control Register"
|
|
bitfld.long 0x08 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RWMOD ,Read wait mode" "Stopping SDIO_D2,Using SDIO_CK"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RWSTOP ,Read wait stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 8. " RWSTART ,Read wait start" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " DBLOCKSIZE ,Data block size" "1 byte,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes,?..."
|
|
bitfld.long 0x08 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DTMODE ,Data transfer mode selection" "Block,Stream"
|
|
bitfld.long 0x08 1. " DTDIR ,Data transfer direction selection" "Controller to card,Card to controller"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "SDIO_DCOUNT,SDIO Data Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value"
|
|
line.long 0x04 "SDIO_STA,SDIO Status Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 23. " CEATAEND ,CE-ATA command completion signal received for CMD61" "Not completed,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "Not available,Available"
|
|
bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO Half Full: there are at least 8 words in the FIFO" "Not half full,Half full"
|
|
bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO Half Empty: at least 8 words can be written into the FIFO" "Not half empty,Half empty"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Not in progress,In progress"
|
|
bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Not in progress,In progress"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Not in progress,In progress"
|
|
bitfld.long 0x04 10. " DBCKEND ,Data block sent/received" "Not sent/received,Sent/Received"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x04 9. " STBITERR ,Start bit not detected on all data signals in wide bus mode" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " DATAEND ,Data end" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CMDSENT ,Command sent" "Not sent,Sent"
|
|
bitfld.long 0x04 6. " CMDREND ,Command response received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No overrun,Overrun"
|
|
bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received" "Not sent/received,Sent/received"
|
|
bitfld.long 0x04 0. " CCRCFAIL ,Command response received" "Not received,Received"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SDIO_ICR,SDIO Interrupt Clear Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x00 23. " CEATAENDC ,CEATAEND Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x00 9. " STBITERRC ,STBITERR Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDC ,DATAEND Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 7. " CMDSENTC ,CMDSENT Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CMDRENDC ,CMDREND Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " RXOVERRC ,RXOVERR Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL Flag Clear Bit" "Not cleared,Cleared"
|
|
line.long 0x04 "SDIO_MASK,SDIO Mask Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 23. " CEATAENDIE ,CE-ATA command completion signal received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOITIE ,SDIO Mode Interrupt Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " RXDAVLIE ,Data available in Rx FIFO Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TXDAVLIE ,Data available in Tx FIFO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " RXFIFOEIE ,Rx FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " TXFIFOEIE ,Tx FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " RXFIFOFIE ,Rx FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TXFIFOFIE ,Tx FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " RXFIFOHFIE ,Rx FIFO Half Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " TXFIFOHEIE ,Tx FIFO Half Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RXACTIE ,Data Receive Acting Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TXACTIE ,Data Transmit Acting Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CMDACTIE ,Command Acting Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DBCKENDIE ,Data Block End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x04 9. " STBITERRIE ,Start Bit Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " DATAENDIE ,Data End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " CMDSENTIE ,Command Sent Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CMDRENDIE ,Command Response Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXOVERRIE ,Rx FIFO OverRun Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TXUNDERRIE ,Tx FIFO UnderRun Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DTIMEOUTIE ,Data TimeOut Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CTIMEOUTIE ,Command TimeOut Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DCRCFAILIE ,Data CRC Fail Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CCRCFAILIE ,Command CRC Fail Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SDIO_FIFOCNT,SDIO FIFO Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO"
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "SDIO_FIFO0,SDIO Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "SDIO_FIFO1,SDIO Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "SDIO_FIFO2,SDIO Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "SDIO_FIFO3,SDIO Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "SDIO_FIFO4,SDIO Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "SDIO_FIFO5,SDIO Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "SDIO_FIFO6,SDIO Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "SDIO_FIFO7,SDIO Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "SDIO_FIFO8,SDIO Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "SDIO_FIFO9,SDIO Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "SDIO_FIFO10,SDIO Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "SDIO_FIFO11,SDIO Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "SDIO_FIFO12,SDIO Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "SDIO_FIFO13,SDIO Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "SDIO_FIFO14,SDIO Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "SDIO_FIFO15,SDIO Data FIFO Register 15"
|
|
in
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "SDIO_FIFO16,SDIO Data FIFO Register 16"
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "SDIO_FIFO17,SDIO Data FIFO Register 17"
|
|
in
|
|
hgroup.long 0xC8++0x03
|
|
hide.long 0x00 "SDIO_FIFO18,SDIO Data FIFO Register 18"
|
|
in
|
|
hgroup.long 0xCC++0x03
|
|
hide.long 0x00 "SDIO_FIFO19,SDIO Data FIFO Register 19"
|
|
in
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "SDIO_FIFO20,SDIO Data FIFO Register 20"
|
|
in
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "SDIO_FIFO21,SDIO Data FIFO Register 21"
|
|
in
|
|
hgroup.long 0xD8++0x03
|
|
hide.long 0x00 "SDIO_FIFO22,SDIO Data FIFO Register 22"
|
|
in
|
|
hgroup.long 0xDC++0x03
|
|
hide.long 0x00 "SDIO_FIFO23,SDIO Data FIFO Register 23"
|
|
in
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "SDIO_FIFO24,SDIO Data FIFO Register 24"
|
|
in
|
|
hgroup.long 0xE4++0x03
|
|
hide.long 0x00 "SDIO_FIFO25,SDIO Data FIFO Register 25"
|
|
in
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SDIO_FIFO26,SDIO Data FIFO Register 26"
|
|
in
|
|
hgroup.long 0xEC++0x03
|
|
hide.long 0x00 "SDIO_FIFO27,SDIO Data FIFO Register 27"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "SDIO_FIFO28,SDIO Data FIFO Register 28"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "SDIO_FIFO29,SDIO Data FIFO Register 29"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "SDIO_FIFO30,SDIO Data FIFO Register 30"
|
|
in
|
|
hgroup.long 0xFC++0x03
|
|
hide.long 0x00 "SDIO_FIFO31,SDIO Data FIFO Register 31"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
textline ""
|