31769 lines
1.8 MiB
31769 lines
1.8 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32G4x On-Chip Peripherals
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; @Props: Released
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; @Author: TRJ, KMB, DAB, NEJ, KRZ
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; @Changelog: 2019-10-04 TRJ
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; 2021-08-16 KMB
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; 2022-01-28 DAB
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; 2023-09-20 NEJ
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; 2023-10-13 KRZ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: Generated (TRACE32, build: 163471.), based on:
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; STM32G431.svd (Ver. 2.1), STM32G441.svd (Ver. 2.1),
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; STM32G471.svd (Ver. 2.1), STM32G473.svd (Ver. 2.2),
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; STM32G474.svd (Ver. 2.1), STM32G483.svd (Ver. 2.1),
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; STM32G484.svd (Ver. 2.1), STM32G491.svd (Ver. 1.9),
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; STM32G4A1.svd (Ver. 1.9), STM32GBK1CBT6.svd (Ver. 2.1)
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; @Core: Cortex-M4F
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; @Chip: STM32G431C6, STM32G431C8, STM32G431CB, STM32G431K6, STM32G431K8,
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; STM32G431KB, STM32G431M6, STM32G431M8, STM32G431MB, STM32G431R6,
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; STM32G431R8, STM32G431RB, STM32G431V6, STM32G431V8, STM32G431VB,
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; STM32G441CB, STM32G441KB, STM32G441MB, STM32G441RB, STM32G441VB,
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; STM32G473CB, STM32G473CC, STM32G473CE, STM32G473MB, STM32G473MC,
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; STM32G473ME, STM32G473QB, STM32G473QC, STM32G473QE, STM32G473RB,
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; STM32G473RC, STM32G473RE, STM32G473VB, STM32G473VC, STM32G473VE,
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; STM32G474CB, STM32G474CC, STM32G474CE, STM32G474MB, STM32G474MC,
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; STM32G474ME, STM32G474QB, STM32G474QC, STM32G474QE, STM32G474RB,
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; STM32G474RC, STM32G474RE, STM32G474VB, STM32G474VC, STM32G474VE,
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; STM32G483CE, STM32G483ME, STM32G483QE, STM32G483RE, STM32G483VE,
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; STM32G484CE, STM32G484ME, STM32G484QE, STM32G484RE, STM32G484VE,
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; STM32G491CC, STM32G491CE, STM32G491KC, STM32G491KE, STM32G491MC,
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; STM32G491ME, STM32G491RC, STM32G491RE, STM32G491VC, STM32G491VE,
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; STM32G4A1CE, STM32G4A1KE, STM32G4A1ME, STM32G4A1RE, STM32G4A1VE
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32g4.per 16749 2023-10-13 11:19:56Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
AUTOINDENT.ON CENTER TREE
|
|
ENUMDELIMITER ","
|
|
base ad:0x0
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x0
|
|
tree "ADC1"
|
|
base ad:0x50000000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC2"
|
|
base ad:0x50000100
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC12_Common"
|
|
base ad:0x50000300
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CSR,ADC Common status register"
|
|
bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOSMP_SLV,EOSMP_SLV" "0,1"
|
|
bitfld.long 0x0 16. "ADRDY_SLV,ADRDY_SLV" "0,1"
|
|
bitfld.long 0x0 10. "JQOVF_MST,JQOVF_MST" "0,1"
|
|
bitfld.long 0x0 9. "AWD3_MST,AWD3_MST" "0,1"
|
|
bitfld.long 0x0 8. "AWD2_MST,AWD2_MST" "0,1"
|
|
bitfld.long 0x0 7. "AWD1_MST,AWD1_MST" "0,1"
|
|
bitfld.long 0x0 6. "JEOS_MST,JEOS_MST" "0,1"
|
|
bitfld.long 0x0 5. "JEOC_MST,JEOC_MST" "0,1"
|
|
bitfld.long 0x0 4. "OVR_MST,OVR_MST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS_MST,EOS_MST" "0,1"
|
|
bitfld.long 0x0 2. "EOC_MST,EOC_MST" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP_MST,EOSMP_MST" "0,1"
|
|
bitfld.long 0x0 0. "ADDRDY_MST,ADDRDY_MST" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CCR,ADC common control register"
|
|
bitfld.long 0x0 24. "VBATSEL,VBAT selection" "0,1"
|
|
bitfld.long 0x0 23. "VSENSESEL,VTS selection" "0,1"
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MDMA,Direct memory access mode for multi ADC mode" "0,1,2,3"
|
|
bitfld.long 0x0 13. "DMACFG,DMA configuration (for multi-ADC mode)" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling phases"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CDR,ADC common regular data register for dual and triple modes"
|
|
hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC"
|
|
tree.end
|
|
sif (cpuis("STM32G471*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC4"
|
|
base ad:0x50000500
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC5"
|
|
base ad:0x50000600
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC4"
|
|
base ad:0x50000500
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC5"
|
|
base ad:0x50000600
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC4"
|
|
base ad:0x50000500
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC5"
|
|
base ad:0x50000600
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC4"
|
|
base ad:0x50000500
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
tree "ADC5"
|
|
base ad:0x50000600
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G491*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G4A1*"))
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "ISR,interrupt and status register"
|
|
bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x0 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x0 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x0 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x0 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x0 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x0 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1"
|
|
line.long 0x4 "IER,interrupt enable register"
|
|
bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
line.long 0x8 "CR,control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADEN" "0,1"
|
|
line.long 0xC "CFGR,configuration register"
|
|
bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,AWDCH1CH"
|
|
bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0xC 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0xC 15. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0xC 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group"
|
|
bitfld.long 0xC 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0xC 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0xC 0. "DMAEN,DMAEN" "0,1"
|
|
line.long 0x10 "CFGR2,configuration register"
|
|
bitfld.long 0x10 27. "SMPTRIG,SMPTRIG" "0,1"
|
|
bitfld.long 0x10 26. "BULB,BULB" "0,1"
|
|
bitfld.long 0x10 25. "SWTRIG,SWTRIG" "0,1"
|
|
bitfld.long 0x10 16. "GCOMP,GCOMP" "0,1"
|
|
bitfld.long 0x10 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0,1"
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,ALIGN"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x10 0. "ROVSE,DMAEN" "0,1"
|
|
line.long 0x14 "SMPR1,sample time register 1"
|
|
bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time" "0,1"
|
|
bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMPR2,sample time register 2"
|
|
bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,HT1"
|
|
bitfld.long 0x0 12.--14. "AWDFILT,AWDFILT" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,LT1"
|
|
line.long 0x4 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x4 0.--7. 1. "LT2,LT2"
|
|
line.long 0x8 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "SQR1,regular sequence register 1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4"
|
|
hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3"
|
|
hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2"
|
|
hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length"
|
|
line.long 0x4 "SQR2,regular sequence register 2"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9"
|
|
hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8"
|
|
hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7"
|
|
hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5"
|
|
line.long 0x8 "SQR3,regular sequence register 3"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14"
|
|
hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13"
|
|
hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12"
|
|
hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10"
|
|
line.long 0xC "SQR4,regular sequence register 4"
|
|
hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,regular Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular Data converted"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "JSQR,injected sequence register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4"
|
|
hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3"
|
|
hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2"
|
|
hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1"
|
|
bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL"
|
|
bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "OFR1,offset register 1"
|
|
bitfld.long 0x0 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x0 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x0 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x4 "OFR2,offset register 2"
|
|
bitfld.long 0x4 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x4 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x4 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0x8 "OFR3,offset register 3"
|
|
bitfld.long 0x8 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0x8 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0x8 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0x8 0.--11. 1. "OFFSET1,OFFSET1"
|
|
line.long 0xC "OFR4,offset register 4"
|
|
bitfld.long 0xC 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,OFFSET1_CH"
|
|
bitfld.long 0xC 25. "SATEN,SATEN" "0,1"
|
|
bitfld.long 0xC 24. "OFFSETPOS,OFFSETPOS" "0,1"
|
|
hexmask.long.word 0xC 0.--11. 1. "OFFSET1,OFFSET1"
|
|
rgroup.long 0x80++0xF
|
|
line.long 0x0 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "JDATA1,JDATA1"
|
|
line.long 0x4 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "JDATA2,JDATA2"
|
|
line.long 0x8 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "JDATA3,JDATA3"
|
|
line.long 0xC "JDR4,injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "JDATA4,JDATA4"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,AWD2CH"
|
|
line.long 0x4 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "DIFSEL,Differential Mode Selection Register 2"
|
|
hexmask.long.tbyte 0x0 1.--18. 1. "DIFSEL_1_18,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x0 0. "DIFSEL_0,Differential mode for channels 0" "0,1"
|
|
line.long 0x4 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "GCOMP,Gain compensation Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "GCOMPCOEFF,GCOMPCOEFF"
|
|
tree.end
|
|
endif
|
|
tree "ADC345_Common"
|
|
base ad:0x50000700
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CSR,ADC Common status register"
|
|
bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the slave ADC" "0,1"
|
|
bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave ADC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOSMP_SLV,EOSMP_SLV" "0,1"
|
|
bitfld.long 0x0 16. "ADRDY_SLV,ADRDY_SLV" "0,1"
|
|
bitfld.long 0x0 10. "JQOVF_MST,JQOVF_MST" "0,1"
|
|
bitfld.long 0x0 9. "AWD3_MST,AWD3_MST" "0,1"
|
|
bitfld.long 0x0 8. "AWD2_MST,AWD2_MST" "0,1"
|
|
bitfld.long 0x0 7. "AWD1_MST,AWD1_MST" "0,1"
|
|
bitfld.long 0x0 6. "JEOS_MST,JEOS_MST" "0,1"
|
|
bitfld.long 0x0 5. "JEOC_MST,JEOC_MST" "0,1"
|
|
bitfld.long 0x0 4. "OVR_MST,OVR_MST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS_MST,EOS_MST" "0,1"
|
|
bitfld.long 0x0 2. "EOC_MST,EOC_MST" "0,1"
|
|
bitfld.long 0x0 1. "EOSMP_MST,EOSMP_MST" "0,1"
|
|
bitfld.long 0x0 0. "ADDRDY_MST,ADDRDY_MST" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CCR,ADC common control register"
|
|
bitfld.long 0x0 24. "VBATSEL,VBAT selection" "0,1"
|
|
bitfld.long 0x0 23. "VSENSESEL,VTS selection" "0,1"
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MDMA,Direct memory access mode for multi ADC mode" "0,1,2,3"
|
|
bitfld.long 0x0 13. "DMACFG,DMA configuration (for multi-ADC mode)" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling phases"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CDR,ADC common regular data register for dual and triple modes"
|
|
hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave ADC"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master ADC"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*")||cpuis("STM32G473*")||cpuis("STM32G483*")||cpuis("STM32G484*")||cpuis("STM32G4A1*")||cpuis("STM32GBK1CB*"))
|
|
tree "AES (Advanced Encryption Standard Hardware Accelerator)"
|
|
base ad:0x50060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB"
|
|
bitfld.long 0x0 18. "KEYSIZE,KEYSIZE" "0,1"
|
|
bitfld.long 0x0 16. "CHMOD_2,CHMOD_2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,GCMPH" "0,1,2,3"
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x0 5.--6. "CHMOD,AES chaining mode" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key [31:0])"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key [63:32])"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key [95:64])"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key [127:96])"
|
|
line.long 0x10 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR [31:0])"
|
|
line.long 0x14 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR [63:32])"
|
|
line.long 0x18 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR [95:64])"
|
|
line.long 0x1C "IVR3,initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR [127:96])"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "KEY,AES key"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "KEY,AES key"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "KEY,AES key"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "KEY,AES key"
|
|
line.long 0x30 "SUSP0R,suspend registers"
|
|
hexmask.long 0x30 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x34 "SUSP1R,suspend registers"
|
|
hexmask.long 0x34 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x38 "SUSP2R,suspend registers"
|
|
hexmask.long 0x38 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x3C "SUSP3R,suspend registers"
|
|
hexmask.long 0x3C 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x40 "SUSP4R,suspend registers"
|
|
hexmask.long 0x40 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x44 "SUSP5R,suspend registers"
|
|
hexmask.long 0x44 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x48 "SUSP6R,suspend registers"
|
|
hexmask.long 0x48 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x4C "SUSP7R,suspend registers"
|
|
hexmask.long 0x4C 0.--31. 1. "SUSP,AES suspend"
|
|
tree.end
|
|
endif
|
|
tree "COMP (Comparators)"
|
|
base ad:0x40010200
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "COMP_C1CSR,Comparator control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x0 30. "VALUE,VALUE" "0,1"
|
|
bitfld.long 0x0 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x0 22. "BRGEN,BRGEN" "0,1"
|
|
bitfld.long 0x0 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "POL,POL" "0,1"
|
|
bitfld.long 0x0 8. "INPSEL,INPSEL" "0,1"
|
|
bitfld.long 0x0 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "COMP_C2CSR,Comparator control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x4 30. "VALUE,VALUE" "0,1"
|
|
bitfld.long 0x4 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x4 22. "BRGEN,BRGEN" "0,1"
|
|
bitfld.long 0x4 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "POL,POL" "0,1"
|
|
bitfld.long 0x4 8. "INPSEL,INPSEL" "0,1"
|
|
bitfld.long 0x4 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "EN,EN" "0,1"
|
|
line.long 0x8 "COMP_C3CSR,Comparator control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x8 30. "VALUE,VALUE" "0,1"
|
|
bitfld.long 0x8 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x8 22. "BRGEN,BRGEN" "0,1"
|
|
bitfld.long 0x8 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "POL,POL" "0,1"
|
|
bitfld.long 0x8 8. "INPSEL,INPSEL" "0,1"
|
|
bitfld.long 0x8 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0. "EN,EN" "0,1"
|
|
line.long 0xC "COMP_C4CSR,Comparator control/status register"
|
|
bitfld.long 0xC 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0xC 30. "VALUE,VALUE" "0,1"
|
|
bitfld.long 0xC 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0xC 22. "BRGEN,BRGEN" "0,1"
|
|
bitfld.long 0xC 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 15. "POL,POL" "0,1"
|
|
bitfld.long 0xC 8. "INPSEL,INPSEL" "0,1"
|
|
bitfld.long 0xC 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0. "EN,EN" "0,1"
|
|
sif (cpuis("STM32G473*"))
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "COMP_C5CSR,Comparator control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x0 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x0 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "POL,POL" "0,1"
|
|
bitfld.long 0x0 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "COMP_C6CSR,Comparator control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x4 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x4 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "POL,POL" "0,1"
|
|
bitfld.long 0x4 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "EN,EN" "0,1"
|
|
line.long 0x8 "COMP_C7CSR,Comparator control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x8 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x8 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "POL,POL" "0,1"
|
|
bitfld.long 0x8 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0. "EN,EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "COMP_C5CSR,Comparator control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x0 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x0 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "POL,POL" "0,1"
|
|
bitfld.long 0x0 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "COMP_C6CSR,Comparator control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x4 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x4 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "POL,POL" "0,1"
|
|
bitfld.long 0x4 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "EN,EN" "0,1"
|
|
line.long 0x8 "COMP_C7CSR,Comparator control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x8 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x8 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "POL,POL" "0,1"
|
|
bitfld.long 0x8 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0. "EN,EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "COMP_C5CSR,Comparator control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x0 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x0 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "POL,POL" "0,1"
|
|
bitfld.long 0x0 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "COMP_C6CSR,Comparator control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x4 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x4 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "POL,POL" "0,1"
|
|
bitfld.long 0x4 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "EN,EN" "0,1"
|
|
line.long 0x8 "COMP_C7CSR,Comparator control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x8 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x8 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "POL,POL" "0,1"
|
|
bitfld.long 0x8 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0. "EN,EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "COMP_C5CSR,Comparator control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x0 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x0 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15. "POL,POL" "0,1"
|
|
bitfld.long 0x0 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,EN" "0,1"
|
|
line.long 0x4 "COMP_C6CSR,Comparator control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x4 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x4 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "POL,POL" "0,1"
|
|
bitfld.long 0x4 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "EN,EN" "0,1"
|
|
line.long 0x8 "COMP_C7CSR,Comparator control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
rbitfld.long 0x8 30. "VALUE,VALUE" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "SCALEN,SCALEN" "0,1"
|
|
bitfld.long 0x8 22. "BRGEN,BRGEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19.--21. "BLANKSEL,BLANKSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "HYST,HYST" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "POL,POL" "0,1"
|
|
bitfld.long 0x8 8. "INPSEL,INPSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "INMSEL,INMSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0. "EN,EN" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "CORDIC (CORDIC co-processor)"
|
|
base ad:0x40020C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,CORDIC Control Status register"
|
|
bitfld.long 0x0 31. "RRDY,RRDY" "0,1"
|
|
bitfld.long 0x0 22. "ARGSIZE,ARGSIZE" "0,1"
|
|
bitfld.long 0x0 21. "RESSIZE,RESSIZE" "0,1"
|
|
bitfld.long 0x0 20. "NARGS,NARGS" "0,1"
|
|
bitfld.long 0x0 19. "NRES,NRES" "0,1"
|
|
bitfld.long 0x0 18. "DMAWEN,DMAWEN" "0,1"
|
|
bitfld.long 0x0 17. "DMAREN,DMAREN" "0,1"
|
|
bitfld.long 0x0 16. "IEN,IEN" "0,1"
|
|
bitfld.long 0x0 8.--10. "SCALE,SCALE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRECISION,PRECISION"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FUNC,FUNC"
|
|
line.long 0x4 "WDATA,FMAC Write Data register"
|
|
hexmask.long 0x4 0.--31. 1. "ARG,ARG"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDATA,FMAC Read Data register"
|
|
hexmask.long 0x0 0.--31. 1. "RES,RES"
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 8-bit data register bits"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
tree.end
|
|
tree "CRS (Clock Recovery System)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,CRS control register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TRIM,HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that.."
|
|
bitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware." "0,1"
|
|
bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set the TRIM bits are read-only. The TRIM value.." "0,1"
|
|
bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set the CRS_CFGR register is write-protected and cannot be modified." "0,1"
|
|
bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt enable" "0,1"
|
|
line.long 0x4 "CFGR,This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled. this register is write-protected."
|
|
bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source." "0,1"
|
|
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode the periodic USB SOF will not be.." "0,1,2,3"
|
|
bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic.."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ISR,CRS interrupt and status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage."
|
|
bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target." "0,1"
|
|
bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by.." "0,1"
|
|
bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency.." "0,1"
|
|
bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal.." "0,1"
|
|
bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC.." "0,1"
|
|
bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register." "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3 but smaller than FELIM * 128. This means that to compensate the frequency error the TRIM value must be.." "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough.." "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "ICR,CRS interrupt flag clear register"
|
|
bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register." "0,1"
|
|
bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit clears TRIMOVF SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register." "0,1"
|
|
bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register." "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register." "0,1"
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x0
|
|
tree "DAC1"
|
|
base ad:0x50000800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DAC_CR,DAC control register"
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)."
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2." "0,1"
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1." "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x0 17. "SWTRIGB2,DAC channel2 software trigger B" "0,1"
|
|
bitfld.long 0x0 16. "SWTRIGB1,DAC channel1 software trigger B" "0,1"
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2.." "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1.." "0,1"
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B"
|
|
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned data"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data"
|
|
hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B"
|
|
hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2."
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1."
|
|
line.long 0x4 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output"
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2."
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1"
|
|
bitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1"
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1"
|
|
bitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1"
|
|
line.long 0x4 "DAC_CCR,DAC calibration control register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value"
|
|
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value"
|
|
line.long 0x8 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1"
|
|
bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3"
|
|
bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1"
|
|
bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI"
|
|
hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "DAC_STR1,Sawtooth register"
|
|
hexmask.long.word 0x0 16.--31. 1. "STINCDATA1,DAC CH1 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x0 12. "STDIR1,DAC Channel1 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "STRSTDATA1,DAC Channel 1 Sawtooth reset value"
|
|
line.long 0x4 "DAC_STR2,Sawtooth register"
|
|
hexmask.long.word 0x4 16.--31. 1. "STINCDATA2,DAC CH2 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x4 12. "STDIR2,DAC Channel2 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "STRSTDATA2,DAC Channel 2 Sawtooth reset value"
|
|
line.long 0x8 "DAC_STMODR,Sawtooth Mode register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "STINCTRIGSEL2,DAC Channel 2 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 16.--19. 1. "STRSTTRIGSEL2,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "STINCTRIGSEL1,DAC Channel 1 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "STRSTTRIGSEL1,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
tree.end
|
|
tree "DAC2"
|
|
base ad:0x50000C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DAC_CR,DAC control register"
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)."
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2." "0,1"
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1." "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x0 17. "SWTRIGB2,DAC channel2 software trigger B" "0,1"
|
|
bitfld.long 0x0 16. "SWTRIGB1,DAC channel1 software trigger B" "0,1"
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2.." "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1.." "0,1"
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B"
|
|
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned data"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data"
|
|
hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B"
|
|
hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2."
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1."
|
|
line.long 0x4 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output"
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2."
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1"
|
|
bitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1"
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1"
|
|
bitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1"
|
|
line.long 0x4 "DAC_CCR,DAC calibration control register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value"
|
|
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value"
|
|
line.long 0x8 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1"
|
|
bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3"
|
|
bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1"
|
|
bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI"
|
|
hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "DAC_STR1,Sawtooth register"
|
|
hexmask.long.word 0x0 16.--31. 1. "STINCDATA1,DAC CH1 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x0 12. "STDIR1,DAC Channel1 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "STRSTDATA1,DAC Channel 1 Sawtooth reset value"
|
|
line.long 0x4 "DAC_STR2,Sawtooth register"
|
|
hexmask.long.word 0x4 16.--31. 1. "STINCDATA2,DAC CH2 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x4 12. "STDIR2,DAC Channel2 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "STRSTDATA2,DAC Channel 2 Sawtooth reset value"
|
|
line.long 0x8 "DAC_STMODR,Sawtooth Mode register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "STINCTRIGSEL2,DAC Channel 2 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 16.--19. 1. "STRSTTRIGSEL2,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "STINCTRIGSEL1,DAC Channel 1 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "STRSTTRIGSEL1,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
tree.end
|
|
tree "DAC3"
|
|
base ad:0x50001000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DAC_CR,DAC control register"
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)."
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2." "0,1"
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1." "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x0 17. "SWTRIGB2,DAC channel2 software trigger B" "0,1"
|
|
bitfld.long 0x0 16. "SWTRIGB1,DAC channel1 software trigger B" "0,1"
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2.." "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1.." "0,1"
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B"
|
|
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned data"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data"
|
|
hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B"
|
|
hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2."
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1."
|
|
line.long 0x4 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output"
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2."
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1"
|
|
bitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1"
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1"
|
|
bitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1"
|
|
line.long 0x4 "DAC_CCR,DAC calibration control register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value"
|
|
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value"
|
|
line.long 0x8 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1"
|
|
bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3"
|
|
bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1"
|
|
bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI"
|
|
hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "DAC_STR1,Sawtooth register"
|
|
hexmask.long.word 0x0 16.--31. 1. "STINCDATA1,DAC CH1 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x0 12. "STDIR1,DAC Channel1 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "STRSTDATA1,DAC Channel 1 Sawtooth reset value"
|
|
line.long 0x4 "DAC_STR2,Sawtooth register"
|
|
hexmask.long.word 0x4 16.--31. 1. "STINCDATA2,DAC CH2 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x4 12. "STDIR2,DAC Channel2 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "STRSTDATA2,DAC Channel 2 Sawtooth reset value"
|
|
line.long 0x8 "DAC_STMODR,Sawtooth Mode register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "STINCTRIGSEL2,DAC Channel 2 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 16.--19. 1. "STRSTTRIGSEL2,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "STINCTRIGSEL1,DAC Channel 1 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "STRSTTRIGSEL1,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
tree.end
|
|
tree "DAC4"
|
|
base ad:0x50001400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DAC_CR,DAC control register"
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)."
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2." "0,1"
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be.." "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software." "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/.."
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)."
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1." "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x0 17. "SWTRIGB2,DAC channel2 software trigger B" "0,1"
|
|
bitfld.long 0x0 16. "SWTRIGB1,DAC channel1 software trigger B" "0,1"
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2.." "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1.." "0,1"
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DHRB,DAC channel1 12-bit right-aligned data B"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x4 20.--31. 1. "DACC1DHRB,DAC channel1 12-bit left-aligned data B"
|
|
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "DACC1DHRB,DAC channel1 8-bit right-aligned data"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0xC 16.--27. 1. "DACC2DHRB,DAC channel2 12-bit right-aligned data"
|
|
hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 20.--31. 1. "DACC2DHRB,DAC channel2 12-bit left-aligned data B"
|
|
hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2."
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DACC2DHRB,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2."
|
|
hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1."
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2."
|
|
hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x0 16.--27. 1. "DACC1DORB,DAC channel1 data output"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1."
|
|
line.long 0x4 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DACC2DORB,DAC channel2 data output"
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2."
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 28. "DORSTAT2,DAC channel 2 output register status bit" "0,1"
|
|
bitfld.long 0x0 27. "DAC2RDY,DAC channel 2 ready status bit" "0,1"
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared.." "0,1"
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." "0,1"
|
|
bitfld.long 0x0 12. "DORSTAT1,DAC channel1 output register status bit" "0,1"
|
|
bitfld.long 0x0 11. "DAC1RDY,DAC channel1 ready status bit" "0,1"
|
|
line.long 0x4 "DAC_CCR,DAC calibration control register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming value"
|
|
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming value"
|
|
line.long 0x8 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x8 25. "SINFORMAT2,Enable signed format for DAC channel2" "0,1"
|
|
bitfld.long 0x8 24. "DMADOUBLE2,DAC Channel2 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 14.--15. "HFSEL,High frequency interface mode selection" "0,1,2,3"
|
|
bitfld.long 0x8 9. "SINFORMAT1,Enable signed format for DAC channel1" "0,1"
|
|
bitfld.long 0x8 8. "DMADOUBLE1,DAC Channel1 DMA double data mode" "0,1"
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write.." "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case the write can.."
|
|
line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI"
|
|
hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "DAC_STR1,Sawtooth register"
|
|
hexmask.long.word 0x0 16.--31. 1. "STINCDATA1,DAC CH1 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x0 12. "STDIR1,DAC Channel1 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "STRSTDATA1,DAC Channel 1 Sawtooth reset value"
|
|
line.long 0x4 "DAC_STR2,Sawtooth register"
|
|
hexmask.long.word 0x4 16.--31. 1. "STINCDATA2,DAC CH2 Sawtooth increment value (12.4 bit format)"
|
|
bitfld.long 0x4 12. "STDIR2,DAC Channel2 Sawtooth direction setting" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "STRSTDATA2,DAC Channel 2 Sawtooth reset value"
|
|
line.long 0x8 "DAC_STMODR,Sawtooth Mode register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "STINCTRIGSEL2,DAC Channel 2 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 16.--19. 1. "STRSTTRIGSEL2,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "STINCTRIGSEL1,DAC Channel 1 Sawtooth Increment trigger selection"
|
|
hexmask.long.byte 0x8 0.--3. 1. "STRSTTRIGSEL1,DAC Channel 1 Sawtooth Reset trigger selection"
|
|
tree.end
|
|
tree.end
|
|
tree "DBGMCU (MCU Debug Component)"
|
|
base ad:0xE0042000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "IDCODE,MCU Device ID Code Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision Identifier"
|
|
hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Device Identifier"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "CR,Debug MCU Configuration Register"
|
|
bitfld.long 0x0 6.--7. "TRACE_MODE,Trace pin assignment control" "0,1,2,3"
|
|
bitfld.long 0x0 5. "TRACE_IOEN,Trace pin assignment control" "0,1"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby Mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
bitfld.long 0x0 0. "DBG_SLEEP,Debug Sleep Mode" "0,1"
|
|
line.long 0x4 "APB1L_FZ,APB Low Freeze Register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIMER_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 30. "DBG_I2C3_STOP,I2C3 SMBUS timeout mode stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 22. "DBG_I2C2_STOP,I2C2 SMBUS timeout mode stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout mode stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Debug Independent Wachdog stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Debug Window Wachdog stopped when Core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Debug RTC stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 4. "DBG_TIMER6_STOP,Debug Timer 6 stopped when Core is halted" "0,1"
|
|
bitfld.long 0x4 3. "DBG_TIM5_STOP,TIM5 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 2. "DBG_TIM4_STOP,TIM4 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is halted" "0,1"
|
|
line.long 0x8 "APB1H_FZ,APB Low Freeze Register 2"
|
|
bitfld.long 0x8 1. "DBG_I2C4_STOP,DBG_I2C4_STOP" "0,1"
|
|
line.long 0xC "APB2_FZ,APB High Freeze Register"
|
|
bitfld.long 0xC 29. "DBG_HRTIM3_STOP,DBG_HRTIM0_STOP" "0,1"
|
|
bitfld.long 0xC 28. "DBG_HRTIM2_STOP,DBG_HRTIM0_STOP" "0,1"
|
|
bitfld.long 0xC 27. "DBG_HRTIM1_STOP,DBG_HRTIM0_STOP" "0,1"
|
|
bitfld.long 0xC 26. "DBG_HRTIM0_STOP,DBG_HRTIM0_STOP" "0,1"
|
|
bitfld.long 0xC 20. "DBG_TIM20_STOP,TIM20counter stopped when core is halted" "0,1"
|
|
bitfld.long 0xC 18. "DBG_TIM17_STOP,TIM17 counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0xC 16. "DBG_TIM15_STOP,TIM15 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0xC 13. "DBG_TIM8_STOP,TIM8 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0xC 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
tree.end
|
|
tree "DMA (Direct Memory Access Controller)"
|
|
base ad:0x0
|
|
tree "DMA1"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 31. "TEIF8,TEIF8" "0,1"
|
|
bitfld.long 0x0 30. "HTIF8,HTIF8" "0,1"
|
|
bitfld.long 0x0 29. "TCIF8,TCIF8" "0,1"
|
|
bitfld.long 0x0 28. "GIF8,GIF8" "0,1"
|
|
bitfld.long 0x0 27. "TEIF7,TEIF7" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,HTIF7" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,TCIF7" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,GIF7" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,TEIF6" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,HTIF6" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,TCIF6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "GIF6,GIF6" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,TEIF5" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,HTIF5" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,TCIF5" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,GIF5" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,TEIF4" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,HTIF4" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,TCIF4" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,GIF4" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,TEIF3" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,HTIF3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,TCIF3" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,GIF3" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,TEIF2" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,HTIF2" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,TCIF2" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,GIF2" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,TEIF1" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,HTIF1" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,TCIF1" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,GIF1" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 31. "TEIF8,TEIF8" "0,1"
|
|
bitfld.long 0x0 30. "HTIF8,HTIF8" "0,1"
|
|
bitfld.long 0x0 29. "TCIF8,TCIF8" "0,1"
|
|
bitfld.long 0x0 28. "GIF8,GIF8" "0,1"
|
|
bitfld.long 0x0 27. "TEIF7,TEIF7" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,HTIF7" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,TCIF7" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,GIF7" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,TEIF6" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,HTIF6" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,TCIF6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "GIF6,GIF6" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,TEIF5" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,HTIF5" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,TCIF5" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,GIF5" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,TEIF4" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,HTIF4" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,TCIF4" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,GIF4" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,TEIF3" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,HTIF3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,TCIF3" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,GIF3" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,TEIF2" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,HTIF2" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,TCIF2" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,GIF2" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,TEIF1" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,HTIF1" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,TCIF1" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,GIF1" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CCR4,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCR5,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "CCR6,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CCR7,DMA channel 6 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "CCR8,DMA channel 7 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CNDTR1,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CNDTR2,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CNDTR3,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "CNDTR4,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "CNDTR5,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CNDTR6,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CNDTR7,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CNDTR8,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CPAR1,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CPAR2,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "CPAR3,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "CPAR4,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CPAR5,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CPAR6,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "CPAR7,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "CPAR8,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CMAR1,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CMAR2,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "CMAR3,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CMAR4,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "CMAR5,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "CMAR6,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "CMAR7,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CMAR8,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,interrupt status register"
|
|
bitfld.long 0x0 31. "TEIF8,TEIF8" "0,1"
|
|
bitfld.long 0x0 30. "HTIF8,HTIF8" "0,1"
|
|
bitfld.long 0x0 29. "TCIF8,TCIF8" "0,1"
|
|
bitfld.long 0x0 28. "GIF8,GIF8" "0,1"
|
|
bitfld.long 0x0 27. "TEIF7,TEIF7" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,HTIF7" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,TCIF7" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,GIF7" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,TEIF6" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,HTIF6" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,TCIF6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "GIF6,GIF6" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,TEIF5" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,HTIF5" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,TCIF5" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,GIF5" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,TEIF4" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,HTIF4" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,TCIF4" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,GIF4" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,TEIF3" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,HTIF3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,TCIF3" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,GIF3" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,TEIF2" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,HTIF2" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,TCIF2" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,GIF2" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,TEIF1" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,HTIF1" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,TCIF1" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,GIF1" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 31. "TEIF8,TEIF8" "0,1"
|
|
bitfld.long 0x0 30. "HTIF8,HTIF8" "0,1"
|
|
bitfld.long 0x0 29. "TCIF8,TCIF8" "0,1"
|
|
bitfld.long 0x0 28. "GIF8,GIF8" "0,1"
|
|
bitfld.long 0x0 27. "TEIF7,TEIF7" "0,1"
|
|
bitfld.long 0x0 26. "HTIF7,HTIF7" "0,1"
|
|
bitfld.long 0x0 25. "TCIF7,TCIF7" "0,1"
|
|
bitfld.long 0x0 24. "GIF7,GIF7" "0,1"
|
|
bitfld.long 0x0 23. "TEIF6,TEIF6" "0,1"
|
|
bitfld.long 0x0 22. "HTIF6,HTIF6" "0,1"
|
|
bitfld.long 0x0 21. "TCIF6,TCIF6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "GIF6,GIF6" "0,1"
|
|
bitfld.long 0x0 19. "TEIF5,TEIF5" "0,1"
|
|
bitfld.long 0x0 18. "HTIF5,HTIF5" "0,1"
|
|
bitfld.long 0x0 17. "TCIF5,TCIF5" "0,1"
|
|
bitfld.long 0x0 16. "GIF5,GIF5" "0,1"
|
|
bitfld.long 0x0 15. "TEIF4,TEIF4" "0,1"
|
|
bitfld.long 0x0 14. "HTIF4,HTIF4" "0,1"
|
|
bitfld.long 0x0 13. "TCIF4,TCIF4" "0,1"
|
|
bitfld.long 0x0 12. "GIF4,GIF4" "0,1"
|
|
bitfld.long 0x0 11. "TEIF3,TEIF3" "0,1"
|
|
bitfld.long 0x0 10. "HTIF3,HTIF3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,TCIF3" "0,1"
|
|
bitfld.long 0x0 8. "GIF3,GIF3" "0,1"
|
|
bitfld.long 0x0 7. "TEIF2,TEIF2" "0,1"
|
|
bitfld.long 0x0 6. "HTIF2,HTIF2" "0,1"
|
|
bitfld.long 0x0 5. "TCIF2,TCIF2" "0,1"
|
|
bitfld.long 0x0 4. "GIF2,GIF2" "0,1"
|
|
bitfld.long 0x0 3. "TEIF1,TEIF1" "0,1"
|
|
bitfld.long 0x0 2. "HTIF1,HTIF1" "0,1"
|
|
bitfld.long 0x0 1. "TCIF1,TCIF1" "0,1"
|
|
bitfld.long 0x0 0. "GIF1,GIF1" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CCR4,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCR5,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "CCR6,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CCR7,DMA channel 6 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "CCR8,DMA channel 7 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM" "0,1"
|
|
bitfld.long 0x0 12.--13. "PL,PL" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "MSIZE,MSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "PSIZE,PSIZE" "0,1,2,3"
|
|
bitfld.long 0x0 7. "MINC,MINC" "0,1"
|
|
bitfld.long 0x0 6. "PINC,PINC" "0,1"
|
|
bitfld.long 0x0 5. "CIRC,CIRC" "0,1"
|
|
bitfld.long 0x0 4. "DIR,DIR" "0,1"
|
|
bitfld.long 0x0 3. "TEIE,TEIE" "0,1"
|
|
bitfld.long 0x0 2. "HTIE,HTIE" "0,1"
|
|
bitfld.long 0x0 1. "TCIE,TCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,channel enable" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CNDTR1,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CNDTR2,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CNDTR3,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "CNDTR4,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "CNDTR5,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "CNDTR6,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CNDTR7,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "CNDTR8,channel x number of data to transfer register"
|
|
hexmask.long.word 0x0 0.--15. 1. "NDT,Number of data items to transfer"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CPAR1,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CPAR2,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "CPAR3,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "CPAR4,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "CPAR5,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "CPAR6,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "CPAR7,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "CPAR8,DMA channel x peripheral address register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CMAR1,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CMAR2,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "CMAR3,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CMAR4,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "CMAR5,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "CMAR6,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "CMAR7,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CMAR8,DMA channel x memory address register"
|
|
hexmask.long 0x0 0.--31. 1. "MA,Memory 1 address (used in case of Double buffer mode)"
|
|
tree.end
|
|
tree.end
|
|
tree "DMAMUX (DMA Request Multiplexer)"
|
|
base ad:0x40020800
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x0 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x4 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x8 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0xC "C3CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0xC 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x10 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x14 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x18 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x1C 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x1C 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x20 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x20 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x24 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x24 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x28 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x28 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x2C 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x2C 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x30 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x30 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x30 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x34 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x34 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x34 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x38 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x38 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x38 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer channel x control register"
|
|
hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input selected"
|
|
hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode it also defines the number of DMA requests to forward.."
|
|
bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector Defines the synchronization event on the selected synchronization input:" "0,1,2,3"
|
|
bitfld.long 0x3C 16. "SE,Synchronous operating mode enable/disable" "0,1"
|
|
bitfld.long 0x3C 9. "EGE,Event generation enable/disable" "0,1"
|
|
bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization event overrun" "0,1"
|
|
hexmask.long.byte 0x3C 0.--6. 1. "DMAREQ_ID,Input DMA request line selected"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x control register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note:.."
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" "0,1,2,3"
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel enable/disable" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event overrun" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input selected"
|
|
line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x control register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note:.."
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" "0,1,2,3"
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel enable/disable" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event overrun" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input selected"
|
|
line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x control register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note:.."
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" "0,1,2,3"
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel enable/disable" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event overrun" "0,1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input selected"
|
|
line.long 0xC "RG3CR,DMAMux - DMA request generator channel x control register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note:.."
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" "0,1,2,3"
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel enable/disable" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event overrun" "0,1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input selected"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "RGSR,DMAMux - DMA request generator status register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OF,Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x while the DMA request generator counter value is lower than GNBREQ. The flag is cleared.."
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COF,Clear trigger event overrun flag Upon setting this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register."
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event flag"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event flag"
|
|
tree.end
|
|
tree "EXTI (Extended Interrupt/Event Controller)"
|
|
base ad:0x40010400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "IMR1,Interrupt mask register"
|
|
bitfld.long 0x0 31. "IM31,Interrupt Mask on line 31" "0,1"
|
|
bitfld.long 0x0 30. "IM30,Interrupt Mask on line 30" "0,1"
|
|
bitfld.long 0x0 29. "IM29,Interrupt Mask on line 29" "0,1"
|
|
bitfld.long 0x0 28. "IM28,Interrupt Mask on line 28" "0,1"
|
|
bitfld.long 0x0 27. "IM27,Interrupt Mask on line 27" "0,1"
|
|
bitfld.long 0x0 26. "IM26,Interrupt Mask on line 26" "0,1"
|
|
bitfld.long 0x0 25. "IM25,Interrupt Mask on line 25" "0,1"
|
|
bitfld.long 0x0 24. "IM24,Interrupt Mask on line 24" "0,1"
|
|
bitfld.long 0x0 23. "IM23,Interrupt Mask on line 23" "0,1"
|
|
bitfld.long 0x0 22. "IM22,Interrupt Mask on line 22" "0,1"
|
|
bitfld.long 0x0 21. "IM21,Interrupt Mask on line 21" "0,1"
|
|
bitfld.long 0x0 20. "IM20,Interrupt Mask on line 20" "0,1"
|
|
bitfld.long 0x0 19. "IM19,Interrupt Mask on line 19" "0,1"
|
|
bitfld.long 0x0 18. "IM18,Interrupt Mask on line 18" "0,1"
|
|
bitfld.long 0x0 17. "IM17,Interrupt Mask on line 17" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "IM16,Interrupt Mask on line 16" "0,1"
|
|
bitfld.long 0x0 15. "IM15,Interrupt Mask on line 15" "0,1"
|
|
bitfld.long 0x0 14. "IM14,Interrupt Mask on line 14" "0,1"
|
|
bitfld.long 0x0 13. "IM13,Interrupt Mask on line 13" "0,1"
|
|
bitfld.long 0x0 12. "IM12,Interrupt Mask on line 12" "0,1"
|
|
bitfld.long 0x0 11. "IM11,Interrupt Mask on line 11" "0,1"
|
|
bitfld.long 0x0 10. "IM10,Interrupt Mask on line 10" "0,1"
|
|
bitfld.long 0x0 9. "IM9,Interrupt Mask on line 9" "0,1"
|
|
bitfld.long 0x0 8. "IM8,Interrupt Mask on line 8" "0,1"
|
|
bitfld.long 0x0 7. "IM7,Interrupt Mask on line 7" "0,1"
|
|
bitfld.long 0x0 6. "IM6,Interrupt Mask on line 6" "0,1"
|
|
bitfld.long 0x0 5. "IM5,Interrupt Mask on line 5" "0,1"
|
|
bitfld.long 0x0 4. "IM4,Interrupt Mask on line 4" "0,1"
|
|
bitfld.long 0x0 3. "IM3,Interrupt Mask on line 3" "0,1"
|
|
bitfld.long 0x0 2. "IM2,Interrupt Mask on line 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IM1,Interrupt Mask on line 1" "0,1"
|
|
bitfld.long 0x0 0. "IM0,Interrupt Mask on line 0" "0,1"
|
|
line.long 0x4 "EMR1,Event mask register"
|
|
bitfld.long 0x4 31. "EM31,Event Mask on line 31" "0,1"
|
|
bitfld.long 0x4 30. "EM30,Event Mask on line 30" "0,1"
|
|
bitfld.long 0x4 29. "EM29,Event Mask on line 29" "0,1"
|
|
bitfld.long 0x4 28. "EM28,Event Mask on line 28" "0,1"
|
|
bitfld.long 0x4 27. "EM27,Event Mask on line 27" "0,1"
|
|
bitfld.long 0x4 26. "EM26,Event Mask on line 26" "0,1"
|
|
bitfld.long 0x4 25. "EM25,Event Mask on line 25" "0,1"
|
|
bitfld.long 0x4 24. "EM24,Event Mask on line 24" "0,1"
|
|
bitfld.long 0x4 23. "EM23,Event Mask on line 23" "0,1"
|
|
bitfld.long 0x4 22. "EM22,Event Mask on line 22" "0,1"
|
|
bitfld.long 0x4 21. "EM21,Event Mask on line 21" "0,1"
|
|
bitfld.long 0x4 20. "EM20,Event Mask on line 20" "0,1"
|
|
bitfld.long 0x4 19. "EM19,Event Mask on line 19" "0,1"
|
|
bitfld.long 0x4 18. "EM18,Event Mask on line 18" "0,1"
|
|
bitfld.long 0x4 17. "EM17,Event Mask on line 17" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "EM16,Event Mask on line 16" "0,1"
|
|
bitfld.long 0x4 15. "EM15,Event Mask on line 15" "0,1"
|
|
bitfld.long 0x4 14. "EM14,Event Mask on line 14" "0,1"
|
|
bitfld.long 0x4 13. "EM13,Event Mask on line 13" "0,1"
|
|
bitfld.long 0x4 12. "EM12,Event Mask on line 12" "0,1"
|
|
bitfld.long 0x4 11. "EM11,Event Mask on line 11" "0,1"
|
|
bitfld.long 0x4 10. "EM10,Event Mask on line 10" "0,1"
|
|
bitfld.long 0x4 9. "EM9,Event Mask on line 9" "0,1"
|
|
bitfld.long 0x4 8. "EM8,Event Mask on line 8" "0,1"
|
|
bitfld.long 0x4 7. "EM7,Event Mask on line 7" "0,1"
|
|
bitfld.long 0x4 6. "EM6,Event Mask on line 6" "0,1"
|
|
bitfld.long 0x4 5. "EM5,Event Mask on line 5" "0,1"
|
|
bitfld.long 0x4 4. "EM4,Event Mask on line 4" "0,1"
|
|
bitfld.long 0x4 3. "EM3,Event Mask on line 3" "0,1"
|
|
bitfld.long 0x4 2. "EM2,Event Mask on line 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EM1,Event Mask on line 1" "0,1"
|
|
bitfld.long 0x4 0. "EM0,Event Mask on line 0" "0,1"
|
|
line.long 0x8 "RTSR1,Rising Trigger selection register"
|
|
bitfld.long 0x8 29.--31. "RT,RT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 22. "RT22,Rising trigger event configuration of line 22" "0,1"
|
|
bitfld.long 0x8 21. "RT21,Rising trigger event configuration of line 21" "0,1"
|
|
bitfld.long 0x8 20. "RT20,Rising trigger event configuration of line 20" "0,1"
|
|
bitfld.long 0x8 19. "RT19,Rising trigger event configuration of line 19" "0,1"
|
|
bitfld.long 0x8 18. "RT18,Rising trigger event configuration of line 18" "0,1"
|
|
bitfld.long 0x8 16. "RT16,Rising trigger event configuration of line 16" "0,1"
|
|
bitfld.long 0x8 15. "RT15,Rising trigger event configuration of line 15" "0,1"
|
|
bitfld.long 0x8 14. "RT14,Rising trigger event configuration of line 14" "0,1"
|
|
bitfld.long 0x8 13. "RT13,Rising trigger event configuration of line 13" "0,1"
|
|
bitfld.long 0x8 12. "RT12,Rising trigger event configuration of line 12" "0,1"
|
|
bitfld.long 0x8 11. "RT11,Rising trigger event configuration of line 11" "0,1"
|
|
bitfld.long 0x8 10. "RT10,Rising trigger event configuration of line 10" "0,1"
|
|
bitfld.long 0x8 9. "RT9,Rising trigger event configuration of line 9" "0,1"
|
|
bitfld.long 0x8 8. "RT8,Rising trigger event configuration of line 8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RT7,Rising trigger event configuration of line 7" "0,1"
|
|
bitfld.long 0x8 6. "RT6,Rising trigger event configuration of line 6" "0,1"
|
|
bitfld.long 0x8 5. "RT5,Rising trigger event configuration of line 5" "0,1"
|
|
bitfld.long 0x8 4. "RT4,Rising trigger event configuration of line 4" "0,1"
|
|
bitfld.long 0x8 3. "RT3,Rising trigger event configuration of line 3" "0,1"
|
|
bitfld.long 0x8 2. "RT2,Rising trigger event configuration of line 2" "0,1"
|
|
bitfld.long 0x8 1. "RT1,Rising trigger event configuration of line 1" "0,1"
|
|
bitfld.long 0x8 0. "RT0,Rising trigger event configuration of line 0" "0,1"
|
|
line.long 0xC "FTSR1,Falling Trigger selection register"
|
|
bitfld.long 0xC 22. "FT22,Falling trigger event configuration of line 22" "0,1"
|
|
bitfld.long 0xC 21. "FT21,Falling trigger event configuration of line 21" "0,1"
|
|
bitfld.long 0xC 20. "FT20,Falling trigger event configuration of line 20" "0,1"
|
|
bitfld.long 0xC 19. "FT19,Falling trigger event configuration of line 19" "0,1"
|
|
bitfld.long 0xC 18. "FT18,Falling trigger event configuration of line 18" "0,1"
|
|
bitfld.long 0xC 16. "FT16,Falling trigger event configuration of line 16" "0,1"
|
|
bitfld.long 0xC 15. "FT15,Falling trigger event configuration of line 15" "0,1"
|
|
bitfld.long 0xC 14. "FT14,Falling trigger event configuration of line 14" "0,1"
|
|
bitfld.long 0xC 13. "FT13,Falling trigger event configuration of line 13" "0,1"
|
|
bitfld.long 0xC 12. "FT12,Falling trigger event configuration of line 12" "0,1"
|
|
bitfld.long 0xC 11. "FT11,Falling trigger event configuration of line 11" "0,1"
|
|
bitfld.long 0xC 10. "FT10,Falling trigger event configuration of line 10" "0,1"
|
|
bitfld.long 0xC 9. "FT9,Falling trigger event configuration of line 9" "0,1"
|
|
bitfld.long 0xC 8. "FT8,Falling trigger event configuration of line 8" "0,1"
|
|
bitfld.long 0xC 7. "FT7,Falling trigger event configuration of line 7" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "FT6,Falling trigger event configuration of line 6" "0,1"
|
|
bitfld.long 0xC 5. "FT5,Falling trigger event configuration of line 5" "0,1"
|
|
bitfld.long 0xC 4. "FT4,Falling trigger event configuration of line 4" "0,1"
|
|
bitfld.long 0xC 3. "FT3,Falling trigger event configuration of line 3" "0,1"
|
|
bitfld.long 0xC 2. "FT2,Falling trigger event configuration of line 2" "0,1"
|
|
bitfld.long 0xC 1. "FT1,Falling trigger event configuration of line 1" "0,1"
|
|
bitfld.long 0xC 0. "FT0,Falling trigger event configuration of line 0" "0,1"
|
|
line.long 0x10 "SWIER1,Software interrupt event register"
|
|
bitfld.long 0x10 22. "SWI22,Software Interrupt on line 22" "0,1"
|
|
bitfld.long 0x10 21. "SWI21,Software Interrupt on line 21" "0,1"
|
|
bitfld.long 0x10 20. "SWI20,Software Interrupt on line 20" "0,1"
|
|
bitfld.long 0x10 19. "SWI19,Software Interrupt on line 19" "0,1"
|
|
bitfld.long 0x10 18. "SWI18,Software Interrupt on line 18" "0,1"
|
|
bitfld.long 0x10 16. "SWI16,Software Interrupt on line 16" "0,1"
|
|
bitfld.long 0x10 15. "SWI15,Software Interrupt on line 15" "0,1"
|
|
bitfld.long 0x10 14. "SWI14,Software Interrupt on line 14" "0,1"
|
|
bitfld.long 0x10 13. "SWI13,Software Interrupt on line 13" "0,1"
|
|
bitfld.long 0x10 12. "SWI12,Software Interrupt on line 12" "0,1"
|
|
bitfld.long 0x10 11. "SWI11,Software Interrupt on line 11" "0,1"
|
|
bitfld.long 0x10 10. "SWI10,Software Interrupt on line 10" "0,1"
|
|
bitfld.long 0x10 9. "SWI9,Software Interrupt on line 9" "0,1"
|
|
bitfld.long 0x10 8. "SWI8,Software Interrupt on line 8" "0,1"
|
|
bitfld.long 0x10 7. "SWI7,Software Interrupt on line 7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "SWI6,Software Interrupt on line 6" "0,1"
|
|
bitfld.long 0x10 5. "SWI5,Software Interrupt on line 5" "0,1"
|
|
bitfld.long 0x10 4. "SWI4,Software Interrupt on line 4" "0,1"
|
|
bitfld.long 0x10 3. "SWI3,Software Interrupt on line 3" "0,1"
|
|
bitfld.long 0x10 2. "SWI2,Software Interrupt on line 2" "0,1"
|
|
bitfld.long 0x10 1. "SWI1,Software Interrupt on line 1" "0,1"
|
|
bitfld.long 0x10 0. "SWI0,Software Interrupt on line 0" "0,1"
|
|
line.long 0x14 "PR1,Pending register"
|
|
bitfld.long 0x14 22. "PIF22,Pending bit 22" "0,1"
|
|
bitfld.long 0x14 21. "PIF21,Pending bit 21" "0,1"
|
|
bitfld.long 0x14 20. "PIF20,Pending bit 20" "0,1"
|
|
bitfld.long 0x14 19. "PIF19,Pending bit 19" "0,1"
|
|
bitfld.long 0x14 18. "PIF18,Pending bit 18" "0,1"
|
|
bitfld.long 0x14 16. "PIF16,Pending bit 16" "0,1"
|
|
bitfld.long 0x14 15. "PIF15,Pending bit 15" "0,1"
|
|
bitfld.long 0x14 14. "PIF14,Pending bit 14" "0,1"
|
|
bitfld.long 0x14 13. "PIF13,Pending bit 13" "0,1"
|
|
bitfld.long 0x14 12. "PIF12,Pending bit 12" "0,1"
|
|
bitfld.long 0x14 11. "PIF11,Pending bit 11" "0,1"
|
|
bitfld.long 0x14 10. "PIF10,Pending bit 10" "0,1"
|
|
bitfld.long 0x14 9. "PIF9,Pending bit 9" "0,1"
|
|
bitfld.long 0x14 8. "PIF8,Pending bit 8" "0,1"
|
|
bitfld.long 0x14 7. "PIF7,Pending bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "PIF6,Pending bit 6" "0,1"
|
|
bitfld.long 0x14 5. "PIF5,Pending bit 5" "0,1"
|
|
bitfld.long 0x14 4. "PIF4,Pending bit 4" "0,1"
|
|
bitfld.long 0x14 3. "PIF3,Pending bit 3" "0,1"
|
|
bitfld.long 0x14 2. "PIF2,Pending bit 2" "0,1"
|
|
bitfld.long 0x14 1. "PIF1,Pending bit 1" "0,1"
|
|
bitfld.long 0x14 0. "PIF0,Pending bit 0" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "IMR2,Interrupt mask register"
|
|
bitfld.long 0x0 11. "IM43,Interrupt Mask on external/internal line 43" "0,1"
|
|
bitfld.long 0x0 10. "IM42,Interrupt Mask on external/internal line 42" "0,1"
|
|
bitfld.long 0x0 9. "IM41,Interrupt Mask on external/internal line 41" "0,1"
|
|
bitfld.long 0x0 8. "IM40,Interrupt Mask on external/internal line 40" "0,1"
|
|
bitfld.long 0x0 7. "IM39,Interrupt Mask on external/internal line 39" "0,1"
|
|
bitfld.long 0x0 6. "IM38,Interrupt Mask on external/internal line 38" "0,1"
|
|
bitfld.long 0x0 5. "IM37,Interrupt Mask on external/internal line 37" "0,1"
|
|
bitfld.long 0x0 4. "IM36,Interrupt Mask on external/internal line 36" "0,1"
|
|
bitfld.long 0x0 3. "IM35,Interrupt Mask on external/internal line 35" "0,1"
|
|
bitfld.long 0x0 2. "IM34,Interrupt Mask on external/internal line 34" "0,1"
|
|
bitfld.long 0x0 1. "IM33,Interrupt Mask on external/internal line 33" "0,1"
|
|
bitfld.long 0x0 0. "IM32,Interrupt Mask on external/internal line 32" "0,1"
|
|
line.long 0x4 "EMR2,Event mask register"
|
|
bitfld.long 0x4 8. "EM40,Event mask on external/internal line 40" "0,1"
|
|
bitfld.long 0x4 7. "EM39,Event mask on external/internal line 39" "0,1"
|
|
bitfld.long 0x4 6. "EM38,Event mask on external/internal line 38" "0,1"
|
|
bitfld.long 0x4 5. "EM37,Event mask on external/internal line 37" "0,1"
|
|
bitfld.long 0x4 4. "EM36,Event mask on external/internal line 36" "0,1"
|
|
bitfld.long 0x4 3. "EM35,Event mask on external/internal line 35" "0,1"
|
|
bitfld.long 0x4 2. "EM34,Event mask on external/internal line 34" "0,1"
|
|
bitfld.long 0x4 1. "EM33,Event mask on external/internal line 33" "0,1"
|
|
bitfld.long 0x4 0. "EM32,Event mask on external/internal line 32" "0,1"
|
|
line.long 0x8 "RTSR2,Rising Trigger selection register"
|
|
bitfld.long 0x8 9. "RT41,Rising trigger event configuration bit of line 41" "0,1"
|
|
bitfld.long 0x8 8. "RT40,Rising trigger event configuration bit of line 40" "0,1"
|
|
bitfld.long 0x8 7. "RT39,Rising trigger event configuration bit of line 39" "0,1"
|
|
bitfld.long 0x8 6. "RT38,Rising trigger event configuration bit of line 38" "0,1"
|
|
bitfld.long 0x8 1. "RT33,Rising trigger event configuration bit of line 32" "0,1"
|
|
bitfld.long 0x8 0. "RT32,Rising trigger event configuration bit of line 32" "0,1"
|
|
line.long 0xC "FTSR2,Falling Trigger selection register"
|
|
bitfld.long 0xC 6. "FT38,Falling trigger event configuration bit of line 38" "0,1"
|
|
bitfld.long 0xC 5. "FT37,Falling trigger event configuration bit of line 37" "0,1"
|
|
bitfld.long 0xC 4. "FT36,Falling trigger event configuration bit of line 36" "0,1"
|
|
bitfld.long 0xC 3. "FT35,Falling trigger event configuration bit of line 35" "0,1"
|
|
line.long 0x10 "SWIER2,Software interrupt event register"
|
|
bitfld.long 0x10 6. "SWI38,Software interrupt on line 38" "0,1"
|
|
bitfld.long 0x10 5. "SWI37,Software interrupt on line 37" "0,1"
|
|
bitfld.long 0x10 4. "SWI36,Software interrupt on line 36" "0,1"
|
|
bitfld.long 0x10 3. "SWI35,Software interrupt on line 35" "0,1"
|
|
line.long 0x14 "PR2,Pending register"
|
|
bitfld.long 0x14 6. "PIF38,Pending interrupt flag on line 38" "0,1"
|
|
bitfld.long 0x14 5. "PIF37,Pending interrupt flag on line 37" "0,1"
|
|
bitfld.long 0x14 4. "PIF36,Pending interrupt flag on line 36" "0,1"
|
|
bitfld.long 0x14 3. "PIF35,Pending interrupt flag on line 35" "0,1"
|
|
tree.end
|
|
tree "FDCAN (FD Controller Area Network)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G471*"))
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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|
newline
|
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
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|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,FDCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,REL"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,MON"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY"
|
|
line.long 0x4 "ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,ETV"
|
|
group.long 0xC++0x17
|
|
line.long 0x0 "DBTP,This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024.."
|
|
bitfld.long 0x0 23. "TDC,TDC" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,DBRP"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,DTSEG1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,DTSEG2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,DSJW"
|
|
line.long 0x4 "TEST,Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control.."
|
|
rbitfld.long 0x4 7. "RX,RX" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,TX" "0,1,2,3"
|
|
bitfld.long 0x4 4. "LBCK,LBCK" "0,1"
|
|
line.long 0x8 "RWD,The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC].."
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,WDV"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,WDC"
|
|
line.long 0xC "CCCR,For details about setting and resetting of single bits see Software initialization."
|
|
bitfld.long 0xC 15. "NISO,NISO" "0,1"
|
|
bitfld.long 0xC 14. "TXP,TXP" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,EFBI" "0,1"
|
|
bitfld.long 0xC 12. "PXHD,PXHD" "0,1"
|
|
bitfld.long 0xC 9. "BRSE,BRSE" "0,1"
|
|
bitfld.long 0xC 8. "FDOE,FDOE" "0,1"
|
|
bitfld.long 0xC 7. "TEST,TEST" "0,1"
|
|
bitfld.long 0xC 6. "DAR,DAR" "0,1"
|
|
bitfld.long 0xC 5. "MON,MON" "0,1"
|
|
bitfld.long 0xC 4. "CSR,CSR" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,CSA" "0,1"
|
|
bitfld.long 0xC 2. "ASM,ASM" "0,1"
|
|
bitfld.long 0xC 1. "CCE,CCE" "0,1"
|
|
bitfld.long 0xC 0. "INIT,INIT" "0,1"
|
|
line.long 0x10 "NBTP,FDCAN_NBTP"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,NSJW"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,NBRP"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,NTSEG1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,NTSEG2"
|
|
line.long 0x14 "TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,TCP"
|
|
bitfld.long 0x14 0.--1. "TSS,TSS" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSC,TSC"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TOCC,FDCAN Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TOP,TOP"
|
|
bitfld.long 0x0 1.--2. "TOS,TOS" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ETOC,ETOC" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TOC,TOC"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CEL"
|
|
bitfld.long 0x0 15. "RP,RP" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,TREC"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,TEC"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TDCV,TDCV"
|
|
bitfld.long 0x0 14. "PXE,PXE" "0,1"
|
|
bitfld.long 0x0 13. "REDL,REDL" "0,1"
|
|
bitfld.long 0x0 12. "RBRS,RBRS" "0,1"
|
|
bitfld.long 0x0 11. "RESI,RESI" "0,1"
|
|
bitfld.long 0x0 8.--10. "DLEC,DLEC" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 7. "BO,BO" "0,1"
|
|
rbitfld.long 0x0 6. "EW,EW" "0,1"
|
|
rbitfld.long 0x0 5. "EP,EP" "0,1"
|
|
rbitfld.long 0x0 3.--4. "ACT,ACT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LEC,LEC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x4 8.--14. 1. "TDCO,TDCO"
|
|
hexmask.long.byte 0x4 0.--6. 1. "TDCF,TDCF"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0.."
|
|
bitfld.long 0x0 23. "ARA,ARA" "0,1"
|
|
bitfld.long 0x0 22. "PED,PED" "0,1"
|
|
bitfld.long 0x0 21. "PEA,PEA" "0,1"
|
|
bitfld.long 0x0 20. "WDI,WDI" "0,1"
|
|
bitfld.long 0x0 19. "BO,BO" "0,1"
|
|
bitfld.long 0x0 18. "EW,EW" "0,1"
|
|
bitfld.long 0x0 17. "EP,EP" "0,1"
|
|
bitfld.long 0x0 16. "ELO,ELO" "0,1"
|
|
bitfld.long 0x0 15. "TOO,TOO" "0,1"
|
|
bitfld.long 0x0 14. "MRAF,MRAF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,TSW" "0,1"
|
|
bitfld.long 0x0 12. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x0 11. "TEFF,TEFF" "0,1"
|
|
bitfld.long 0x0 10. "TEFN,TEFN" "0,1"
|
|
bitfld.long 0x0 9. "TFE,TFE" "0,1"
|
|
bitfld.long 0x0 8. "TCF,TCF" "0,1"
|
|
bitfld.long 0x0 7. "TC,TC" "0,1"
|
|
bitfld.long 0x0 6. "HPM,HPM" "0,1"
|
|
bitfld.long 0x0 5. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 4. "RF1F,RF1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,RF1N" "0,1"
|
|
bitfld.long 0x0 2. "RF0L,RF0L" "0,1"
|
|
bitfld.long 0x0 1. "RF0F,RF0F" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,RF0N" "0,1"
|
|
line.long 0x4 "IE,The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line."
|
|
bitfld.long 0x4 23. "ARAE,ARAE" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,PEDE" "0,1"
|
|
bitfld.long 0x4 21. "PEAE,PEAE" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,WDIE" "0,1"
|
|
bitfld.long 0x4 19. "BOE,BOE" "0,1"
|
|
bitfld.long 0x4 18. "EWE,EWE" "0,1"
|
|
bitfld.long 0x4 17. "EPE,EPE" "0,1"
|
|
bitfld.long 0x4 16. "ELOE,ELOE" "0,1"
|
|
bitfld.long 0x4 15. "TOOE,TOOE" "0,1"
|
|
bitfld.long 0x4 14. "MRAFE,MRAFE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,TSWE" "0,1"
|
|
bitfld.long 0x4 12. "TEFLE,TEFLE" "0,1"
|
|
bitfld.long 0x4 11. "TEFFE,TEFFE" "0,1"
|
|
bitfld.long 0x4 10. "TEFNE,TEFNE" "0,1"
|
|
bitfld.long 0x4 9. "TFEE,TFEE" "0,1"
|
|
bitfld.long 0x4 8. "TCFE,TCFE" "0,1"
|
|
bitfld.long 0x4 7. "TCE,TCE" "0,1"
|
|
bitfld.long 0x4 6. "HPME,HPME" "0,1"
|
|
bitfld.long 0x4 5. "RF1LE,RF1LE" "0,1"
|
|
bitfld.long 0x4 4. "RF1FE,RF1FE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,RF1NE" "0,1"
|
|
bitfld.long 0x4 2. "RF0LE,RF0LE" "0,1"
|
|
bitfld.long 0x4 1. "RF0FE,RF0FE" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,RF0NE" "0,1"
|
|
line.long 0x8 "ILS,The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt.."
|
|
bitfld.long 0x8 6. "PERR,PERR" "0,1"
|
|
bitfld.long 0x8 5. "BERR,BERR" "0,1"
|
|
bitfld.long 0x8 4. "MISC,MISC" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,TFERR" "0,1"
|
|
bitfld.long 0x8 2. "SMSG,SMSG" "0,1"
|
|
bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1"
|
|
bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1"
|
|
line.long 0xC "ILE,Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1."
|
|
bitfld.long 0xC 1. "EINT1,EINT1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,EINT0" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "RXGFC,Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707:.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS"
|
|
bitfld.long 0x0 9. "F0OM,F0OM" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,F1OM" "0,1"
|
|
bitfld.long 0x0 4.--5. "ANFS,ANFS" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,ANFE" "0,1,2,3"
|
|
bitfld.long 0x0 1. "RRFS,RRFS" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,RRFE" "0,1"
|
|
line.long 0x4 "XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,EIDM"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "HPMS,This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages."
|
|
bitfld.long 0x0 15. "FLST,FLST" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,FIDX"
|
|
bitfld.long 0x0 6.--7. "MSI,MSI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "BIDX,BIDX" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,RF0L" "0,1"
|
|
bitfld.long 0x0 24. "F0F,F0F" "0,1"
|
|
bitfld.long 0x0 16.--17. "F0PI,F0PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,F0GI" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,F0FL"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F0AI,F0AI" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
bitfld.long 0x0 25. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 24. "F1F,F1F" "0,1"
|
|
bitfld.long 0x0 16.--17. "F1PI,F1PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,F1GI" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,F1FL"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F1AI,F1AI" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TXBC,FDCAN Tx Buffer Configuration Register"
|
|
bitfld.long 0x0 24. "TFQM,TFQM" "0,1"
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "TXFQS,The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated)."
|
|
bitfld.long 0x0 21. "TFQF,TFQF" "0,1"
|
|
bitfld.long 0x0 16.--17. "TFQPI,TFQPI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,TFFL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x4 0.--2. "TRP,TRP" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x0 0.--2. "AR,AR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 0.--2. "CR,CR" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 0.--2. "TO,TO" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 0.--2. "CF,CF" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 0.--2. "TIE,TIE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 0.--2. "CFIE,CFIE" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x0 24. "EFF,EFF" "0,1"
|
|
bitfld.long 0x0 16.--17. "EFPI,EFPI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,EFGI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "EFFL,EFFL" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x0 0.--1. "EFAI,EFAI" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider. the APB clock could be divided prior to be used by the CAN sub"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "FDCAN3"
|
|
base ad:0x40006C00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,FDCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,REL"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,MON"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY"
|
|
line.long 0x4 "ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,ETV"
|
|
group.long 0xC++0x17
|
|
line.long 0x0 "DBTP,This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024.."
|
|
bitfld.long 0x0 23. "TDC,TDC" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,DBRP"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,DTSEG1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,DTSEG2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,DSJW"
|
|
line.long 0x4 "TEST,Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control.."
|
|
rbitfld.long 0x4 7. "RX,RX" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,TX" "0,1,2,3"
|
|
bitfld.long 0x4 4. "LBCK,LBCK" "0,1"
|
|
line.long 0x8 "RWD,The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC].."
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,WDV"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,WDC"
|
|
line.long 0xC "CCCR,For details about setting and resetting of single bits see Software initialization."
|
|
bitfld.long 0xC 15. "NISO,NISO" "0,1"
|
|
bitfld.long 0xC 14. "TXP,TXP" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,EFBI" "0,1"
|
|
bitfld.long 0xC 12. "PXHD,PXHD" "0,1"
|
|
bitfld.long 0xC 9. "BRSE,BRSE" "0,1"
|
|
bitfld.long 0xC 8. "FDOE,FDOE" "0,1"
|
|
bitfld.long 0xC 7. "TEST,TEST" "0,1"
|
|
bitfld.long 0xC 6. "DAR,DAR" "0,1"
|
|
bitfld.long 0xC 5. "MON,MON" "0,1"
|
|
bitfld.long 0xC 4. "CSR,CSR" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,CSA" "0,1"
|
|
bitfld.long 0xC 2. "ASM,ASM" "0,1"
|
|
bitfld.long 0xC 1. "CCE,CCE" "0,1"
|
|
bitfld.long 0xC 0. "INIT,INIT" "0,1"
|
|
line.long 0x10 "NBTP,FDCAN_NBTP"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,NSJW"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,NBRP"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,NTSEG1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,NTSEG2"
|
|
line.long 0x14 "TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,TCP"
|
|
bitfld.long 0x14 0.--1. "TSS,TSS" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSC,TSC"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TOCC,FDCAN Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TOP,TOP"
|
|
bitfld.long 0x0 1.--2. "TOS,TOS" "0,1,2,3"
|
|
bitfld.long 0x0 0. "ETOC,ETOC" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TOC,TOC"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CEL"
|
|
bitfld.long 0x0 15. "RP,RP" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,TREC"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,TEC"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TDCV,TDCV"
|
|
bitfld.long 0x0 14. "PXE,PXE" "0,1"
|
|
bitfld.long 0x0 13. "REDL,REDL" "0,1"
|
|
bitfld.long 0x0 12. "RBRS,RBRS" "0,1"
|
|
bitfld.long 0x0 11. "RESI,RESI" "0,1"
|
|
bitfld.long 0x0 8.--10. "DLEC,DLEC" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 7. "BO,BO" "0,1"
|
|
rbitfld.long 0x0 6. "EW,EW" "0,1"
|
|
rbitfld.long 0x0 5. "EP,EP" "0,1"
|
|
rbitfld.long 0x0 3.--4. "ACT,ACT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LEC,LEC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x4 8.--14. 1. "TDCO,TDCO"
|
|
hexmask.long.byte 0x4 0.--6. 1. "TDCF,TDCF"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0.."
|
|
bitfld.long 0x0 23. "ARA,ARA" "0,1"
|
|
bitfld.long 0x0 22. "PED,PED" "0,1"
|
|
bitfld.long 0x0 21. "PEA,PEA" "0,1"
|
|
bitfld.long 0x0 20. "WDI,WDI" "0,1"
|
|
bitfld.long 0x0 19. "BO,BO" "0,1"
|
|
bitfld.long 0x0 18. "EW,EW" "0,1"
|
|
bitfld.long 0x0 17. "EP,EP" "0,1"
|
|
bitfld.long 0x0 16. "ELO,ELO" "0,1"
|
|
bitfld.long 0x0 15. "TOO,TOO" "0,1"
|
|
bitfld.long 0x0 14. "MRAF,MRAF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,TSW" "0,1"
|
|
bitfld.long 0x0 12. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x0 11. "TEFF,TEFF" "0,1"
|
|
bitfld.long 0x0 10. "TEFN,TEFN" "0,1"
|
|
bitfld.long 0x0 9. "TFE,TFE" "0,1"
|
|
bitfld.long 0x0 8. "TCF,TCF" "0,1"
|
|
bitfld.long 0x0 7. "TC,TC" "0,1"
|
|
bitfld.long 0x0 6. "HPM,HPM" "0,1"
|
|
bitfld.long 0x0 5. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 4. "RF1F,RF1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,RF1N" "0,1"
|
|
bitfld.long 0x0 2. "RF0L,RF0L" "0,1"
|
|
bitfld.long 0x0 1. "RF0F,RF0F" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,RF0N" "0,1"
|
|
line.long 0x4 "IE,The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line."
|
|
bitfld.long 0x4 23. "ARAE,ARAE" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,PEDE" "0,1"
|
|
bitfld.long 0x4 21. "PEAE,PEAE" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,WDIE" "0,1"
|
|
bitfld.long 0x4 19. "BOE,BOE" "0,1"
|
|
bitfld.long 0x4 18. "EWE,EWE" "0,1"
|
|
bitfld.long 0x4 17. "EPE,EPE" "0,1"
|
|
bitfld.long 0x4 16. "ELOE,ELOE" "0,1"
|
|
bitfld.long 0x4 15. "TOOE,TOOE" "0,1"
|
|
bitfld.long 0x4 14. "MRAFE,MRAFE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,TSWE" "0,1"
|
|
bitfld.long 0x4 12. "TEFLE,TEFLE" "0,1"
|
|
bitfld.long 0x4 11. "TEFFE,TEFFE" "0,1"
|
|
bitfld.long 0x4 10. "TEFNE,TEFNE" "0,1"
|
|
bitfld.long 0x4 9. "TFEE,TFEE" "0,1"
|
|
bitfld.long 0x4 8. "TCFE,TCFE" "0,1"
|
|
bitfld.long 0x4 7. "TCE,TCE" "0,1"
|
|
bitfld.long 0x4 6. "HPME,HPME" "0,1"
|
|
bitfld.long 0x4 5. "RF1LE,RF1LE" "0,1"
|
|
bitfld.long 0x4 4. "RF1FE,RF1FE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,RF1NE" "0,1"
|
|
bitfld.long 0x4 2. "RF0LE,RF0LE" "0,1"
|
|
bitfld.long 0x4 1. "RF0FE,RF0FE" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,RF0NE" "0,1"
|
|
line.long 0x8 "ILS,The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt.."
|
|
bitfld.long 0x8 6. "PERR,PERR" "0,1"
|
|
bitfld.long 0x8 5. "BERR,BERR" "0,1"
|
|
bitfld.long 0x8 4. "MISC,MISC" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,TFERR" "0,1"
|
|
bitfld.long 0x8 2. "SMSG,SMSG" "0,1"
|
|
bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1"
|
|
bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1"
|
|
line.long 0xC "ILE,Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1."
|
|
bitfld.long 0xC 1. "EINT1,EINT1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,EINT0" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "RXGFC,Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707:.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS"
|
|
bitfld.long 0x0 9. "F0OM,F0OM" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,F1OM" "0,1"
|
|
bitfld.long 0x0 4.--5. "ANFS,ANFS" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,ANFE" "0,1,2,3"
|
|
bitfld.long 0x0 1. "RRFS,RRFS" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,RRFE" "0,1"
|
|
line.long 0x4 "XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,EIDM"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "HPMS,This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages."
|
|
bitfld.long 0x0 15. "FLST,FLST" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,FIDX"
|
|
bitfld.long 0x0 6.--7. "MSI,MSI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "BIDX,BIDX" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,RF0L" "0,1"
|
|
bitfld.long 0x0 24. "F0F,F0F" "0,1"
|
|
bitfld.long 0x0 16.--17. "F0PI,F0PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,F0GI" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,F0FL"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F0AI,F0AI" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
bitfld.long 0x0 25. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 24. "F1F,F1F" "0,1"
|
|
bitfld.long 0x0 16.--17. "F1PI,F1PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,F1GI" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,F1FL"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F1AI,F1AI" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TXBC,FDCAN Tx Buffer Configuration Register"
|
|
bitfld.long 0x0 24. "TFQM,TFQM" "0,1"
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "TXFQS,The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated)."
|
|
bitfld.long 0x0 21. "TFQF,TFQF" "0,1"
|
|
bitfld.long 0x0 16.--17. "TFQPI,TFQPI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,TFFL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x4 0.--2. "TRP,TRP" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x0 0.--2. "AR,AR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 0.--2. "CR,CR" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 0.--2. "TO,TO" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 0.--2. "CF,CF" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 0.--2. "TIE,TIE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 0.--2. "CFIE,CFIE" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x0 24. "EFF,EFF" "0,1"
|
|
bitfld.long 0x0 16.--17. "EFPI,EFPI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,EFGI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "EFFL,EFFL" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x0 0.--1. "EFAI,EFAI" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider. the APB clock could be divided prior to be used by the CAN sub"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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|
newline
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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|
newline
|
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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newline
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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|
newline
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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|
newline
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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|
newline
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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|
newline
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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|
newline
|
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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|
newline
|
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
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|
newline
|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
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|
newline
|
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
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|
newline
|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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|
newline
|
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
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|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
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|
newline
|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
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|
newline
|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
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|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
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|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
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|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "FDCAN3"
|
|
base ad:0x40006C00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
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bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
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|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
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|
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
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|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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|
newline
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
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|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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|
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
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|
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
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|
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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|
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|
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
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|
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
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|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
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|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
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|
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bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
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|
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
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|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
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|
newline
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hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
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|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
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|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
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|
newline
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bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
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|
newline
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bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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|
newline
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bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
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|
newline
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bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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|
newline
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
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|
newline
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
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|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
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newline
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
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|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
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|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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|
newline
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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|
newline
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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newline
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
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|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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|
newline
|
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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newline
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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|
newline
|
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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|
newline
|
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
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newline
|
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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|
newline
|
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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|
newline
|
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
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bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "FDCAN3"
|
|
base ad:0x40006C00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "FDCAN3"
|
|
base ad:0x40006C00
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G491*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G4A1*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
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bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
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|
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
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|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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|
newline
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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newline
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
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|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
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|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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newline
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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|
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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newline
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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newline
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
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|
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
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|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
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bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
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|
newline
|
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32GBK1CB*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
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|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
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|
newline
|
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
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|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
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|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
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bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
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|
newline
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bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
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|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
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hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
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hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
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|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
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|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
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|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
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newline
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bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
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|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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|
newline
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bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
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newline
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bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
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|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
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|
newline
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bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
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|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
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newline
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rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
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bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
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newline
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bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
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|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
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hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
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hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
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|
newline
|
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
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hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
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|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
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hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
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bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
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line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
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hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
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line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
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hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
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bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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newline
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bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
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line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
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hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
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group.long 0x40++0xB
|
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line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
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rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
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newline
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
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|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
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bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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newline
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bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
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newline
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bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
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bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
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rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
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rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
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rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
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newline
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bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
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|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
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hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
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hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
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group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
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bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
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newline
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bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
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newline
|
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bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
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bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
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newline
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bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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newline
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bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
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newline
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bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
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bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
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newline
|
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bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
|
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bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
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bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
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bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
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newline
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bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
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bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
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bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
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newline
|
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bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
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bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
|
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bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
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bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
|
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bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
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newline
|
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bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
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newline
|
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bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
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newline
|
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bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
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bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
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bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
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bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
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hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
tree "FDCAN"
|
|
base ad:0x4000A400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*")||cpuis("STM32G473*"))
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,FDCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,REL"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,MON"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY"
|
|
line.long 0x4 "ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,ETV"
|
|
group.long 0xC++0x17
|
|
line.long 0x0 "DBTP,This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024.."
|
|
bitfld.long 0x0 23. "TDC,TDC" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,DBRP"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,DTSEG1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,DTSEG2"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,DSJW"
|
|
line.long 0x4 "TEST,Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control.."
|
|
rbitfld.long 0x4 7. "RX,RX" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,TX" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,LBCK" "0,1"
|
|
line.long 0x8 "RWD,The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC].."
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,WDV"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,WDC"
|
|
line.long 0xC "CCCR,For details about setting and resetting of single bits see Software initialization."
|
|
bitfld.long 0xC 15. "NISO,NISO" "0,1"
|
|
bitfld.long 0xC 14. "TXP,TXP" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,EFBI" "0,1"
|
|
bitfld.long 0xC 12. "PXHD,PXHD" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,BRSE" "0,1"
|
|
bitfld.long 0xC 8. "FDOE,FDOE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,TEST" "0,1"
|
|
bitfld.long 0xC 6. "DAR,DAR" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,MON" "0,1"
|
|
bitfld.long 0xC 4. "CSR,CSR" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,CSA" "0,1"
|
|
bitfld.long 0xC 2. "ASM,ASM" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,CCE" "0,1"
|
|
bitfld.long 0xC 0. "INIT,INIT" "0,1"
|
|
line.long 0x10 "NBTP,FDCAN_NBTP"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,NSJW"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,NBRP"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,NTSEG1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,NTSEG2"
|
|
line.long 0x14 "TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,TCP"
|
|
bitfld.long 0x14 0.--1. "TSS,TSS" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSC,TSC"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TOCC,FDCAN Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TOP,TOP"
|
|
bitfld.long 0x0 1.--2. "TOS,TOS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "ETOC,ETOC" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TOC,TOC"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CEL"
|
|
bitfld.long 0x0 15. "RP,RP" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,TREC"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,TEC"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TDCV,TDCV"
|
|
bitfld.long 0x0 14. "PXE,PXE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "REDL,REDL" "0,1"
|
|
bitfld.long 0x0 12. "RBRS,RBRS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RESI,RESI" "0,1"
|
|
bitfld.long 0x0 8.--10. "DLEC,DLEC" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "BO,BO" "0,1"
|
|
rbitfld.long 0x0 6. "EW,EW" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "EP,EP" "0,1"
|
|
rbitfld.long 0x0 3.--4. "ACT,ACT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LEC,LEC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x4 8.--14. 1. "TDCO,TDCO"
|
|
hexmask.long.byte 0x4 0.--6. 1. "TDCF,TDCF"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0.."
|
|
bitfld.long 0x0 23. "ARA,ARA" "0,1"
|
|
bitfld.long 0x0 22. "PED,PED" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,PEA" "0,1"
|
|
bitfld.long 0x0 20. "WDI,WDI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,BO" "0,1"
|
|
bitfld.long 0x0 18. "EW,EW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,EP" "0,1"
|
|
bitfld.long 0x0 16. "ELO,ELO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,TOO" "0,1"
|
|
bitfld.long 0x0 14. "MRAF,MRAF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,TSW" "0,1"
|
|
bitfld.long 0x0 12. "TEFL,TEFL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,TEFF" "0,1"
|
|
bitfld.long 0x0 10. "TEFN,TEFN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,TFE" "0,1"
|
|
bitfld.long 0x0 8. "TCF,TCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,TC" "0,1"
|
|
bitfld.long 0x0 6. "HPM,HPM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 4. "RF1F,RF1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,RF1N" "0,1"
|
|
bitfld.long 0x0 2. "RF0L,RF0L" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,RF0F" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,RF0N" "0,1"
|
|
line.long 0x4 "IE,The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line."
|
|
bitfld.long 0x4 23. "ARAE,ARAE" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,PEDE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,PEAE" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,WDIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,BOE" "0,1"
|
|
bitfld.long 0x4 18. "EWE,EWE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,EPE" "0,1"
|
|
bitfld.long 0x4 16. "ELOE,ELOE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,TOOE" "0,1"
|
|
bitfld.long 0x4 14. "MRAFE,MRAFE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,TSWE" "0,1"
|
|
bitfld.long 0x4 12. "TEFLE,TEFLE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,TEFFE" "0,1"
|
|
bitfld.long 0x4 10. "TEFNE,TEFNE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,TFEE" "0,1"
|
|
bitfld.long 0x4 8. "TCFE,TCFE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,TCE" "0,1"
|
|
bitfld.long 0x4 6. "HPME,HPME" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,RF1LE" "0,1"
|
|
bitfld.long 0x4 4. "RF1FE,RF1FE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,RF1NE" "0,1"
|
|
bitfld.long 0x4 2. "RF0LE,RF0LE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,RF0FE" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,RF0NE" "0,1"
|
|
line.long 0x8 "ILS,The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt.."
|
|
bitfld.long 0x8 6. "PERR,PERR" "0,1"
|
|
bitfld.long 0x8 5. "BERR,BERR" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,MISC" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,TFERR" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,SMSG" "0,1"
|
|
bitfld.long 0x8 1. "RxFIFO1,RxFIFO1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RxFIFO0,RxFIFO0" "0,1"
|
|
line.long 0xC "ILE,Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1."
|
|
bitfld.long 0xC 1. "EINT1,EINT1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,EINT0" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "RXGFC,Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707:.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,LSE"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,LSS"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,F0OM" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,F1OM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,ANFS" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,ANFE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,RRFS" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,RRFE" "0,1"
|
|
line.long 0x4 "XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,EIDM"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "HPMS,This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages."
|
|
bitfld.long 0x0 15. "FLST,FLST" "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,FIDX"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,MSI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "BIDX,BIDX" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,RF0L" "0,1"
|
|
bitfld.long 0x0 24. "F0F,F0F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,F0PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,F0GI" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,F0FL"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F0AI,F0AI" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
bitfld.long 0x0 25. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x0 24. "F1F,F1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,F1PI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,F1GI" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,F1FL"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x0 0.--2. "F1AI,F1AI" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TXBC,FDCAN Tx Buffer Configuration Register"
|
|
bitfld.long 0x0 24. "TFQM,TFQM" "0,1"
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "TXFQS,The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated)."
|
|
bitfld.long 0x0 21. "TFQF,TFQF" "0,1"
|
|
bitfld.long 0x0 16.--17. "TFQPI,TFQPI" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,TFGI" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,TFFL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x4 0.--2. "TRP,TRP" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x0 0.--2. "AR,AR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 0.--2. "CR,CR" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 0.--2. "TO,TO" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 0.--2. "CF,CF" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 0.--2. "TIE,TIE" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 0.--2. "CFIE,CFIE" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x0 24. "EFF,EFF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,EFPI" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,EFGI" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,EFFL" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x0 0.--1. "EFAI,EFAI" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider. the APB clock could be divided prior to be used by the CAN sub"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ACR,Access control register"
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug software enable" "0,1"
|
|
bitfld.long 0x0 14. "SLEEP_PD,Flash Power-down mode during Low-power sleep mode" "0,1"
|
|
bitfld.long 0x0 13. "RUN_PD,Flash Power-down mode during Low-power run mode" "0,1"
|
|
bitfld.long 0x0 12. "DCRST,Data cache reset" "0,1"
|
|
bitfld.long 0x0 11. "ICRST,Instruction cache reset" "0,1"
|
|
bitfld.long 0x0 10. "DCEN,Data cache enable" "0,1"
|
|
bitfld.long 0x0 9. "ICEN,Instruction cache enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Latency"
|
|
wgroup.long 0x4++0xB
|
|
line.long 0x0 "PDKEYR,Power down key register"
|
|
hexmask.long 0x0 0.--31. 1. "PDKEYR,RUN_PD in FLASH_ACR key"
|
|
line.long 0x4 "KEYR,Flash key register"
|
|
hexmask.long 0x4 0.--31. 1. "KEYR,KEYR"
|
|
line.long 0x8 "OPTKEYR,Option byte key register"
|
|
hexmask.long 0x8 0.--31. 1. "OPTKEYR,Option byte key"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SR,Status register"
|
|
rbitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
bitfld.long 0x0 15. "OPTVERR,Option validity error" "0,1"
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
bitfld.long 0x0 9. "FASTERR,Fast programming error" "0,1"
|
|
bitfld.long 0x0 8. "MISERR,Fast programming data miss error" "0,1"
|
|
bitfld.long 0x0 7. "PGSERR,Programming sequence error" "0,1"
|
|
bitfld.long 0x0 6. "SIZERR,Size error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PGAERR,Programming alignment error" "0,1"
|
|
bitfld.long 0x0 4. "WRPERR,Write protected error" "0,1"
|
|
bitfld.long 0x0 3. "PROGERR,Programming error" "0,1"
|
|
bitfld.long 0x0 1. "OPERR,Operation error" "0,1"
|
|
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
|
|
line.long 0x4 "CR,Flash control register"
|
|
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
|
|
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
|
|
bitfld.long 0x4 28. "SEC_PROT1,SEC_PROT1" "0,1"
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,Force the option byte loading" "0,1"
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt enable" "0,1"
|
|
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 24. "EOPIE,End of operation interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "FSTPG,Fast programming" "0,1"
|
|
bitfld.long 0x4 17. "OPTSTRT,Options modification start" "0,1"
|
|
bitfld.long 0x4 16. "STRT,Start" "0,1"
|
|
hexmask.long.byte 0x4 3.--9. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER1,Bank 1 Mass erase" "0,1"
|
|
bitfld.long 0x4 1. "PER,Page erase" "0,1"
|
|
bitfld.long 0x4 0. "PG,Programming" "0,1"
|
|
line.long 0x8 "ECCR,Flash ECC register"
|
|
bitfld.long 0x8 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x8 30. "ECCC,ECC correction" "0,1"
|
|
bitfld.long 0x8 29. "ECCD2,ECC2 detection" "0,1"
|
|
bitfld.long 0x8 28. "ECCC2,ECC correction" "0,1"
|
|
bitfld.long 0x8 24. "ECCIE,ECCIE" "0,1"
|
|
rbitfld.long 0x8 22. "SYSF_ECC,SYSF_ECC" "0,1"
|
|
rbitfld.long 0x8 21. "BK_ECC,BK_ECC" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--18. 1. "ADDR_ECC,ECC fail address"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "OPTR,Flash option register"
|
|
bitfld.long 0x0 30. "IRHEN,IRHEN" "0,1"
|
|
bitfld.long 0x0 28.--29. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
bitfld.long 0x0 27. "nBOOT0,nBOOT0" "0,1"
|
|
bitfld.long 0x0 26. "nSWBOOT0,nSWBOOT0" "0,1"
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
bitfld.long 0x0 25. "CCMSRAM_RST,CCM SRAM Erase when system reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G491*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G4A1*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32GBK1CB*"))
|
|
bitfld.long 0x0 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
endif
|
|
bitfld.long 0x0 24. "SRAM2_PE,SRAM2 parity check enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "nBOOT1,Boot configuration" "0,1"
|
|
sif (cpuis("STM32G473*"))
|
|
bitfld.long 0x0 22. "DBANK,DBANK" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
bitfld.long 0x0 20. "BFB2,Dual-bank boot" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0,1"
|
|
bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0,1"
|
|
bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0,1"
|
|
sif (cpuis("STM32G473*"))
|
|
bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G491*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G4A1*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32GBK1CB*"))
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog selection" "0,1"
|
|
endif
|
|
bitfld.long 0x0 14. "nRST_SHDW,nRST_SHDW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "nRST_STDBY,nRST_STDBY" "0,1"
|
|
bitfld.long 0x0 12. "nRST_STOP,nRST_STOP" "0,1"
|
|
bitfld.long 0x0 8.--10. "BOR_LEV,BOR reset Level" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDP,Read protection level"
|
|
line.long 0x4 "PCROP1SR,Flash Bank 1 PCROP Start address register"
|
|
hexmask.long.word 0x4 0.--14. 1. "PCROP1_STRT,Bank 1 PCROP area start offset"
|
|
line.long 0x8 "PCROP1ER,Flash Bank 1 PCROP End address register"
|
|
bitfld.long 0x8 31. "PCROP_RDP,PCROP area preserved when RDP level decreased" "0,1"
|
|
hexmask.long.word 0x8 0.--14. 1. "PCROP1_END,Bank 1 PCROP area end offset"
|
|
line.long 0xC "WRP1AR,Flash Bank 1 WRP area A address register"
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP1A_END,Bank 1 WRP first area A end offset"
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP1A_STRT,Bank 1 WRP first area start offset"
|
|
line.long 0x10 "WRP1BR,Flash Bank 1 WRP area B address register"
|
|
hexmask.long.byte 0x10 16.--22. 1. "WRP1B_END,Bank 1 WRP second area B start offset"
|
|
hexmask.long.byte 0x10 0.--6. 1. "WRP1B_STRT,Bank 1 WRP second area B end offset"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "SEC1R,securable area bank1 register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,BOOT_LOCK" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE1,SEC_SIZE1"
|
|
tree.end
|
|
tree "FMAC (Filter Math Accelerator)"
|
|
base ad:0x40021400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "X1BUFCFG,FMAC X1 Buffer Configuration register"
|
|
bitfld.long 0x0 24.--25. "FULL_WM,FULL_WM" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--15. 1. "X1_BUF_SIZE,X1_BUF_SIZE"
|
|
hexmask.long.byte 0x0 0.--7. 1. "X1_BASE,X1_BASE"
|
|
line.long 0x4 "X2BUFCFG,FMAC X2 Buffer Configuration register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "X2_BUF_SIZE,X1_BUF_SIZE"
|
|
hexmask.long.byte 0x4 0.--7. 1. "X2_BASE,X1_BASE"
|
|
line.long 0x8 "YBUFCFG,FMAC Y Buffer Configuration register"
|
|
bitfld.long 0x8 24.--25. "EMPTY_WM,EMPTY_WM" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--15. 1. "Y_BUF_SIZE,X1_BUF_SIZE"
|
|
hexmask.long.byte 0x8 0.--7. 1. "Y_BASE,X1_BASE"
|
|
line.long 0xC "PARAM,FMAC Parameter register"
|
|
bitfld.long 0xC 31. "START,START" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. "FUNC,FUNC"
|
|
hexmask.long.byte 0xC 16.--23. 1. "R,R"
|
|
hexmask.long.byte 0xC 8.--15. 1. "Q,Q"
|
|
hexmask.long.byte 0xC 0.--7. 1. "P,P"
|
|
line.long 0x10 "CR,FMAC Control register"
|
|
bitfld.long 0x10 16. "RESET,RESET" "0,1"
|
|
bitfld.long 0x10 15. "CLIPEN,CLIPEN" "0,1"
|
|
bitfld.long 0x10 9. "DMAWEN,DMAWEN" "0,1"
|
|
bitfld.long 0x10 8. "DMAREN,DMAREN" "0,1"
|
|
bitfld.long 0x10 4. "SATIEN,SATIEN" "0,1"
|
|
bitfld.long 0x10 3. "UNFLIEN,UNFLIEN" "0,1"
|
|
bitfld.long 0x10 2. "OVFLIEN,OVFLIEN" "0,1"
|
|
bitfld.long 0x10 1. "WIEN,WIEN" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RIEN,RIEN" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SR,FMAC Status register"
|
|
bitfld.long 0x0 10. "SAT,SAT" "0,1"
|
|
bitfld.long 0x0 9. "UNFL,UNFL" "0,1"
|
|
bitfld.long 0x0 8. "OVFL,OVFL" "0,1"
|
|
bitfld.long 0x0 1. "X1FULL,X1FULL" "0,1"
|
|
bitfld.long 0x0 0. "YEMPTY,YEMPTY" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "WDATA,FMAC Write Data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RDATA,FMAC Read Data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RDATA,RDATA"
|
|
tree.end
|
|
sif (cpuis("STM32G473*")||cpuis("STM32G474*")||cpuis("STM32G483*")||cpuis("STM32G484*"))
|
|
tree "FMC (Flexible Memory Controller)"
|
|
base ad:0xA0000000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "BCR1,SRAM/NOR-Flash chip-select control register 1"
|
|
bitfld.long 0x0 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x0 21. "WFDIS,WFDIS" "0,1"
|
|
bitfld.long 0x0 20. "CCLKEN,CCLKEN" "0,1"
|
|
bitfld.long 0x0 19. "CBURSTRW,CBURSTRW" "0,1"
|
|
bitfld.long 0x0 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "ASYNCWAIT,ASYNCWAIT" "0,1"
|
|
bitfld.long 0x0 14. "EXTMOD,EXTMOD" "0,1"
|
|
bitfld.long 0x0 13. "WAITEN,WAITEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WREN,WREN" "0,1"
|
|
bitfld.long 0x0 11. "WAITCFG,WAITCFG" "0,1"
|
|
bitfld.long 0x0 9. "WAITPOL,WAITPOL" "0,1"
|
|
bitfld.long 0x0 8. "BURSTEN,BURSTEN" "0,1"
|
|
bitfld.long 0x0 6. "FACCEN,FACCEN" "0,1"
|
|
bitfld.long 0x0 4.--5. "MWID,MWID" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MTYP,MTYP" "0,1,2,3"
|
|
bitfld.long 0x0 1. "MUXEN,MUXEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MBKEN,MBKEN" "0,1"
|
|
line.long 0x4 "BTR1,SRAM/NOR-Flash chip-select timing register 1"
|
|
bitfld.long 0x4 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--27. 1. "DATLAT,DATLAT"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,CLKDIV"
|
|
hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x4 0.--3. 1. "ADDSET,ADDSET"
|
|
line.long 0x8 "BCR2,SRAM/NOR-Flash chip-select control register 2"
|
|
bitfld.long 0x8 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x8 21. "WFDIS,WFDIS" "0,1"
|
|
bitfld.long 0x8 20. "CCLKEN,CCLKEN" "0,1"
|
|
bitfld.long 0x8 19. "CBURSTRW,CBURSTRW" "0,1"
|
|
bitfld.long 0x8 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "ASYNCWAIT,ASYNCWAIT" "0,1"
|
|
bitfld.long 0x8 14. "EXTMOD,EXTMOD" "0,1"
|
|
bitfld.long 0x8 13. "WAITEN,WAITEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "WREN,WREN" "0,1"
|
|
bitfld.long 0x8 11. "WAITCFG,WAITCFG" "0,1"
|
|
bitfld.long 0x8 9. "WAITPOL,WAITPOL" "0,1"
|
|
bitfld.long 0x8 8. "BURSTEN,BURSTEN" "0,1"
|
|
bitfld.long 0x8 6. "FACCEN,FACCEN" "0,1"
|
|
bitfld.long 0x8 4.--5. "MWID,MWID" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "MTYP,MTYP" "0,1,2,3"
|
|
bitfld.long 0x8 1. "MUXEN,MUXEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "MBKEN,MBKEN" "0,1"
|
|
line.long 0xC "BTR2,SRAM/NOR-Flash chip-select timing register 2"
|
|
bitfld.long 0xC 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0xC 24.--27. 1. "DATLAT,DATLAT"
|
|
hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,CLKDIV"
|
|
hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0xC 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0xC 0.--3. 1. "ADDSET,ADDSET"
|
|
line.long 0x10 "BCR3,SRAM/NOR-Flash chip-select control register 3"
|
|
bitfld.long 0x10 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x10 21. "WFDIS,WFDIS" "0,1"
|
|
bitfld.long 0x10 20. "CCLKEN,CCLKEN" "0,1"
|
|
bitfld.long 0x10 19. "CBURSTRW,CBURSTRW" "0,1"
|
|
bitfld.long 0x10 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 15. "ASYNCWAIT,ASYNCWAIT" "0,1"
|
|
bitfld.long 0x10 14. "EXTMOD,EXTMOD" "0,1"
|
|
bitfld.long 0x10 13. "WAITEN,WAITEN" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "WREN,WREN" "0,1"
|
|
bitfld.long 0x10 11. "WAITCFG,WAITCFG" "0,1"
|
|
bitfld.long 0x10 9. "WAITPOL,WAITPOL" "0,1"
|
|
bitfld.long 0x10 8. "BURSTEN,BURSTEN" "0,1"
|
|
bitfld.long 0x10 6. "FACCEN,FACCEN" "0,1"
|
|
bitfld.long 0x10 4.--5. "MWID,MWID" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "MTYP,MTYP" "0,1,2,3"
|
|
bitfld.long 0x10 1. "MUXEN,MUXEN" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "MBKEN,MBKEN" "0,1"
|
|
line.long 0x14 "BTR3,SRAM/NOR-Flash chip-select timing register 3"
|
|
bitfld.long 0x14 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x14 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x14 24.--27. 1. "DATLAT,DATLAT"
|
|
hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,CLKDIV"
|
|
hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x14 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ADDSET,ADDSET"
|
|
line.long 0x18 "BCR4,SRAM/NOR-Flash chip-select control register 4"
|
|
bitfld.long 0x18 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x18 21. "WFDIS,WFDIS" "0,1"
|
|
bitfld.long 0x18 20. "CCLKEN,CCLKEN" "0,1"
|
|
bitfld.long 0x18 19. "CBURSTRW,CBURSTRW" "0,1"
|
|
bitfld.long 0x18 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 15. "ASYNCWAIT,ASYNCWAIT" "0,1"
|
|
bitfld.long 0x18 14. "EXTMOD,EXTMOD" "0,1"
|
|
bitfld.long 0x18 13. "WAITEN,WAITEN" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "WREN,WREN" "0,1"
|
|
bitfld.long 0x18 11. "WAITCFG,WAITCFG" "0,1"
|
|
bitfld.long 0x18 9. "WAITPOL,WAITPOL" "0,1"
|
|
bitfld.long 0x18 8. "BURSTEN,BURSTEN" "0,1"
|
|
bitfld.long 0x18 6. "FACCEN,FACCEN" "0,1"
|
|
bitfld.long 0x18 4.--5. "MWID,MWID" "0,1,2,3"
|
|
bitfld.long 0x18 2.--3. "MTYP,MTYP" "0,1,2,3"
|
|
bitfld.long 0x18 1. "MUXEN,MUXEN" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "MBKEN,MBKEN" "0,1"
|
|
line.long 0x1C "BTR4,SRAM/NOR-Flash chip-select timing register 4"
|
|
bitfld.long 0x1C 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x1C 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,DATLAT"
|
|
hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,CLKDIV"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,ADDSET"
|
|
line.long 0x20 "PCSCNTR,PSRAM chip select counter register"
|
|
bitfld.long 0x20 19. "CNTB4EN,CNTB4EN" "0,1"
|
|
bitfld.long 0x20 18. "CNTB3EN,CNTB3EN" "0,1"
|
|
bitfld.long 0x20 17. "CNTB2EN,CNTB2EN" "0,1"
|
|
bitfld.long 0x20 16. "CNTB1EN,CNTB1EN" "0,1"
|
|
hexmask.long.word 0x20 0.--15. 1. "CSCOUNT,CSCOUNT"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "PCR,PC Card/NAND Flash control register 3"
|
|
bitfld.long 0x0 17.--19. "ECCPS,ECCPS" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 13.--16. 1. "TAR,TAR"
|
|
hexmask.long.byte 0x0 9.--12. 1. "TCLR,TCLR"
|
|
bitfld.long 0x0 6. "ECCEN,ECCEN" "0,1"
|
|
bitfld.long 0x0 4.--5. "PWID,PWID" "0,1,2,3"
|
|
bitfld.long 0x0 3. "PTYP,PTYP" "0,1"
|
|
bitfld.long 0x0 2. "PBKEN,PBKEN" "0,1"
|
|
bitfld.long 0x0 1. "PWAITEN,PWAITEN" "0,1"
|
|
line.long 0x4 "SR,FIFO status and interrupt register 3"
|
|
rbitfld.long 0x4 6. "FEMPT,FEMPT" "0,1"
|
|
bitfld.long 0x4 5. "IFEN,IFEN" "0,1"
|
|
bitfld.long 0x4 4. "ILEN,ILEN" "0,1"
|
|
bitfld.long 0x4 3. "IREN,IREN" "0,1"
|
|
bitfld.long 0x4 2. "IFS,IFS" "0,1"
|
|
bitfld.long 0x4 1. "ILS,ILS" "0,1"
|
|
bitfld.long 0x4 0. "IRS,IRS" "0,1"
|
|
line.long 0x8 "PMEM,Common memory space timing register 3"
|
|
hexmask.long.byte 0x8 24.--31. 1. "MEMHIZx,MEMHIZx"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MEMHOLDx,MEMHOLDx"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MEMWAITx,MEMWAITx"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MEMSETx,MEMSETx"
|
|
line.long 0xC "PATT,Attribute memory space timing register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. "ATTHIZx,ATTHIZx"
|
|
hexmask.long.byte 0xC 16.--23. 1. "ATTHOLDx,ATTHOLDx"
|
|
hexmask.long.byte 0xC 8.--15. 1. "ATTWAITx,ATTWAITx"
|
|
hexmask.long.byte 0xC 0.--7. 1. "ATTSETx,ATTSETx"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "ECCR,ECC result register 3"
|
|
hexmask.long 0x0 0.--31. 1. "ECCx,ECCx"
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "BWTR1,SRAM/NOR-Flash write timing registers 1"
|
|
bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET"
|
|
group.long 0x10C++0x3
|
|
line.long 0x0 "BWTR2,SRAM/NOR-Flash write timing registers 2"
|
|
bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET"
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "BWTR3,SRAM/NOR-Flash write timing registers 3"
|
|
bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET"
|
|
group.long 0x11C++0x3
|
|
line.long 0x0 "BWTR4,SRAM/NOR-Flash write timing registers 4"
|
|
bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST"
|
|
hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET"
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General Purpose Inputs/Outputs)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x48000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
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|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
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bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
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bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
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|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
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bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
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wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
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bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
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bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
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bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
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bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
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bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
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bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
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|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
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|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
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bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
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|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
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hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
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wgroup.long 0x28++0x3
|
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line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
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bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
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bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
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bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
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bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
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bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
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bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
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bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
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bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
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bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
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bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
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bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
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bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x48000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
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bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
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bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
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bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
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bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x48000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOD"
|
|
base ad:0x48000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOE"
|
|
base ad:0x48001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x48001400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOG"
|
|
base ad:0x48001800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFRL7,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFRL6,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFRL5,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFRL4,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFRL3,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFRL2,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFRL1,Alternate function selection for port x bit y (y = 0..7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFRL0,Alternate function selection for port x bit y (y = 0..7)"
|
|
line.long 0x8 "AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFRH15,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFRH14,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFRH13,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFRH12,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFRH11,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFRH10,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFRH9,Alternate function selection for port x bit y (y = 8..15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFRH8,Alternate function selection for port x bit y (y = 8..15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("STM32G474*")||cpuis("STM32G484*"))
|
|
tree "HRTIM (High-Resolution Timer)"
|
|
base ad:0x0
|
|
tree "HRTIM_Common"
|
|
base ad:0x40016B80
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,Control Register 1"
|
|
bitfld.long 0x0 25.--27. "AD4USRC,ADC Trigger 4 Update Source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 22.--24. "AD3USRC,ADC Trigger 3 Update Source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19.--21. "AD2USRC,ADC Trigger 2 Update Source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "AD1USRC,ADC Trigger 1 Update Source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "TFUDIS,Timer f Update Disable" "0,1"
|
|
bitfld.long 0x0 5. "TEUDIS,Timer E Update Disable" "0,1"
|
|
bitfld.long 0x0 4. "TDUDIS,Timer D Update Disable" "0,1"
|
|
bitfld.long 0x0 3. "TCUDIS,Timer C Update Disable" "0,1"
|
|
bitfld.long 0x0 2. "TBUDIS,Timer B Update Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAUDIS,Timer A Update Disable" "0,1"
|
|
bitfld.long 0x0 0. "MUDIS,Master Update Disable" "0,1"
|
|
line.long 0x4 "CR2,Control Register 2"
|
|
bitfld.long 0x4 21. "SWPF,Swap Timer F outputs" "0,1"
|
|
bitfld.long 0x4 20. "SWPE,Swap Timer E outputs" "0,1"
|
|
bitfld.long 0x4 19. "SWPD,Swap Timer D outputs" "0,1"
|
|
bitfld.long 0x4 18. "SWPC,Swap Timer C outputs" "0,1"
|
|
bitfld.long 0x4 17. "SWPB,Swap Timer B outputs" "0,1"
|
|
bitfld.long 0x4 16. "SWPA,Swap Timer A outputs" "0,1"
|
|
bitfld.long 0x4 14. "TFRST,Timer f counter software reset" "0,1"
|
|
bitfld.long 0x4 13. "TERST,Timer E counter software reset" "0,1"
|
|
bitfld.long 0x4 12. "TDRST,Timer D counter software reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TCRST,Timer C counter software reset" "0,1"
|
|
bitfld.long 0x4 10. "TBRST,Timer B counter software reset" "0,1"
|
|
bitfld.long 0x4 9. "TARST,Timer A counter software reset" "0,1"
|
|
bitfld.long 0x4 8. "MRST,Master Counter software reset" "0,1"
|
|
bitfld.long 0x4 6. "TFSWU,Timer f Software Update" "0,1"
|
|
bitfld.long 0x4 5. "TESWU,Timer E Software Update" "0,1"
|
|
bitfld.long 0x4 4. "TDSWU,Timer D Software Update" "0,1"
|
|
bitfld.long 0x4 3. "TCSWU,Timer C Software Update" "0,1"
|
|
bitfld.long 0x4 2. "TBSWU,Timer B Software Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TASWU,Timer A Software update" "0,1"
|
|
bitfld.long 0x4 0. "MSWU,Master Timer Software update" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 17. "BMPER,Burst mode Period Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 16. "DLLRDY,DLL Ready Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "FLT6,Fault 6 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 5. "SYSFLT,System Fault Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "FLT5,Fault 5 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "FLT4,Fault 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "FLT3,Fault 3 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 1. "FLT2,Fault 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "FLT1,Fault 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 17. "BMPERC,Burst mode period flag Clear" "0,1"
|
|
bitfld.long 0x0 16. "DLLRDYC,DLL Ready Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "FLT6C,Fault 6 Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 5. "SYSFLTC,System Fault Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 4. "FLT5C,Fault 5 Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "FLT4C,Fault 4 Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "FLT3C,Fault 3 Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "FLT2C,Fault 2 Interrupt Flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "FLT1C,Fault 1 Interrupt Flag Clear" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "BMPERIE,Burst mode period Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "DLLRDYIE,DLL Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "FLT6IE,Fault 6 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "SYSFLTE,System Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "FLT5IE,Fault 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "FLT4IE,Fault 4 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "FLT3IE,Fault 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "FLT2IE,Fault 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "FLT1IE,Fault 1 Interrupt Enable" "0,1"
|
|
line.long 0x4 "OENR,Output Enable Register"
|
|
bitfld.long 0x4 11. "TF2ODS,Timer F Output 2 disable status" "0,1"
|
|
bitfld.long 0x4 10. "TF1ODS,Timer F Output 1 disable status" "0,1"
|
|
bitfld.long 0x4 9. "TE2OEN,Timer E Output 2 Enable" "0,1"
|
|
bitfld.long 0x4 8. "TE1OEN,Timer E Output 1 Enable" "0,1"
|
|
bitfld.long 0x4 7. "TD2OEN,Timer D Output 2 Enable" "0,1"
|
|
bitfld.long 0x4 6. "TD1OEN,Timer D Output 1 Enable" "0,1"
|
|
bitfld.long 0x4 5. "TC2OEN,Timer C Output 2 Enable" "0,1"
|
|
bitfld.long 0x4 4. "TC1OEN,Timer C Output 1 Enable" "0,1"
|
|
bitfld.long 0x4 3. "TB2OEN,Timer B Output 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TB1OEN,Timer B Output 1 Enable" "0,1"
|
|
bitfld.long 0x4 1. "TA2OEN,Timer A Output 2 Enable" "0,1"
|
|
bitfld.long 0x4 0. "TA1OEN,Timer A Output 1 Enable" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "ODISR,ODISR"
|
|
bitfld.long 0x0 11. "TF2ODIS,TF2ODIS" "0,1"
|
|
bitfld.long 0x0 10. "TF1ODIS,TF1ODIS" "0,1"
|
|
bitfld.long 0x0 9. "TE2ODIS,TE2ODIS" "0,1"
|
|
bitfld.long 0x0 8. "TE1ODIS,TE1ODIS" "0,1"
|
|
bitfld.long 0x0 7. "TD2ODIS,TD2ODIS" "0,1"
|
|
bitfld.long 0x0 6. "TD1ODIS,TD1ODIS" "0,1"
|
|
bitfld.long 0x0 5. "TC2ODIS,TC2ODIS" "0,1"
|
|
bitfld.long 0x0 4. "TC1ODIS,TC1ODIS" "0,1"
|
|
bitfld.long 0x0 3. "TB2ODIS,TB2ODIS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TB1ODIS,TB1ODIS" "0,1"
|
|
bitfld.long 0x0 1. "TA2ODIS,TA2ODIS" "0,1"
|
|
bitfld.long 0x0 0. "TA1ODIS,TA1ODIS" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ODSR,Output Disable Status Register"
|
|
bitfld.long 0x0 11. "TF2ODS,TF2ODS" "0,1"
|
|
bitfld.long 0x0 10. "TF1ODS,TF1ODS" "0,1"
|
|
bitfld.long 0x0 9. "TE2ODS,Timer E Output 2 disable status" "0,1"
|
|
bitfld.long 0x0 8. "TE1ODS,Timer E Output 1 disable status" "0,1"
|
|
bitfld.long 0x0 7. "TD2ODS,Timer D Output 2 disable status" "0,1"
|
|
bitfld.long 0x0 6. "TD1ODS,Timer D Output 1 disable status" "0,1"
|
|
bitfld.long 0x0 5. "TC2ODS,Timer C Output 2 disable status" "0,1"
|
|
bitfld.long 0x0 4. "TC1ODS,Timer C Output 1 disable status" "0,1"
|
|
bitfld.long 0x0 3. "TB2ODS,Timer B Output 2 disable status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TB1ODS,Timer B Output 1 disable status" "0,1"
|
|
bitfld.long 0x0 1. "TA2ODS,Timer A Output 2 disable status" "0,1"
|
|
bitfld.long 0x0 0. "TA1ODS,Timer A Output 1 disable status" "0,1"
|
|
group.long 0x20++0x4F
|
|
line.long 0x0 "BMCR,Burst Mode Control Register"
|
|
bitfld.long 0x0 31. "BMSTAT,Burst Mode Status" "0,1"
|
|
bitfld.long 0x0 22. "TFBM,Timer f Burst Mode" "0,1"
|
|
bitfld.long 0x0 21. "TEBM,Timer E Burst Mode" "0,1"
|
|
bitfld.long 0x0 20. "TDBM,Timer D Burst Mode" "0,1"
|
|
bitfld.long 0x0 19. "TCBM,Timer C Burst Mode" "0,1"
|
|
bitfld.long 0x0 18. "TBBM,Timer B Burst Mode" "0,1"
|
|
bitfld.long 0x0 17. "TABM,Timer A Burst Mode" "0,1"
|
|
bitfld.long 0x0 16. "MTBM,Master Timer Burst Mode" "0,1"
|
|
bitfld.long 0x0 10. "BMPREN,Burst Mode Preload Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--9. 1. "BMPRSC,Burst Mode Prescaler"
|
|
hexmask.long.byte 0x0 2.--5. 1. "BMCLK,Burst Mode Clock source"
|
|
bitfld.long 0x0 1. "BMOM,Burst Mode operating mode" "0,1"
|
|
bitfld.long 0x0 0. "BME,Burst Mode enable" "0,1"
|
|
line.long 0x4 "BMTRG,BMTRG"
|
|
bitfld.long 0x4 31. "OCHPEV,OCHPEV" "0,1"
|
|
bitfld.long 0x4 30. "EEV8,EEV8" "0,1"
|
|
bitfld.long 0x4 29. "EEV7,EEV7" "0,1"
|
|
bitfld.long 0x4 28. "TDEEV8,TDEEV8" "0,1"
|
|
bitfld.long 0x4 27. "TDEEV7,TDEEV7" "0,1"
|
|
bitfld.long 0x4 26. "TECMP2,TECMP2" "0,1"
|
|
bitfld.long 0x4 25. "TECMP1,TECMP1" "0,1"
|
|
bitfld.long 0x4 24. "TEREP,TEREP" "0,1"
|
|
bitfld.long 0x4 23. "TERST,TERST" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "TDCMP2,TDCMP2" "0,1"
|
|
bitfld.long 0x4 21. "TDCMP1,TDCMP1" "0,1"
|
|
bitfld.long 0x4 20. "TDREP,TDREP" "0,1"
|
|
bitfld.long 0x4 19. "TDRST,TDRST" "0,1"
|
|
bitfld.long 0x4 18. "TCCMP2,TCCMP2" "0,1"
|
|
bitfld.long 0x4 17. "TCCMP1,TCCMP1" "0,1"
|
|
bitfld.long 0x4 16. "TCREP,TCREP" "0,1"
|
|
bitfld.long 0x4 15. "TCRST,TCRST" "0,1"
|
|
bitfld.long 0x4 14. "TBCMP2,TBCMP2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TBCMP1,TBCMP1" "0,1"
|
|
bitfld.long 0x4 12. "TBREP,TBREP" "0,1"
|
|
bitfld.long 0x4 11. "TBRST,TBRST" "0,1"
|
|
bitfld.long 0x4 10. "TACMP2,TACMP2" "0,1"
|
|
bitfld.long 0x4 9. "TACMP1,TACMP1" "0,1"
|
|
bitfld.long 0x4 8. "TAREP,TAREP" "0,1"
|
|
bitfld.long 0x4 7. "TARST,TARST" "0,1"
|
|
bitfld.long 0x4 6. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x4 5. "MSTCMP3,MSTCMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x4 3. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x4 2. "MSTREP,MSTREP" "0,1"
|
|
bitfld.long 0x4 1. "MSTRST,MSTRST" "0,1"
|
|
bitfld.long 0x4 0. "SW,SW" "0,1"
|
|
line.long 0x8 "BMCMPR,BMCMPR"
|
|
hexmask.long.word 0x8 0.--15. 1. "BMCMP,BMCMP"
|
|
line.long 0xC "BMPER,Burst Mode Period Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BMPER,Burst mode Period"
|
|
line.long 0x10 "EECR1,Timer External Event Control Register 1"
|
|
bitfld.long 0x10 29. "EE5FAST,External Event 5 Fast mode" "0,1"
|
|
bitfld.long 0x10 27.--28. "EE5SNS,External Event 5 Sensitivity" "0,1,2,3"
|
|
bitfld.long 0x10 26. "EE5POL,External Event 5 Polarity" "0,1"
|
|
bitfld.long 0x10 24.--25. "EE5SRC,External Event 5 Source" "0,1,2,3"
|
|
bitfld.long 0x10 23. "EE4FAST,External Event 4 Fast mode" "0,1"
|
|
bitfld.long 0x10 21.--22. "EE4SNS,External Event 4 Sensitivity" "0,1,2,3"
|
|
bitfld.long 0x10 20. "EE4POL,External Event 4 Polarity" "0,1"
|
|
bitfld.long 0x10 18.--19. "EE4SRC,External Event 4 Source" "0,1,2,3"
|
|
bitfld.long 0x10 17. "EE3FAST,External Event 3 Fast mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15.--16. "EE3SNS,External Event 3 Sensitivity" "0,1,2,3"
|
|
bitfld.long 0x10 14. "EE3POL,External Event 3 Polarity" "0,1"
|
|
bitfld.long 0x10 12.--13. "EE3SRC,External Event 3 Source" "0,1,2,3"
|
|
bitfld.long 0x10 11. "EE2FAST,External Event 2 Fast mode" "0,1"
|
|
bitfld.long 0x10 9.--10. "EE2SNS,External Event 2 Sensitivity" "0,1,2,3"
|
|
bitfld.long 0x10 8. "EE2POL,External Event 2 Polarity" "0,1"
|
|
bitfld.long 0x10 6.--7. "EE2SRC,External Event 2 Source" "0,1,2,3"
|
|
bitfld.long 0x10 5. "EE1FAST,External Event 1 Fast mode" "0,1"
|
|
bitfld.long 0x10 3.--4. "EE1SNS,External Event 1 Sensitivity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 2. "EE1POL,External Event 1 Polarity" "0,1"
|
|
bitfld.long 0x10 0.--1. "EE1SRC,External Event 1 Source" "0,1,2,3"
|
|
line.long 0x14 "EECR2,Timer External Event Control Register 2"
|
|
bitfld.long 0x14 27.--28. "EE10SNS,EE10SNS" "0,1,2,3"
|
|
bitfld.long 0x14 26. "EE10POL,EE10POL" "0,1"
|
|
bitfld.long 0x14 24.--25. "EE10SRC,EE10SRC" "0,1,2,3"
|
|
bitfld.long 0x14 21.--22. "EE9SNS,EE9SNS" "0,1,2,3"
|
|
bitfld.long 0x14 20. "EE9POL,EE9POL" "0,1"
|
|
bitfld.long 0x14 18.--19. "EE9SRC,EE9SRC" "0,1,2,3"
|
|
bitfld.long 0x14 15.--16. "EE8SNS,EE8SNS" "0,1,2,3"
|
|
bitfld.long 0x14 14. "EE8POL,EE8POL" "0,1"
|
|
bitfld.long 0x14 12.--13. "EE8SRC,EE8SRC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 9.--10. "EE7SNS,EE7SNS" "0,1,2,3"
|
|
bitfld.long 0x14 8. "EE7POL,EE7POL" "0,1"
|
|
bitfld.long 0x14 6.--7. "EE7SRC,EE7SRC" "0,1,2,3"
|
|
bitfld.long 0x14 3.--4. "EE6SNS,EE6SNS" "0,1,2,3"
|
|
bitfld.long 0x14 2. "EE6POL,EE6POL" "0,1"
|
|
bitfld.long 0x14 0.--1. "EE6SRC,EE6SRC" "0,1,2,3"
|
|
line.long 0x18 "EECR3,Timer External Event Control Register 3"
|
|
bitfld.long 0x18 30.--31. "EEVSD,EEVSD" "0,1,2,3"
|
|
hexmask.long.byte 0x18 24.--27. 1. "EE10F,EE10F"
|
|
hexmask.long.byte 0x18 18.--21. 1. "EE9F,EE9F"
|
|
hexmask.long.byte 0x18 12.--15. 1. "EE8F,EE8F"
|
|
hexmask.long.byte 0x18 6.--9. 1. "EE7F,EE7F"
|
|
hexmask.long.byte 0x18 0.--3. 1. "EE6F,EE6F"
|
|
line.long 0x1C "ADC1R,ADC Trigger 1 Register"
|
|
bitfld.long 0x1C 31. "AD1TEPER,ADC trigger 1 on Timer E Period" "0,1"
|
|
bitfld.long 0x1C 30. "AD1TEC4,ADC trigger 1 on Timer E compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "AD1TEC3,ADC trigger 1 on Timer E compare 3" "0,1"
|
|
bitfld.long 0x1C 28. "AD1TEC2,ADC trigger 1 on Timer E compare 2" "0,1"
|
|
bitfld.long 0x1C 27. "AD1TDPER,ADC trigger 1 on Timer D Period" "0,1"
|
|
bitfld.long 0x1C 26. "AD1TDC4,ADC trigger 1 on Timer D compare 4" "0,1"
|
|
bitfld.long 0x1C 25. "AD1TDC3,ADC trigger 1 on Timer D compare 3" "0,1"
|
|
bitfld.long 0x1C 24. "AD1TDC2,ADC trigger 1 on Timer D compare 2" "0,1"
|
|
bitfld.long 0x1C 23. "AD1TCPER,ADC trigger 1 on Timer C Period" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "AD1TCC4,ADC trigger 1 on Timer C compare 4" "0,1"
|
|
bitfld.long 0x1C 21. "AD1TCC3,ADC trigger 1 on Timer C compare 3" "0,1"
|
|
bitfld.long 0x1C 20. "AD1TCC2,ADC trigger 1 on Timer C compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "AD1TBRST,ADC trigger 1 on Timer B Reset" "0,1"
|
|
bitfld.long 0x1C 18. "AD1TBPER,ADC trigger 1 on Timer B Period" "0,1"
|
|
bitfld.long 0x1C 17. "AD1TBC4,ADC trigger 1 on Timer B compare 4" "0,1"
|
|
bitfld.long 0x1C 16. "AD1TBC3,ADC trigger 1 on Timer B compare 3" "0,1"
|
|
bitfld.long 0x1C 15. "AD1TBC2,ADC trigger 1 on Timer B compare 2" "0,1"
|
|
bitfld.long 0x1C 14. "AD1TARST,ADC trigger 1 on Timer A Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "AD1TAPER,ADC trigger 1 on Timer A Period" "0,1"
|
|
bitfld.long 0x1C 12. "AD1TAC4,ADC trigger 1 on Timer A compare 4" "0,1"
|
|
bitfld.long 0x1C 11. "AD1TAC3,ADC trigger 1 on Timer A compare 3" "0,1"
|
|
bitfld.long 0x1C 10. "AD1TAC2,ADC trigger 1 on Timer A compare 2" "0,1"
|
|
bitfld.long 0x1C 9. "AD1EEV5,ADC trigger 1 on External Event 5" "0,1"
|
|
bitfld.long 0x1C 8. "AD1EEV4,ADC trigger 1 on External Event 4" "0,1"
|
|
bitfld.long 0x1C 7. "AD1EEV3,ADC trigger 1 on External Event 3" "0,1"
|
|
bitfld.long 0x1C 6. "AD1EEV2,ADC trigger 1 on External Event 2" "0,1"
|
|
bitfld.long 0x1C 5. "AD1EEV1,ADC trigger 1 on External Event 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "AD1MPER,ADC trigger 1 on Master Period" "0,1"
|
|
bitfld.long 0x1C 3. "AD1MC4,ADC trigger 1 on Master Compare 4" "0,1"
|
|
bitfld.long 0x1C 2. "AD1MC3,ADC trigger 1 on Master Compare 3" "0,1"
|
|
bitfld.long 0x1C 1. "AD1MC2,ADC trigger 1 on Master Compare 2" "0,1"
|
|
bitfld.long 0x1C 0. "AD1MC1,ADC trigger 1 on Master Compare 1" "0,1"
|
|
line.long 0x20 "ADC2R,ADC Trigger 2 Register"
|
|
bitfld.long 0x20 31. "AD2TERST,ADC trigger 2 on Timer E Reset" "0,1"
|
|
bitfld.long 0x20 30. "AD2TEC4,ADC trigger 2 on Timer E compare 4" "0,1"
|
|
bitfld.long 0x20 29. "AD2TEC3,ADC trigger 2 on Timer E compare 3" "0,1"
|
|
bitfld.long 0x20 28. "AD2TEC2,ADC trigger 2 on Timer E compare 2" "0,1"
|
|
bitfld.long 0x20 27. "AD2TDRST,ADC trigger 2 on Timer D Reset" "0,1"
|
|
bitfld.long 0x20 26. "AD2TDPER,ADC trigger 2 on Timer D Period" "0,1"
|
|
bitfld.long 0x20 25. "AD2TDC4,ADC trigger 2 on Timer D compare 4" "0,1"
|
|
bitfld.long 0x20 24. "AD2TDC3,ADC trigger 2 on Timer D compare 3" "0,1"
|
|
bitfld.long 0x20 23. "AD2TDC2,ADC trigger 2 on Timer D compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x20 22. "AD2TCRST,ADC trigger 2 on Timer C Reset" "0,1"
|
|
bitfld.long 0x20 21. "AD2TCPER,ADC trigger 2 on Timer C Period" "0,1"
|
|
bitfld.long 0x20 20. "AD2TCC4,ADC trigger 2 on Timer C compare 4" "0,1"
|
|
bitfld.long 0x20 19. "AD2TCC3,ADC trigger 2 on Timer C compare 3" "0,1"
|
|
bitfld.long 0x20 18. "AD2TCC2,ADC trigger 2 on Timer C compare 2" "0,1"
|
|
bitfld.long 0x20 17. "AD2TBPER,ADC trigger 2 on Timer B Period" "0,1"
|
|
bitfld.long 0x20 16. "AD2TBC4,ADC trigger 2 on Timer B compare 4" "0,1"
|
|
bitfld.long 0x20 15. "AD2TBC3,ADC trigger 2 on Timer B compare 3" "0,1"
|
|
bitfld.long 0x20 14. "AD2TBC2,ADC trigger 2 on Timer B compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x20 13. "AD2TAPER,ADC trigger 2 on Timer A Period" "0,1"
|
|
bitfld.long 0x20 12. "AD2TAC4,ADC trigger 2 on Timer A compare 4" "0,1"
|
|
bitfld.long 0x20 11. "AD2TAC3,ADC trigger 2 on Timer A compare 3" "0,1"
|
|
bitfld.long 0x20 10. "AD2TAC2,ADC trigger 2 on Timer A compare 2" "0,1"
|
|
bitfld.long 0x20 9. "AD2EEV10,ADC trigger 2 on External Event 10" "0,1"
|
|
bitfld.long 0x20 8. "AD2EEV9,ADC trigger 2 on External Event 9" "0,1"
|
|
bitfld.long 0x20 7. "AD2EEV8,ADC trigger 2 on External Event 8" "0,1"
|
|
bitfld.long 0x20 6. "AD2EEV7,ADC trigger 2 on External Event 7" "0,1"
|
|
bitfld.long 0x20 5. "AD2EEV6,ADC trigger 2 on External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "AD2MPER,ADC trigger 2 on Master Period" "0,1"
|
|
bitfld.long 0x20 3. "AD2MC4,ADC trigger 2 on Master Compare 4" "0,1"
|
|
bitfld.long 0x20 2. "AD2MC3,ADC trigger 2 on Master Compare 3" "0,1"
|
|
bitfld.long 0x20 1. "AD2MC2,ADC trigger 2 on Master Compare 2" "0,1"
|
|
bitfld.long 0x20 0. "AD2MC1,ADC trigger 2 on Master Compare 1" "0,1"
|
|
line.long 0x24 "ADC3R,ADC Trigger 3 Register"
|
|
bitfld.long 0x24 31. "AD1TEPER,AD1TEPER" "0,1"
|
|
bitfld.long 0x24 30. "AD1TEC4,AD1TEC4" "0,1"
|
|
bitfld.long 0x24 29. "AD1TEC3,AD1TEC3" "0,1"
|
|
bitfld.long 0x24 28. "AD1TEC2,AD1TEC2" "0,1"
|
|
bitfld.long 0x24 27. "AD1TDPER,AD1TDPER" "0,1"
|
|
bitfld.long 0x24 26. "AD1TDC4,AD1TDC4" "0,1"
|
|
bitfld.long 0x24 25. "AD1TDC3,AD1TDC3" "0,1"
|
|
bitfld.long 0x24 24. "AD1TDC2,AD1TDC2" "0,1"
|
|
bitfld.long 0x24 23. "AD1TCPER,AD1TCPER" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "AD1TCC4,AD1TCC4" "0,1"
|
|
bitfld.long 0x24 21. "AD1TCC3,AD1TCC3" "0,1"
|
|
bitfld.long 0x24 20. "AD1TCC2,AD1TCC2" "0,1"
|
|
bitfld.long 0x24 19. "AD1TBRST,AD1TBRST" "0,1"
|
|
bitfld.long 0x24 18. "AD1TBPER,AD1TBPER" "0,1"
|
|
bitfld.long 0x24 17. "AD1TBC4,AD1TBC4" "0,1"
|
|
bitfld.long 0x24 16. "AD1TBC3,AD1TBC3" "0,1"
|
|
bitfld.long 0x24 15. "AD1TBC2,AD1TBC2" "0,1"
|
|
bitfld.long 0x24 14. "AD1TARST,AD1TARST" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "AD1TAPER,AD1TAPER" "0,1"
|
|
bitfld.long 0x24 12. "AD1TAC4,AD1TAC4" "0,1"
|
|
bitfld.long 0x24 11. "AD1TAC3,AD1TAC3" "0,1"
|
|
bitfld.long 0x24 10. "AD1TAC2,AD1TAC2" "0,1"
|
|
bitfld.long 0x24 9. "AD1EEV5,AD1EEV5" "0,1"
|
|
bitfld.long 0x24 8. "AD1EEV4,AD1EEV4" "0,1"
|
|
bitfld.long 0x24 7. "AD1EEV3,AD1EEV3" "0,1"
|
|
bitfld.long 0x24 6. "AD1EEV2,AD1EEV2" "0,1"
|
|
bitfld.long 0x24 5. "AD1EEV1,AD1EEV1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "AD1MPER,AD1MPER" "0,1"
|
|
bitfld.long 0x24 3. "AD1MC4,AD1MC4" "0,1"
|
|
bitfld.long 0x24 2. "AD1MC3,AD1MC3" "0,1"
|
|
bitfld.long 0x24 1. "AD1MC2,AD1MC2" "0,1"
|
|
bitfld.long 0x24 0. "AD1MC1,AD1MC1" "0,1"
|
|
line.long 0x28 "ADC4R,ADC Trigger 4 Register"
|
|
bitfld.long 0x28 31. "AD2TERST,AD2TERST" "0,1"
|
|
bitfld.long 0x28 30. "AD2TEC4,AD2TEC4" "0,1"
|
|
bitfld.long 0x28 29. "AD2TEC3,AD2TEC3" "0,1"
|
|
bitfld.long 0x28 28. "AD2TEC2,AD2TEC2" "0,1"
|
|
bitfld.long 0x28 27. "AD2TDRST,AD2TDRST" "0,1"
|
|
bitfld.long 0x28 26. "AD2TDPER,AD2TDPER" "0,1"
|
|
bitfld.long 0x28 25. "AD2TDC4,AD2TDC4" "0,1"
|
|
bitfld.long 0x28 24. "AD2TDC3,AD2TDC3" "0,1"
|
|
bitfld.long 0x28 23. "AD2TDC2,AD2TDC2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "AD2TCRST,AD2TCRST" "0,1"
|
|
bitfld.long 0x28 21. "AD2TCPER,AD2TCPER" "0,1"
|
|
bitfld.long 0x28 20. "AD2TCC4,AD2TCC4" "0,1"
|
|
bitfld.long 0x28 19. "AD2TCC3,AD2TCC3" "0,1"
|
|
bitfld.long 0x28 18. "AD2TCC2,AD2TCC2" "0,1"
|
|
bitfld.long 0x28 17. "AD2TBPER,AD2TBPER" "0,1"
|
|
bitfld.long 0x28 16. "AD2TBC4,AD2TBC4" "0,1"
|
|
bitfld.long 0x28 15. "AD2TBC3,AD2TBC3" "0,1"
|
|
bitfld.long 0x28 14. "AD2TBC2,AD2TBC2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "AD2TAPER,AD2TAPER" "0,1"
|
|
bitfld.long 0x28 12. "AD2TAC4,AD2TAC4" "0,1"
|
|
bitfld.long 0x28 11. "AD2TAC3,AD2TAC3" "0,1"
|
|
bitfld.long 0x28 10. "AD2TAC2,AD2TAC2" "0,1"
|
|
bitfld.long 0x28 9. "AD2EEV10,AD2EEV10" "0,1"
|
|
bitfld.long 0x28 8. "AD2EEV9,AD2EEV9" "0,1"
|
|
bitfld.long 0x28 7. "AD2EEV8,AD2EEV8" "0,1"
|
|
bitfld.long 0x28 6. "AD2EEV7,AD2EEV7" "0,1"
|
|
bitfld.long 0x28 5. "AD2EEV6,AD2EEV6" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "AD2MPER,AD2MPER" "0,1"
|
|
bitfld.long 0x28 3. "AD2MC4,AD2MC4" "0,1"
|
|
bitfld.long 0x28 2. "AD2MC3,AD2MC3" "0,1"
|
|
bitfld.long 0x28 1. "AD2MC2,AD2MC2" "0,1"
|
|
bitfld.long 0x28 0. "AD2MC1,AD2MC1" "0,1"
|
|
line.long 0x2C "DLLCR,DLL Control Register"
|
|
bitfld.long 0x2C 2.--3. "CALRTE,DLL Calibration rate" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "CALEN,DLL Calibration Enable" "0,1"
|
|
bitfld.long 0x2C 0. "CAL,DLL Calibration Start" "0,1"
|
|
line.long 0x30 "FLTINR1,HRTIM Fault Input Register 1"
|
|
bitfld.long 0x30 31. "FLT4LCK,FLT4LCK" "0,1"
|
|
hexmask.long.byte 0x30 27.--30. 1. "FLT4F,FLT4F"
|
|
bitfld.long 0x30 26. "FLT4SRC,FLT4SRC" "0,1"
|
|
bitfld.long 0x30 25. "FLT4P,FLT4P" "0,1"
|
|
bitfld.long 0x30 24. "FLT4E,FLT4E" "0,1"
|
|
bitfld.long 0x30 23. "FLT3LCK,FLT3LCK" "0,1"
|
|
hexmask.long.byte 0x30 19.--22. 1. "FLT3F,FLT3F"
|
|
bitfld.long 0x30 18. "FLT3SRC,FLT3SRC" "0,1"
|
|
bitfld.long 0x30 17. "FLT3P,FLT3P" "0,1"
|
|
newline
|
|
bitfld.long 0x30 16. "FLT3E,FLT3E" "0,1"
|
|
bitfld.long 0x30 15. "FLT2LCK,FLT2LCK" "0,1"
|
|
hexmask.long.byte 0x30 11.--14. 1. "FLT2F,FLT2F"
|
|
bitfld.long 0x30 10. "FLT2SRC,FLT2SRC" "0,1"
|
|
bitfld.long 0x30 9. "FLT2P,FLT2P" "0,1"
|
|
bitfld.long 0x30 8. "FLT2E,FLT2E" "0,1"
|
|
bitfld.long 0x30 7. "FLT1LCK,FLT1LCK" "0,1"
|
|
hexmask.long.byte 0x30 3.--6. 1. "FLT1F,FLT1F"
|
|
bitfld.long 0x30 2. "FLT1SRC,FLT1SRC" "0,1"
|
|
newline
|
|
bitfld.long 0x30 1. "FLT1P,FLT1P" "0,1"
|
|
bitfld.long 0x30 0. "FLT1E,FLT1E" "0,1"
|
|
line.long 0x34 "FLTINR2,HRTIM Fault Input Register 2"
|
|
bitfld.long 0x34 24.--25. "FLTSD,FLTSD" "0,1,2,3"
|
|
bitfld.long 0x34 21. "FLT6SRC_1,FLT6SRC" "0,1"
|
|
bitfld.long 0x34 20. "FLT5SRC_1,FLT5SRC_1" "0,1"
|
|
bitfld.long 0x34 19. "FLT4SRC_1,FLT4SRC_1" "0,1"
|
|
bitfld.long 0x34 18. "FLT3SRC_1,FLT3SRC_1" "0,1"
|
|
bitfld.long 0x34 17. "FLT2SRC_1,FLT2SRC_1" "0,1"
|
|
bitfld.long 0x34 16. "FLT1SRC_1,FLT1SRC_1" "0,1"
|
|
bitfld.long 0x34 15. "FLT6LCK,FLT6LCK" "0,1"
|
|
hexmask.long.byte 0x34 11.--14. 1. "FLT6F,FLT6F"
|
|
newline
|
|
bitfld.long 0x34 10. "FLT6SRC_0,FLT6F" "0,1"
|
|
bitfld.long 0x34 9. "FLT6P,FLT6P" "0,1"
|
|
bitfld.long 0x34 8. "FLT6E,FLT6E" "0,1"
|
|
bitfld.long 0x34 7. "FLT5LCK,FLT5LCK" "0,1"
|
|
hexmask.long.byte 0x34 3.--6. 1. "FLT5F,FLT5F"
|
|
bitfld.long 0x34 2. "FLT5SRC,FLT5SRC" "0,1"
|
|
bitfld.long 0x34 1. "FLT5P,FLT5P" "0,1"
|
|
bitfld.long 0x34 0. "FLT5E,FLT5E" "0,1"
|
|
line.long 0x38 "BDMUPDR,BDMUPDR"
|
|
bitfld.long 0x38 9. "MCMP4,MCMP4" "0,1"
|
|
bitfld.long 0x38 8. "MCMP3,MCMP3" "0,1"
|
|
bitfld.long 0x38 7. "MCMP2,MCMP2" "0,1"
|
|
bitfld.long 0x38 6. "MCMP1,MCMP1" "0,1"
|
|
bitfld.long 0x38 5. "MREP,MREP" "0,1"
|
|
bitfld.long 0x38 4. "MPER,MPER" "0,1"
|
|
bitfld.long 0x38 3. "MCNT,MCNT" "0,1"
|
|
bitfld.long 0x38 2. "MDIER,MDIER" "0,1"
|
|
bitfld.long 0x38 1. "MICR,MICR" "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "MCR,MCR" "0,1"
|
|
line.long 0x3C "BDTAUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x3C 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x3C 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x3C 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x3C 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x3C 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x3C 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x3C 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x3C 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x3C 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x3C 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x3C 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x3C 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x3C 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x3C 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x3C 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x3C 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x3C 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x3C 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x3C 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x3C 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x3C 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
line.long 0x40 "BDTBUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x40 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x40 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x40 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x40 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x40 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x40 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x40 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x40 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x40 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x40 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x40 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x40 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x40 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x40 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x40 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x40 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x40 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x40 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x40 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x40 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x40 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
line.long 0x44 "BDTCUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x44 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x44 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x44 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x44 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x44 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x44 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x44 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x44 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x44 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x44 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x44 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x44 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x44 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x44 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x44 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x44 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x44 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x44 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x44 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x44 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x44 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
line.long 0x48 "BDTDUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x48 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x48 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x48 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x48 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x48 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x48 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x48 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x48 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x48 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x48 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x48 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x48 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x48 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x48 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x48 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x48 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x48 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x48 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x48 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x48 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x48 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
line.long 0x4C "BDTEUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x4C 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x4C 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x4C 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x4C 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x4C 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x4C 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x4C 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x4C 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x4C 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x4C 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x4C 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x4C 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x4C 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x4C 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x4C 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x4C 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x4C 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4C 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x4C 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x4C 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x4C 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x4C 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "BDTFUPR,Burst DMA Timerx update Register"
|
|
bitfld.long 0x0 22. "TIMxEEFR3,TIMxEEFR3" "0,1"
|
|
bitfld.long 0x0 21. "TIMxCR2,TIMxCR2" "0,1"
|
|
bitfld.long 0x0 20. "TIMxFLTR,HRTIM_FLTxR register update enable" "0,1"
|
|
bitfld.long 0x0 19. "TIMxOUTR,HRTIM_OUTxR register update enable" "0,1"
|
|
bitfld.long 0x0 18. "TIMxCHPR,HRTIM_CHPxR register update enable" "0,1"
|
|
bitfld.long 0x0 17. "TIMxRSTR,HRTIM_RSTxR register update enable" "0,1"
|
|
bitfld.long 0x0 16. "TIMxEEFR2,HRTIM_EEFxR2 register update enable" "0,1"
|
|
bitfld.long 0x0 15. "TIMxEEFR1,HRTIM_EEFxR1 register update enable" "0,1"
|
|
bitfld.long 0x0 14. "TIMxRST2R,HRTIM_RST2xR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIMxSET2R,HRTIM_SET2xR register update enable" "0,1"
|
|
bitfld.long 0x0 12. "TIMxRST1R,HRTIM_RST1xR register update enable" "0,1"
|
|
bitfld.long 0x0 11. "TIMxSET1R,HRTIM_SET1xR register update enable" "0,1"
|
|
bitfld.long 0x0 10. "TIMx_DTxR,HRTIM_DTxR register update enable" "0,1"
|
|
bitfld.long 0x0 9. "TIMxCMP4,HRTIM_CMP4xR register update enable" "0,1"
|
|
bitfld.long 0x0 8. "TIMxCMP3,HRTIM_CMP3xR register update enable" "0,1"
|
|
bitfld.long 0x0 7. "TIMxCMP2,HRTIM_CMP2xR register update enable" "0,1"
|
|
bitfld.long 0x0 6. "TIMxCMP1,HRTIM_CMP1xR register update enable" "0,1"
|
|
bitfld.long 0x0 5. "TIMxREP,HRTIM_REPxR register update enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TIMxPER,HRTIM_PERxR register update enable" "0,1"
|
|
bitfld.long 0x0 3. "TIMxCNT,HRTIM_CNTxR register update enable" "0,1"
|
|
bitfld.long 0x0 2. "TIMxDIER,HRTIM_TIMxDIER register update enable" "0,1"
|
|
bitfld.long 0x0 1. "TIMxICR,HRTIM_TIMxICR register update enable" "0,1"
|
|
bitfld.long 0x0 0. "TIMxCR,HRTIM_TIMxCR register update enable" "0,1"
|
|
wgroup.long 0x70++0x3
|
|
line.long 0x0 "BDMADR,Burst DMA Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "BDMADR,Burst DMA Data register"
|
|
group.long 0x78++0x17
|
|
line.long 0x0 "ADCER,HRTIM ADC Extended Trigger Register"
|
|
hexmask.long.byte 0x0 26.--30. 1. "ADC10TRG,ADC10TRG"
|
|
hexmask.long.byte 0x0 21.--25. 1. "ADC9TRG,ADC9TRG"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ADC8TRG,ADC8TRG"
|
|
hexmask.long.byte 0x0 10.--14. 1. "ADC7TRG,ADC7TRG"
|
|
hexmask.long.byte 0x0 5.--9. 1. "ADC6TRG,ADC6TRG"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ADC5TRG,ADC5TRG"
|
|
line.long 0x4 "ADCUR,HRTIM ADC Trigger Update Register"
|
|
bitfld.long 0x4 20.--22. "AD10USRC,AD10USRC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "AD9USRC,AD9USRC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "AD8USRC,AD8USRC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "AD7USRC,AD7USRC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "AD6USRC,AD6USRC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "AD5USRC,AD5USRC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "ADCPS1,HRTIM ADC Post Scaler Register 1"
|
|
hexmask.long.byte 0x8 24.--28. 1. "ADC5PSC,ADC5PSC"
|
|
hexmask.long.byte 0x8 18.--22. 1. "ADC4PSC,ADC4PSC"
|
|
hexmask.long.byte 0x8 12.--16. 1. "ADC3PSC,ADC3PSC"
|
|
hexmask.long.byte 0x8 6.--10. 1. "ADC2PSC,ADC2PSC"
|
|
hexmask.long.byte 0x8 0.--4. 1. "ADC1PSC,ADC1PSC"
|
|
line.long 0xC "ADCPS2,HRTIM ADC Post Scaler Register 2"
|
|
hexmask.long.byte 0xC 24.--28. 1. "ADC10PSC,ADC10PSC"
|
|
hexmask.long.byte 0xC 18.--22. 1. "ADC9PSC,ADC9PSC"
|
|
hexmask.long.byte 0xC 12.--16. 1. "ADC8PSC,ADC8PSC"
|
|
hexmask.long.byte 0xC 6.--10. 1. "ADC7PSC,ADC7PSC"
|
|
hexmask.long.byte 0xC 0.--4. 1. "ADC6PSC,ADC6PSC"
|
|
line.long 0x10 "FLTINR3,HRTIM Fault Input Register 3"
|
|
bitfld.long 0x10 31. "FLT4RSTM,FLT4RSTM" "0,1"
|
|
bitfld.long 0x10 30. "FLT4CRES,FLT4CRES" "0,1"
|
|
hexmask.long.byte 0x10 26.--29. 1. "FLT4CNT,FLT4CNT"
|
|
bitfld.long 0x10 25. "FLT4BLKS,FLT4BLKS" "0,1"
|
|
bitfld.long 0x10 24. "FLT4BLKE,FLT4BLKE" "0,1"
|
|
bitfld.long 0x10 23. "FLT3RSTM,FLT3RSTM" "0,1"
|
|
bitfld.long 0x10 22. "FLT3CRES,FLT3CRES" "0,1"
|
|
hexmask.long.byte 0x10 18.--21. 1. "FLT3CNT,FLT3CNT"
|
|
bitfld.long 0x10 17. "FLT3BLKS,FLT3BLKS" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "FLT3BLKE,FLT3BLKE" "0,1"
|
|
bitfld.long 0x10 15. "FLT2RSTM,FLT2RSTM" "0,1"
|
|
bitfld.long 0x10 14. "FLT2CRES,FLT2CRES" "0,1"
|
|
hexmask.long.byte 0x10 10.--13. 1. "FLT2CNT,FLT2CNT"
|
|
bitfld.long 0x10 9. "FLT2BLKS,FLT2BLKS" "0,1"
|
|
bitfld.long 0x10 8. "FLT2BLKE,FLT2BLKE" "0,1"
|
|
bitfld.long 0x10 7. "FLT1RSTM,FLT1RSTM" "0,1"
|
|
bitfld.long 0x10 6. "FLT1CRES,FLT1CRES" "0,1"
|
|
hexmask.long.byte 0x10 2.--5. 1. "FLT1CNT,FLT1CNT"
|
|
newline
|
|
bitfld.long 0x10 1. "FLT1BLKS,FLT1BLKS" "0,1"
|
|
bitfld.long 0x10 0. "FLT1BLKE,FLT1BLKE" "0,1"
|
|
line.long 0x14 "FLTINR4,HRTIM Fault Input Register 4"
|
|
bitfld.long 0x14 15. "FLT6RSTM,FLT6RSTM" "0,1"
|
|
bitfld.long 0x14 14. "FLT6CRES,FLT6CRES" "0,1"
|
|
hexmask.long.byte 0x14 10.--13. 1. "FLT6CNT,FLT6CNT"
|
|
bitfld.long 0x14 9. "FLT6BLKS,FLT6BLKS" "0,1"
|
|
bitfld.long 0x14 8. "FLT6BLKE,FLT6BLKE" "0,1"
|
|
bitfld.long 0x14 7. "FLT5RSTM,FLT5RSTM" "0,1"
|
|
bitfld.long 0x14 6. "FLT5CRES,FLT5CRES" "0,1"
|
|
hexmask.long.byte 0x14 2.--5. 1. "FLT5CNT,FLT5CNT"
|
|
bitfld.long 0x14 1. "FLT5BLKS,FLT5BLKS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "FLT5BLKE,FLT5BLKE" "0,1"
|
|
tree.end
|
|
tree "HRTIM_Master"
|
|
base ad:0x40016800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x0 30.--31. "BRSTDMA,Burst DMA Update" "0,1,2,3"
|
|
bitfld.long 0x0 29. "MREPU,Master Timer Repetition update" "0,1"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 22. "TFCEN,Timer F counter enable" "0,1"
|
|
bitfld.long 0x0 21. "TECEN,Timer E counter enable" "0,1"
|
|
bitfld.long 0x0 20. "TDCEN,Timer D counter enable" "0,1"
|
|
bitfld.long 0x0 19. "TCCEN,Timer C counter enable" "0,1"
|
|
bitfld.long 0x0 18. "TBCEN,Timer B counter enable" "0,1"
|
|
bitfld.long 0x0 17. "TACEN,Timer A counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCEN,Master Counter enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "SYNC_SRC,Synchronization source" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "SYNC_OUT,Synchronization output" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTM,Synchronization Starts Master" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTM,Synchronization Resets Master" "0,1"
|
|
bitfld.long 0x0 8.--9. "SYNC_IN,synchronization input" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Master Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Master Continuous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CK_PSC,HRTIM Master Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "MISR,Master Timer Interrupt Status Register"
|
|
bitfld.long 0x0 6. "MUPD,Master Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 5. "SYNC,Sync Input Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "MREP,Master Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "MCMP4,Master Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "MCMP3,Master Compare 3 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 1. "MCMP2,Master Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "MCMP1,Master Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "MICR,Master Timer Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "MUPDC,Master update Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 5. "SYNCC,Sync Input Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 4. "MREPC,Repetition Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 3. "MCMP4C,Master Compare 4 Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 2. "MCMP3C,Master Compare 3 Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 1. "MCMP2C,Master Compare 2 Interrupt flag clear" "0,1"
|
|
bitfld.long 0x0 0. "MCMP1C,Master Compare 1 Interrupt flag clear" "0,1"
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "MDIER,HRTIM Master Timer DMA / Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "MUPDDE,MUPDDE" "0,1"
|
|
bitfld.long 0x0 21. "SYNCDE,SYNCDE" "0,1"
|
|
bitfld.long 0x0 20. "MREPDE,MREPDE" "0,1"
|
|
bitfld.long 0x0 19. "MCMP4DE,MCMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "MCMP3DE,MCMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "MCMP2DE,MCMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "MCMP1DE,MCMP1DE" "0,1"
|
|
bitfld.long 0x0 6. "MUPDIE,MUPDIE" "0,1"
|
|
bitfld.long 0x0 5. "SYNCIE,SYNCIE" "0,1"
|
|
bitfld.long 0x0 4. "MREPIE,MREPIE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCMP4IE,MCMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "MCMP3IE,MCMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "MCMP2IE,MCMP2IE" "0,1"
|
|
bitfld.long 0x0 0. "MCMP1IE,MCMP1IE" "0,1"
|
|
line.long 0x4 "MCNTR,Master Timer Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCNT,Counter value"
|
|
line.long 0x8 "MPER,Master Timer Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "MPER,Master Timer Period value"
|
|
line.long 0xC "MREP,Master Timer Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "MREP,Master Timer Repetition counter value"
|
|
line.long 0x10 "MCMP1R,Master Timer Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "MCMP1,Master Timer Compare 1 value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "MCMP2R,Master Timer Compare 2 Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MCMP2,Master Timer Compare 2 value"
|
|
line.long 0x4 "MCMP3R,Master Timer Compare 3 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MCMP3,Master Timer Compare 3 value"
|
|
line.long 0x8 "MCMP4R,Master Timer Compare 4 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "MCMP4,Master Timer Compare 4 value"
|
|
tree.end
|
|
tree "HRTIM_TIMA"
|
|
base ad:0x40016880
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMACR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 23. "TEU,TEU" "0,1"
|
|
bitfld.long 0x0 22. "TDU,TDU" "0,1"
|
|
bitfld.long 0x0 21. "TCU,TCU" "0,1"
|
|
bitfld.long 0x0 20. "TBU,TBU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 16. "TFU,TFU" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMAISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMAICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMADIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTAR,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERAR,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPAR,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1AR,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CAR,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2AR,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3AR,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4AR,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1AR,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2AR,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTAR,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETA1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTA1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETA2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTA2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFAR1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFAR2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTAR,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMBCMP4,Timer B Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPAR,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1ACR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x24 15. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x24 14. "TFCMP1,TFCMP1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x24 12. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2ACR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x28 15. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x28 14. "TFCMP1,TFCMP1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x28 12. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTAR,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTAR,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMACR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "AEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree "HRTIM_TIMB"
|
|
base ad:0x40016900
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMBCR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 23. "TEU,TEU" "0,1"
|
|
bitfld.long 0x0 22. "TDU,TDU" "0,1"
|
|
bitfld.long 0x0 21. "TCU,TCU" "0,1"
|
|
bitfld.long 0x0 19. "TAU,TAU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 16. "TFU,TFU" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMBISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMBICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMBDIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTR,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERBR,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPBR,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1BR,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CBR,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2BR,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3BR,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4BR,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1BR,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2BR,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTBR,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETB1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTB1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETB2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTB2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFBR1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFBR2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTBR,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPBR,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1BCR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x24 19. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x24 18. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x24 17. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x24 16. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2BCR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x28 19. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x28 18. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x28 17. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x28 16. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTBR,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTBR,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMBCR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "BEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree "HRTIM_TIMC"
|
|
base ad:0x40016980
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMCCR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 23. "TEU,TEU" "0,1"
|
|
bitfld.long 0x0 22. "TDU,TDU" "0,1"
|
|
bitfld.long 0x0 20. "TBU,TBU" "0,1"
|
|
bitfld.long 0x0 19. "TAU,TAU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 16. "TFU,TFU" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMCISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMCICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMCDIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTCR,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERCR,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPCR,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1CR,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CCR,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2CR,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3CR,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4CR,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1CR,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2CR,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTCR,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETC1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTC1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETC2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTC2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFCR1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFCR2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTCR,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPCR,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1CCR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x24 23. "TFCMP2,TFCMP2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x24 21. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x24 20. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2CCR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x28 23. "TF1CMP2,TF1CMP2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TF1CMP1,TF1CMP1" "0,1"
|
|
bitfld.long 0x28 21. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x28 20. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTCR,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTCR,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMCCR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "CEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree "HRTIM_TIMD"
|
|
base ad:0x40016A00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMDCR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 23. "TEU,TEU" "0,1"
|
|
bitfld.long 0x0 21. "TCU,TCU" "0,1"
|
|
bitfld.long 0x0 20. "TBU,TBU" "0,1"
|
|
bitfld.long 0x0 19. "TAU,TAU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 16. "TFU,TFU" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMDISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMDICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMDDIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTDR,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERDR,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPDR,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1DR,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CDR,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2DR,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3DR,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4DR,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1DR,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2DR,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTDR,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETD1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTD1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETD2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTD2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFDR1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFDR2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTDR,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPDR,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1DCR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x24 27. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x24 26. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x24 25. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x24 24. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2DCR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1"
|
|
bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1"
|
|
bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1"
|
|
bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1"
|
|
bitfld.long 0x28 27. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x28 26. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x28 25. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x28 24. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTDR,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTDR,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMDCR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "DEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree "HRTIM_TIME"
|
|
base ad:0x40016A80
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMECR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 22. "TDU,TDU" "0,1"
|
|
bitfld.long 0x0 21. "TCU,TCU" "0,1"
|
|
bitfld.long 0x0 20. "TBU,TBU" "0,1"
|
|
bitfld.long 0x0 19. "TAU,TAU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 16. "TFU,TFU" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMEISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMEICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMEDIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTER,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERER,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPER,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1ER,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CER,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2ER,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3ER,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4ER,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1ER,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2ER,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTER,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETE1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTE1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETE2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTE2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFER1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFER2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTER,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMDCMP4,Timer D Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPER,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1ECR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x24 30. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x24 29. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x24 28. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2ECR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TFCMP2,TFCMP2" "0,1"
|
|
bitfld.long 0x28 30. "TFCMP1,TFCMP1" "0,1"
|
|
bitfld.long 0x28 29. "TF1RST,TF1RST" "0,1"
|
|
bitfld.long 0x28 28. "TF1SET,TF1SET" "0,1"
|
|
bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTER,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTER,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMECR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "EEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree "HRTIM_TIMF"
|
|
base ad:0x40016B00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "TIMFCR,Timerx Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating"
|
|
bitfld.long 0x0 27. "PREEN,Preload enable" "0,1"
|
|
bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3"
|
|
bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1"
|
|
bitfld.long 0x0 22. "TDU,TDU" "0,1"
|
|
bitfld.long 0x0 21. "TCU,TCU" "0,1"
|
|
bitfld.long 0x0 20. "TBU,TBU" "0,1"
|
|
bitfld.long 0x0 19. "TAU,TAU" "0,1"
|
|
bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1"
|
|
bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer x" "0,1"
|
|
bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer x" "0,1"
|
|
bitfld.long 0x0 9. "RSYNCU,Re-Synchronized Update" "0,1"
|
|
bitfld.long 0x0 7.--8. "INTLVD,Interleaved mode" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1"
|
|
bitfld.long 0x0 5. "HALF,Half mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1"
|
|
bitfld.long 0x0 3. "CONT,Continuous mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "TIMFISR,Timerx Interrupt Status Register"
|
|
bitfld.long 0x0 21. "O2CPY,Output 2 Copy" "0,1"
|
|
bitfld.long 0x0 20. "O1CPY,Output 1 Copy" "0,1"
|
|
bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1"
|
|
bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1"
|
|
bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1"
|
|
bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1"
|
|
bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "TIMFICR,Timerx Interrupt Clear Register"
|
|
bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag Clear" "0,1"
|
|
bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1"
|
|
bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1"
|
|
bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 6. "UPDC,Update Interrupt flag Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REPC,Repetition Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag Clear" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "TIMFDIER,TIMxDIER"
|
|
bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1"
|
|
bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1"
|
|
bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1"
|
|
bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1"
|
|
bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1"
|
|
bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1"
|
|
bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1"
|
|
bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1"
|
|
bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REPDE,REPDE" "0,1"
|
|
bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1"
|
|
bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1"
|
|
bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1"
|
|
bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1"
|
|
bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1"
|
|
bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1"
|
|
bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1"
|
|
bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1"
|
|
bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1"
|
|
bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1"
|
|
bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1"
|
|
bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1"
|
|
bitfld.long 0x0 4. "REPIE,REPIE" "0,1"
|
|
bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1"
|
|
bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1"
|
|
line.long 0x4 "CNTFR,Timerx Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value"
|
|
line.long 0x8 "PERFR,Timerx Period Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value"
|
|
line.long 0xC "REPFR,Timerx Repetition Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter value"
|
|
line.long 0x10 "CMP1FR,Timerx Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x14 "CMP1CFR,Timerx Compare 1 Compound Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from HRTIM_REPx register)"
|
|
hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value"
|
|
line.long 0x18 "CMP2FR,Timerx Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value"
|
|
line.long 0x1C "CMP3FR,Timerx Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value"
|
|
line.long 0x20 "CMP4FR,Timerx Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CPT1FR,Timerx Capture 1 Register"
|
|
bitfld.long 0x0 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value"
|
|
line.long 0x4 "CPT2FR,Timerx Capture 2 Register"
|
|
bitfld.long 0x4 16. "DIR,Timerx Capture 1 Direction status" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value"
|
|
group.long 0x38++0x3B
|
|
line.long 0x0 "DTFR,Timerx Deadtime Register"
|
|
bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1"
|
|
bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1"
|
|
bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling value" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value"
|
|
bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1"
|
|
bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1"
|
|
bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value"
|
|
line.long 0x4 "SETF1R,Timerx Output1 Set Register"
|
|
bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to active)" "0,1"
|
|
bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1"
|
|
bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1"
|
|
bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1"
|
|
bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1"
|
|
bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1"
|
|
bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1"
|
|
bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1"
|
|
bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1"
|
|
bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1"
|
|
bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1"
|
|
bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1"
|
|
bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1"
|
|
bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1"
|
|
bitfld.long 0x4 7. "MSTPER,Master Period" "0,1"
|
|
bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1"
|
|
bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1"
|
|
bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1"
|
|
bitfld.long 0x4 2. "PER,Timer A Period" "0,1"
|
|
bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1"
|
|
bitfld.long 0x4 0. "SST,Software Set trigger" "0,1"
|
|
line.long 0x8 "RSTE1R,Timerx Output1 Reset Register"
|
|
bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x8 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x8 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x8 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x8 2. "PER,PER" "0,1"
|
|
bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x8 0. "SRT,SRT" "0,1"
|
|
line.long 0xC "SETF2R,Timerx Output2 Set Register"
|
|
bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0xC 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0xC 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0xC 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0xC 2. "PER,PER" "0,1"
|
|
bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0xC 0. "SST,SST" "0,1"
|
|
line.long 0x10 "RSTF2R,Timerx Output2 Reset Register"
|
|
bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1"
|
|
bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1"
|
|
bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1"
|
|
bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1"
|
|
bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1"
|
|
bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1"
|
|
bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1"
|
|
bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1"
|
|
bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1"
|
|
bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1"
|
|
bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1"
|
|
bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1"
|
|
bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1"
|
|
bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1"
|
|
bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1"
|
|
bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1"
|
|
bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1"
|
|
bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1"
|
|
bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1"
|
|
bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1"
|
|
bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1"
|
|
bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1"
|
|
bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1"
|
|
bitfld.long 0x10 6. "CMP4,CMP4" "0,1"
|
|
bitfld.long 0x10 5. "CMP3,CMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CMP2,CMP2" "0,1"
|
|
bitfld.long 0x10 3. "CMP1,CMP1" "0,1"
|
|
bitfld.long 0x10 2. "PER,PER" "0,1"
|
|
bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1"
|
|
bitfld.long 0x10 0. "SRT,SRT" "0,1"
|
|
line.long 0x14 "EEFFR1,Timerx External Event Filtering Register 1"
|
|
hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter"
|
|
bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1"
|
|
hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter"
|
|
bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1"
|
|
hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter"
|
|
bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1"
|
|
hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter"
|
|
bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1"
|
|
hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter"
|
|
newline
|
|
bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1"
|
|
line.long 0x18 "EEFFR2,Timerx External Event Filtering Register 2"
|
|
hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter"
|
|
bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1"
|
|
hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter"
|
|
bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1"
|
|
hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter"
|
|
bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1"
|
|
hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter"
|
|
bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1"
|
|
hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter"
|
|
newline
|
|
bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1"
|
|
line.long 0x1C "RSTFR,TimerA Reset Register"
|
|
bitfld.long 0x1C 31. "TIMFCPM2,Timer F Compare 2" "0,1"
|
|
bitfld.long 0x1C 30. "TIMDCMP4,Timer D Compare 4" "0,1"
|
|
bitfld.long 0x1C 29. "TIMDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x1C 28. "TIMDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1"
|
|
bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1"
|
|
bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1"
|
|
bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1"
|
|
bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1"
|
|
bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1"
|
|
bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1"
|
|
bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1"
|
|
bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1"
|
|
bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1"
|
|
bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1"
|
|
bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1"
|
|
bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1"
|
|
bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1"
|
|
bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1"
|
|
bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1"
|
|
bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1"
|
|
bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1"
|
|
bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1"
|
|
bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1"
|
|
bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1"
|
|
bitfld.long 0x1C 0. "TIMFCMP1,Timer A Update reset" "0,1"
|
|
line.long 0x20 "CHPFR,Timerx Chopper Register"
|
|
hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW"
|
|
bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency value"
|
|
line.long 0x24 "CPT1FCR,Timerx Capture 2 Control Register"
|
|
bitfld.long 0x24 31. "TECMP2,TECMP2" "0,1"
|
|
bitfld.long 0x24 30. "TECMP1,TECMP1" "0,1"
|
|
bitfld.long 0x24 29. "TE1RST,TE1RST" "0,1"
|
|
bitfld.long 0x24 28. "TE1SET,TE1SET" "0,1"
|
|
bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x28 "CPT2FCR,CPT2xCR"
|
|
bitfld.long 0x28 31. "TECMP2,TECMP2" "0,1"
|
|
bitfld.long 0x28 30. "TECMP1,TECMP1" "0,1"
|
|
bitfld.long 0x28 29. "TE1RST,TE1RST" "0,1"
|
|
bitfld.long 0x28 28. "TE1SET,TE1SET" "0,1"
|
|
bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1"
|
|
bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1"
|
|
bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1"
|
|
bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1"
|
|
bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1"
|
|
bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1"
|
|
bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1"
|
|
bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1"
|
|
bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1"
|
|
bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1"
|
|
bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1"
|
|
bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1"
|
|
bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1"
|
|
bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1"
|
|
bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1"
|
|
bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1"
|
|
bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1"
|
|
bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1"
|
|
bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1"
|
|
bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1"
|
|
bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1"
|
|
bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1"
|
|
bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1"
|
|
bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1"
|
|
bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1"
|
|
line.long 0x2C "OUTFR,Timerx Output Register"
|
|
bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1"
|
|
bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1"
|
|
bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1"
|
|
bitfld.long 0x2C 14. "BIAR,Balanced Idle Automatic Resume" "0,1"
|
|
bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1"
|
|
bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle entry" "0,1"
|
|
bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1"
|
|
bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3"
|
|
bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1"
|
|
bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1"
|
|
bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1"
|
|
line.long 0x30 "FLTFR,Timerx Fault Register"
|
|
bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1"
|
|
bitfld.long 0x30 5. "FLT6EN,Fault 6 enable" "0,1"
|
|
bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1"
|
|
bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1"
|
|
bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1"
|
|
bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1"
|
|
bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1"
|
|
line.long 0x34 "TIMFCR2,HRTIM Timerx Control Register 2"
|
|
bitfld.long 0x34 20. "TRGHLF,Triggered-half mode" "0,1"
|
|
bitfld.long 0x34 17. "GTCMP3,Greater than Compare 3 PWM mode" "0,1"
|
|
bitfld.long 0x34 16. "GTCMP1,Greater than Compare 1 PWM mode" "0,1"
|
|
bitfld.long 0x34 14.--15. "FEROM,Fault and Event Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 12.--13. "BMROM,Burst Mode Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 10.--11. "ADROM,ADC Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 8.--9. "OUTROM,Output Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 6.--7. "ROM,Roll-Over Mode" "0,1,2,3"
|
|
bitfld.long 0x34 4. "UDM,Up-Down Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "DCDR,Dual Channel DAC Reset trigger" "0,1"
|
|
bitfld.long 0x34 1. "DCDS,Dual Channel DAC Step trigger" "0,1"
|
|
bitfld.long 0x34 0. "DCDE,Dual Channel DAC trigger enable" "0,1"
|
|
line.long 0x38 "FEEFR3,HRTIM Timerx External Event Filtering Register 3"
|
|
hexmask.long.byte 0x38 8.--13. 1. "EEVACNT,External Event A counter"
|
|
hexmask.long.byte 0x38 4.--7. 1. "EEVASEL,External Event A Selection"
|
|
bitfld.long 0x38 2. "EEVARSTM,External Event A Reset Mode" "0,1"
|
|
bitfld.long 0x38 1. "EEVACRES,External Event A Counter Reset" "0,1"
|
|
bitfld.long 0x38 0. "EEVACE,External Event A Counter Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "I2C (Inter-Integrated Circuit Interface)"
|
|
base ad:0x0
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40007800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
sif (cpuis("STM32G471*"))
|
|
tree "I2C4"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "I2C4"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "I2C4"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "I2C4"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "I2C4"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value"
|
|
tree.end
|
|
tree "LPTIM (Low Power Timer)"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear Flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear Flag" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear Flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0,1,2,3"
|
|
hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "OR,option register"
|
|
bitfld.long 0x0 4.--5. "IN2_2_1,IN2_2_1" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "IN1_2_1,IN1_2_1" "0,1,2,3"
|
|
bitfld.long 0x0 1. "IN2,IN2" "0,1"
|
|
bitfld.long 0x0 0. "IN1,IN1" "0,1"
|
|
tree.end
|
|
tree "OPAMP (Operational Amplifiers)"
|
|
base ad:0x40010300
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "OPAMP1_CSR,OPAMP1 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 30. "CALOUT,CALOUT" "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x0 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
hexmask.long.byte 0x0 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x0 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
bitfld.long 0x0 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x0 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
bitfld.long 0x0 7. "OPAHSM,OPAHSM" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x0 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x4 "OPAMP2_CSR,OPAMP2 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 30. "CALOUT,CALOUT" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x4 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
hexmask.long.byte 0x4 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x4 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x4 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
bitfld.long 0x4 7. "OPAHSM,OPAHSM" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x4 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x4 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x8 "OPAMP3_CSR,OPAMP3 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 30. "CALOUT,CALOUT" "0,1"
|
|
hexmask.long.byte 0x8 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x8 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
hexmask.long.byte 0x8 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x8 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
bitfld.long 0x8 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x8 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
bitfld.long 0x8 7. "OPAHSM,OPAHSM" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
bitfld.long 0x8 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x8 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
bitfld.long 0x8 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x8 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
sif (cpuis("STM32G473*"))
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "OPAMP4_CSR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x0 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x0 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x0 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x0 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x0 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x4 "OPAMP5_CSR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x4 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x4 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x4 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x4 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x4 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x4 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x8 "OPAMP6_CSR,OPAMP6 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x8 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x8 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x8 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x8 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x8 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x8 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x8 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "OPAMP4_CSR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x0 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x0 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x0 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x0 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x0 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x4 "OPAMP5_CSR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x4 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x4 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x4 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x4 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x4 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x4 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x8 "OPAMP6_CSR,OPAMP6 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x8 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x8 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x8 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x8 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x8 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x8 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x8 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "OPAMP4_TCMR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x4 "OPAMP5_TCMR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x4 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "OPAMP4_CSR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x0 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x0 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x0 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x0 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x0 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x4 "OPAMP5_CSR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x4 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x4 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x4 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x4 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x4 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x4 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x8 "OPAMP6_CSR,OPAMP6 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x8 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x8 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x8 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x8 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x8 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x8 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x8 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "OPAMP4_TCMR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x4 "OPAMP5_TCMR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x4 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "OPAMP4_CSR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x0 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x0 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x0 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x0 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x0 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x0 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x4 "OPAMP5_CSR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x4 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x4 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x4 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x4 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x4 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x4 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x4 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
line.long 0x8 "OPAMP6_CSR,OPAMP6 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 30. "CALOUT,CALOUT" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--28. 1. "TRIMOFFSETN,TRIMOFFSETN"
|
|
hexmask.long.byte 0x8 19.--23. 1. "TRIMOFFSETP,TRIMOFFSETP"
|
|
newline
|
|
hexmask.long.byte 0x8 14.--18. 1. "PGA_GAIN,PGA_GAIN"
|
|
bitfld.long 0x8 12.--13. "CALSEL,CALSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 11. "CALON,CALON" "0,1"
|
|
bitfld.long 0x8 8. "OPAINTOEN,OPAINTOEN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "OPAHSM,OPAHSM" "0,1"
|
|
bitfld.long 0x8 5.--6. "VM_SEL,VM_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "USERTRIM,USERTRIM" "0,1"
|
|
bitfld.long 0x8 2.--3. "VP_SEL,VP_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 1. "FORCE_VP,FORCE_VP" "0,1"
|
|
bitfld.long 0x8 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "OPAMP4_TCMR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x4 "OPAMP5_TCMR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x4 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
group.long 0x18++0xB
|
|
line.long 0x0 "OPAMP1_TCMR,OPAMP1 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x4 "OPAMP2_TCMR,OPAMP2 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
bitfld.long 0x4 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x4 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
bitfld.long 0x4 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x8 "OPAMP3_TCMR,OPAMP3 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
bitfld.long 0x8 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x8 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
bitfld.long 0x8 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x8 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
sif (cpuis("STM32G473*"))
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "OPAMP4_TCMR,OPAMP4 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x4 "OPAMP5_TCMR,OPAMP5 control/status register"
|
|
bitfld.long 0x4 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x4 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x4 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x4 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
line.long 0x8 "OPAMP6_TCMR,OPAMP6 control/status register"
|
|
bitfld.long 0x8 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x8 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x8 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x8 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "OPAMP6_TCMR,OPAMP6 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "OPAMP6_TCMR,OPAMP6 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "OPAMP6_TCMR,OPAMP6 control/status register"
|
|
bitfld.long 0x0 31. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x0 5. "T20CM_EN,T20CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "T8CM_EN,T8CM_EN" "0,1"
|
|
bitfld.long 0x0 3. "T1CM_EN,T1CM_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "VPS_SEL,VPS_SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0. "VMS_SEL,VMS_SEL" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "PWR (Power Control)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PWR_CR1,Power control register 1"
|
|
bitfld.long 0x0 14. "LPR,Low-power run" "0,1"
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0: Cannot be written (forbidden by hardware),1: Range 1,2: Range 2,3: Cannot be written (forbidden by hardware)"
|
|
newline
|
|
bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0: Access to RTC and Backup registers disabled,1: Access to RTC and Backup registers enabled"
|
|
bitfld.long 0x0 3. "FPD_STOP,FPD_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,?,3: Standby mode,?,?,?,?"
|
|
line.long 0x4 "PWR_CR2,Power control register 2"
|
|
bitfld.long 0x4 7. "PVMEN2,Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. DAC 1MSPS /DAC 15MSPS min voltage." "0: PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V..,1: PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V.."
|
|
bitfld.long 0x4 6. "PVMEN1,Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. ADC/COMP min voltage 1.62V" "0: PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V..,1: PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V.."
|
|
newline
|
|
bitfld.long 0x4 1.--3. "PVDLS,Programmable voltage detector level selection." "0: V<sub>PVD0</sub> PVD threshold 0,1: V<sub>PVD1</sub> PVD threshold 1,2: V<sub>PVD2</sub> PVD threshold 2,3: V<sub>PVD3</sub> PVD threshold 3,4: V<sub>PVD4</sub> PVD threshold 4,5: V<sub>PVD5</sub> PVD threshold 5,6: V<sub>PVD6</sub> PVD threshold 6,7: External input analog voltage PVD_IN (compared.."
|
|
bitfld.long 0x4 0. "PVDE,Programmable voltage detector enable" "0: Programmable voltage detector disable.,1: Programmable voltage detector enable."
|
|
line.long 0x8 "PWR_CR3,Power control register 3"
|
|
bitfld.long 0x8 15. "EIWUL,Enable internal wakeup line" "0: Internal wakeup line disable.,1: Internal wakeup line enable."
|
|
bitfld.long 0x8 14. "UCPD1_DBDIS,USB Type-C and Power Delivery Dead Battery disable." "0: Enable USB Type-C dead battery pull-down..,1: Disable USB Type-C dead battery pull-down.."
|
|
newline
|
|
bitfld.long 0x8 13. "UCPD1_STDBY,UCPD1_STDBY USB Type-C and Power Delivery standby mode." "0: Write 0 immediately after standby exit when..,1: Write 1 just before entering standby when using.."
|
|
bitfld.long 0x8 10. "APC,Apply pull-up and pull-down configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RRS,SRAM2 retention in Standby mode" "0: SRAM2 is powered off in Standby mode (SRAM2..,1: SRAM2 is powered by the low-power regulator in.."
|
|
bitfld.long 0x8 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EWUP4,Enable Wakeup pin WKUP4" "0,1"
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
bitfld.long 0x8 0. "EWUP1,Enable Wakeup pin WKUP1" "0,1"
|
|
line.long 0xC "PWR_CR4,Power control register 4"
|
|
bitfld.long 0xC 9. "VBRS,V<sub>BAT</sub> battery charging resistor selection" "0: Charge V<sub>BAT</sub> through a 5 kOhms resistor,1: Charge V<sub>BAT</sub> through a 1.5 kOhms.."
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bitfld.long 0xC 8. "VBE,V<sub>BAT</sub> battery charging enable" "0: V<sub>BAT</sub> battery charging disable,1: V<sub>BAT</sub> battery charging enable"
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newline
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bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
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bitfld.long 0xC 3. "WP4,Wakeup pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
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newline
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bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
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bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
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newline
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bitfld.long 0xC 0. "WP1,Wakeup pin WKUP1 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
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rgroup.long 0x10++0x7
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line.long 0x0 "PWR_SR1,Power status register 1"
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bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
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bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter the Standby mode,1: The device entered the Standby mode"
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newline
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bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
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bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
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newline
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bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
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bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
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newline
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bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
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line.long 0x4 "PWR_SR2,Power status register 2"
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bitfld.long 0x4 15. "PVMO2,Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.8 V" "0: V<sub>DDA</sub> voltage is above PVM2 threshold..,1: V<sub>DDA</sub> voltage is below PVM2 threshold.."
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bitfld.long 0x4 14. "PVMO1,Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V" "0: V<sub>DDA</sub> voltage is above PVM1 threshold..,1: V<sub>DDA</sub> voltage is below PVM1 threshold.."
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newline
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bitfld.long 0x4 11. "PVDO,Programmable voltage detector output" "0: V<sub>DD</sub> is above the selected PVD threshold,1: V<sub>DD</sub> is below the selected PVD threshold"
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bitfld.long 0x4 10. "VOSF,Voltage scaling flag" "0: The regulator is ready in the selected voltage..,1: The regulator output voltage is changing to the.."
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newline
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bitfld.long 0x4 9. "REGLPF,Low-power regulator flag" "0: The regulator is ready in main mode (MR),1: The regulator is in low-power mode (LPR)"
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bitfld.long 0x4 8. "REGLPS,Low-power regulator started" "0: The low-power regulator is not ready,1: The low-power regulator is ready"
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wgroup.long 0x18++0x3
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line.long 0x0 "PWR_SCR,Power status clear register"
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bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
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bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
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newline
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bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
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bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
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newline
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bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
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bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
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group.long 0x20++0x37
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line.long 0x0 "PWR_PUCRA,Power Port A pull-up control register"
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bitfld.long 0x0 15. "PU15,Port A pull-up bit 15" "0,1"
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bitfld.long 0x0 13. "PU13,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 12. "PU12,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 11. "PU11,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 10. "PU10,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 9. "PU9,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 8. "PU8,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 7. "PU7,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 6. "PU6,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 5. "PU5,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 4. "PU4,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 3. "PU3,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 2. "PU2,Port A pull-up bit y (y=0..13)" "0,1"
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bitfld.long 0x0 1. "PU1,Port A pull-up bit y (y=0..13)" "0,1"
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newline
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bitfld.long 0x0 0. "PU0,Port A pull-up bit y (y=0..13)" "0,1"
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line.long 0x4 "PWR_PDCRA,Power Port A pull-down control register"
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bitfld.long 0x4 14. "PD14,Port A pull-down bit 14" "0,1"
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bitfld.long 0x4 12. "PD12,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 11. "PD11,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 10. "PD10,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 9. "PD9,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 8. "PD8,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 7. "PD7,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 6. "PD6,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 5. "PD5,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 4. "PD4,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 3. "PD3,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 2. "PD2,Port A pull-down bit y (y=0..12)" "0,1"
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newline
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bitfld.long 0x4 1. "PD1,Port A pull-down bit y (y=0..12)" "0,1"
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bitfld.long 0x4 0. "PD0,Port A pull-down bit y (y=0..12)" "0,1"
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line.long 0x8 "PWR_PUCRB,Power Port B pull-up control register"
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bitfld.long 0x8 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 11. "PU11,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 9. "PU9,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 8. "PU8,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 7. "PU7,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 6. "PU6,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 5. "PU5,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 4. "PU4,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 3. "PU3,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 2. "PU2,Port B pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x8 1. "PU1,Port B pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x8 0. "PU0,Port B pull-up bit y (y=0..15)" "0,1"
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line.long 0xC "PWR_PDCRB,Power Port B pull-down control register"
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bitfld.long 0xC 15. "PD15,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 14. "PD14,Port B pull-down bit y (y=5..15)" "0,1"
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newline
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bitfld.long 0xC 13. "PD13,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 12. "PD12,Port B pull-down bit y (y=5..15)" "0,1"
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newline
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bitfld.long 0xC 11. "PD11,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 10. "PD10,Port B pull-down bit y (y=5..15)" "0,1"
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newline
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bitfld.long 0xC 9. "PD9,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 8. "PD8,Port B pull-down bit y (y=5..15)" "0,1"
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newline
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bitfld.long 0xC 7. "PD7,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 6. "PD6,Port B pull-down bit y (y=5..15)" "0,1"
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newline
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bitfld.long 0xC 5. "PD5,Port B pull-down bit y (y=5..15)" "0,1"
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bitfld.long 0xC 3. "PD3,Port B pull-down bit y (y=0..3)" "0,1"
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newline
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bitfld.long 0xC 2. "PD2,Port B pull-down bit y (y=0..3)" "0,1"
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bitfld.long 0xC 1. "PD1,Port B pull-down bit y (y=0..3)" "0,1"
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newline
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bitfld.long 0xC 0. "PD0,Port B pull-down bit y (y=0..3)" "0,1"
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line.long 0x10 "PWR_PUCRC,Power Port C pull-up control register"
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bitfld.long 0x10 15. "PU15,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 14. "PU14,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x10 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x10 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
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line.long 0x14 "PWR_PDCRC,Power Port C pull-down control register"
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bitfld.long 0x14 15. "PD15,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 14. "PD14,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x14 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
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bitfld.long 0x14 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
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line.long 0x18 "PWR_PUCRD,Power Port D pull-up control register"
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bitfld.long 0x18 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
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newline
|
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bitfld.long 0x18 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
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|
newline
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bitfld.long 0x18 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x18 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
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newline
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bitfld.long 0x18 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
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|
newline
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bitfld.long 0x18 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
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|
newline
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bitfld.long 0x18 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
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bitfld.long 0x18 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
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bitfld.long 0x18 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
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|
bitfld.long 0x18 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
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line.long 0x1C "PWR_PDCRD,Power Port D pull-down control register"
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bitfld.long 0x1C 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
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bitfld.long 0x1C 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x1C 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
line.long 0x20 "PWR_PUCRE,Power Port E pull-up control register"
|
|
bitfld.long 0x20 15. "PU15,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 14. "PU14,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 13. "PU13,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 12. "PU12,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 11. "PU11,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 10. "PU10,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "PU9,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 8. "PU8,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "PU7,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 6. "PU6,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "PU5,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 4. "PU4,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x20 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x24 "PWR_PDCRE,Power Port E pull-down control register"
|
|
bitfld.long 0x24 15. "PD15,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 14. "PD14,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "PD13,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 12. "PD12,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 11. "PD11,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 10. "PD10,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 9. "PD9,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 8. "PD8,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "PD7,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 6. "PD6,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 5. "PD5,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 4. "PD4,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x24 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
line.long 0x28 "PWR_PUCRF,Power Port F pull-up control register"
|
|
bitfld.long 0x28 15. "PU15,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 14. "PU14,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 2. "PU2,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "PU1,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x28 0. "PU0,Port F pull-up bit y (y=0..15)" "0,1"
|
|
line.long 0x2C "PWR_PDCRF,Power Port F pull-down control register"
|
|
bitfld.long 0x2C 15. "PD15,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 14. "PD14,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 2. "PD2,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 1. "PD1,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x2C 0. "PD0,Port F pull-down bit y (y=0..15)" "0,1"
|
|
line.long 0x30 "PWR_PUCRG,Power Port G pull-up control register"
|
|
bitfld.long 0x30 10. "PU10,Port G pull-up bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x30 9. "PU9,Port G pull-up bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 8. "PU8,Port G pull-up bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x30 7. "PU7,Port G pull-up bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 6. "PU6,Port G pull-up bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x30 5. "PU5,Port G pull-up bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 4. "PU4,Port G pull-up bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x30 3. "PU3,Port G pull-up bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 2. "PU2,Port G pull-up bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x30 1. "PU1,Port G pull-up bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x30 0. "PU0,Port G pull-up bit y (y=0..10)" "0,1"
|
|
line.long 0x34 "PWR_PDCRG,Power Port G pull-down control register"
|
|
bitfld.long 0x34 10. "PD10,Port G pull-down bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x34 9. "PD9,Port G pull-down bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x34 8. "PD8,Port G pull-down bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x34 7. "PD7,Port G pull-down bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x34 6. "PD6,Port G pull-down bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x34 5. "PD5,Port G pull-down bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4. "PD4,Port G pull-down bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x34 3. "PD3,Port G pull-down bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "PD2,Port G pull-down bit y (y=0..10)" "0,1"
|
|
bitfld.long 0x34 1. "PD1,Port G pull-down bit y (y=0..10)" "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "PD0,Port G pull-down bit y (y=0..10)" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PWR_CR5,Power control register"
|
|
bitfld.long 0x0 8. "R1MODE,Main regular range 1 mode" "0: Main regulator in range 1 boost mode.,1: Main regulator in range 1 normal mode."
|
|
tree.end
|
|
sif (cpuis("STM32G473*")||cpuis("STM32G474*")||cpuis("STM32G483*")||cpuis("STM32G484*"))
|
|
tree "QUADSPI (Quad-SPI Interface)"
|
|
base ad:0xA0001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,Clock prescaler"
|
|
bitfld.long 0x0 23. "PMM,Polling match mode" "0,1"
|
|
bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1"
|
|
bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1"
|
|
bitfld.long 0x0 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level"
|
|
bitfld.long 0x0 7. "FSEL,FSEL" "0,1"
|
|
bitfld.long 0x0 6. "DFM,DFM" "0,1"
|
|
bitfld.long 0x0 4. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 1. "ABORT,Abort request" "0,1"
|
|
bitfld.long 0x0 0. "EN,Enable" "0,1"
|
|
line.long 0x4 "DCR,device configuration register"
|
|
hexmask.long.byte 0x4 16.--20. 1. "FSIZE,FLASH memory size"
|
|
bitfld.long 0x4 8.--10. "CSHT,Chip select high time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "CKMODE,Mode 0 / mode 3" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,status register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FLEVEL,FIFO level"
|
|
bitfld.long 0x0 5. "BUSY,Busy" "0,1"
|
|
bitfld.long 0x0 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "SMF,Status match flag" "0,1"
|
|
bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1"
|
|
group.long 0xC++0x27
|
|
line.long 0x0 "FCR,flag clear register"
|
|
bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1"
|
|
bitfld.long 0x0 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1"
|
|
line.long 0x4 "DLR,data length register"
|
|
hexmask.long 0x4 0.--31. 1. "DL,Data length"
|
|
line.long 0x8 "CCR,communication configuration register"
|
|
bitfld.long 0x8 31. "DDRM,Double data rate mode" "0,1"
|
|
bitfld.long 0x8 28. "SIOO,Send instruction only once mode" "0,1"
|
|
bitfld.long 0x8 26.--27. "FMODE,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "DMODE,Data mode" "0,1,2,3"
|
|
hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles"
|
|
bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "ADMODE,Address mode" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "IMODE,Instruction mode" "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction"
|
|
line.long 0xC "AR,address register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Address"
|
|
line.long 0x10 "ABR,ABR"
|
|
hexmask.long 0x10 0.--31. 1. "ALTERNATE,ALTERNATE"
|
|
line.long 0x14 "DR,data register"
|
|
hexmask.long 0x14 0.--31. 1. "DATA,Data"
|
|
line.long 0x18 "PSMKR,polling status mask register"
|
|
hexmask.long 0x18 0.--31. 1. "MASK,Status mask"
|
|
line.long 0x1C "PSMAR,polling status match register"
|
|
hexmask.long 0x1C 0.--31. 1. "MATCH,Status match"
|
|
line.long 0x20 "PIR,polling interval register"
|
|
hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval"
|
|
line.long 0x24 "LPTR,low-power timeout register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period"
|
|
tree.end
|
|
endif
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x0 25. "PLLRDY,Main PLL clock ready flag" "0: PLL unlocked,1: PLL locked"
|
|
bitfld.long 0x0 24. "PLLON,Main PLL enable" "0: PLL OFF,1: PLL ON"
|
|
newline
|
|
bitfld.long 0x0 19. "CSSON,Clock security system enable" "0: Clock security system OFF (clock detector OFF),1: Clock security system ON (Clock detector ON if.."
|
|
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0: HSE crystal oscillator not bypassed,1: HSE crystal oscillator bypassed with external.."
|
|
newline
|
|
rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE oscillator not ready,1: HSE oscillator ready"
|
|
bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE oscillator OFF,1: HSE oscillator ON"
|
|
newline
|
|
rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0: HSI16 oscillator not ready,1: HSI16 oscillator ready"
|
|
bitfld.long 0x0 9. "HSIKERON,HSI16 always enable for peripheral kernels." "0: No effect on HSI16 oscillator.,1: HSI16 oscillator is forced ON even in Stop mode."
|
|
newline
|
|
bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0: HSI16 oscillator OFF,1: HSI16 oscillator ON"
|
|
line.long 0x4 "RCC_ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI16 clock trimming"
|
|
hexmask.long.byte 0x4 16.--23. 1. "HSICAL,HSI16 clock calibration"
|
|
line.long 0x8 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0: MCO is divided by 1,1: MCO is divided by 2,2: MCO is divided by 4,3: MCO is divided by 8,4: MCO is divided by 16,?,?,?"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output"
|
|
newline
|
|
bitfld.long 0x8 11.--13. "PPRE2,APB2 prescaler" "?,?,?,?,4: HCLK divided by 2,5: HCLK divided by 4,6: HCLK divided by 8,7: HCLK divided by 16"
|
|
bitfld.long 0x8 8.--10. "PPRE1,APB1 prescaler" "?,?,?,?,4: HCLK divided by 2,5: HCLK divided by 4,6: HCLK divided by 8,7: HCLK divided by 16"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "HPRE,AHB prescaler"
|
|
rbitfld.long 0x8 2.--3. "SWS,System clock switch status" "0: Reserved must be kept at reset value,1: HSI16 oscillator used as system clock,2: HSE used as system clock,3: PLL used as system clock"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SW,System clock switch" "0: Reserved must be kept at reset value,1: HSI16 selected as system clock,2: HSE selected as system clock,3: PLL selected as system clock"
|
|
line.long 0xC "RCC_PLLCFGR,PLL configuration register"
|
|
hexmask.long.byte 0xC 27.--31. 1. "PLLPDIV,Main PLLP division factor"
|
|
bitfld.long 0xC 25.--26. "PLLR,Main PLL division factor for PLL R clock (system clock)" "0: PLLR = 2,1: PLLR = 4,2: PLLR = 6,3: PLLR = 8"
|
|
newline
|
|
bitfld.long 0xC 24. "PLLREN,PLL R clock output enable" "0: PLL R clock output disable,1: PLL R clock output enable"
|
|
bitfld.long 0xC 21.--22. "PLLQ,Main PLL division factor for PLL Q clock." "0: PLLQ = 2,1: PLLQ = 4,2: PLLQ = 6,3: PLLQ = 8"
|
|
newline
|
|
bitfld.long 0xC 20. "PLLQEN,Main PLL Q clock output enable" "0: PLL Q clock output disable,1: PLL Q clock output enable"
|
|
bitfld.long 0xC 17. "PLLP,Main PLL division factor for PLL P clock." "0: PLLP = 7,1: PLLP = 17"
|
|
newline
|
|
bitfld.long 0xC 16. "PLLPEN,Main PLL PLL P clock output enable" "0: PLL P clock output disable,1: PLL P clock output enable"
|
|
hexmask.long.byte 0xC 8.--14. 1. "PLLN,Main PLL multiplication factor for VCO"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "PLLM,Division factor for the main PLL input clock"
|
|
bitfld.long 0xC 0.--1. "PLLSRC,Main PLL entry clock source" "0: No clock sent to PLL,1: No clock sent to PLL,2: HSI16 clock selected as PLL clock entry,3: HSE clock selected as PLL clock entry"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RCC_CIER,Clock interrupt enable register"
|
|
bitfld.long 0x0 10. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled,1: HSI48 ready interrupt enabled"
|
|
bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: Clock security interrupt caused by LSE clock..,1: Clock security interrupt caused by LSE clock.."
|
|
newline
|
|
bitfld.long 0x0 5. "PLLRDYIE,PLL ready interrupt enable" "0: PLL lock interrupt disabled,1: PLL lock interrupt enabled"
|
|
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled,1: HSE ready interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI16 ready interrupt enable" "0: HSI16 ready interrupt disabled,1: HSI16 ready interrupt enabled"
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled,1: LSE ready interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled,1: LSI ready interrupt enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x0 10. "HSI48RDYF,HSI48 ready interrupt flag" "0: No clock ready interrupt caused by the HSI48..,1: Clock ready interrupt caused by the HSI48.."
|
|
bitfld.long 0x0 9. "LSECSSF,LSE Clock security system interrupt flag" "0: No clock security interrupt caused by LSE clock..,1: Clock security interrupt caused by LSE clock.."
|
|
newline
|
|
bitfld.long 0x0 8. "CSSF,Clock security system interrupt flag" "0: No clock security interrupt caused by HSE clock..,1: Clock security interrupt caused by HSE clock.."
|
|
bitfld.long 0x0 5. "PLLRDYF,PLL ready interrupt flag" "0: No clock ready interrupt caused by PLL lock,1: Clock ready interrupt caused by PLL lock"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE oscillator"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI16 ready interrupt flag" "0: No clock ready interrupt caused by the HSI16..,1: Clock ready interrupt caused by the HSI16.."
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE oscillator"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: No clock ready interrupt caused by the LSI..,1: Clock ready interrupt caused by the LSI oscillator"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,Clock interrupt clear register"
|
|
bitfld.long 0x0 10. "HSI48RDYC,HSI48 oscillator ready interrupt clear" "0: No effect,1: Clear the HSI48RDYC flag"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
newline
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
bitfld.long 0x0 5. "PLLRDYC,PLL ready interrupt clear" "0: No effect,1: Clear PLLRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI16 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: LSERDYF cleared"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: LSIRDYF cleared"
|
|
group.long 0x28++0xB
|
|
line.long 0x0 "RCC_AHB1RSTR,AHB1 peripheral reset register"
|
|
bitfld.long 0x0 12. "CRCRST,CRC reset" "0: No effect,1: Reset CRC"
|
|
bitfld.long 0x0 8. "FLASHRST,Flash memory interface reset" "0: No effect,1: Reset Flash memory interface"
|
|
newline
|
|
bitfld.long 0x0 4. "FMACRST,Set and cleared by software" "0: No effect,1: Reset FMAC"
|
|
bitfld.long 0x0 3. "CORDICRST,Set and cleared by software" "0: No effect,1: Reset CORDIC"
|
|
newline
|
|
bitfld.long 0x0 2. "DMAMUX1RST,Set and cleared by software." "0: No effect,1: Reset DMAMUX1"
|
|
bitfld.long 0x0 1. "DMA2RST,DMA2 reset" "0: No effect,1: Reset DMA2"
|
|
newline
|
|
bitfld.long 0x0 0. "DMA1RST,DMA1 reset" "0: No effect,1: Reset DMA1"
|
|
line.long 0x4 "RCC_AHB2RSTR,AHB2 peripheral reset register"
|
|
bitfld.long 0x4 26. "RNGRST,RNG reset" "0: No effect,1: Reset RNG"
|
|
bitfld.long 0x4 24. "AESRST,AESRST reset" "0: No effect,1: Reset AES"
|
|
newline
|
|
bitfld.long 0x4 19. "DAC4RST,DAC4 reset" "0: No effect,1: Reset DAC4"
|
|
bitfld.long 0x4 18. "DAC3RST,DAC3 reset" "0: No effect,1: Reset DAC3"
|
|
newline
|
|
bitfld.long 0x4 17. "DAC2RST,DAC2 reset" "0: No effect,1: Reset DAC2"
|
|
bitfld.long 0x4 16. "DAC1RST,DAC1 reset" "0: No effect,1: Reset DAC1"
|
|
newline
|
|
bitfld.long 0x4 14. "ADC345RST,ADC345 reset" "0: No effect,1: Reset ADC345"
|
|
bitfld.long 0x4 13. "ADC12RST,ADC12 reset" "0: No effect,1: Reset ADC12 interface"
|
|
newline
|
|
bitfld.long 0x4 6. "GPIOGRST,IO port G reset" "0: No effect,1: Reset IO port G"
|
|
bitfld.long 0x4 5. "GPIOFRST,IO port F reset" "0: No effect,1: Reset IO port F"
|
|
newline
|
|
bitfld.long 0x4 4. "GPIOERST,IO port E reset" "0: No effect,1: Reset IO port E"
|
|
bitfld.long 0x4 3. "GPIODRST,IO port D reset" "0: No effect,1: Reset IO port D"
|
|
newline
|
|
bitfld.long 0x4 2. "GPIOCRST,IO port C reset" "0: No effect,1: Reset IO port C"
|
|
bitfld.long 0x4 1. "GPIOBRST,IO port B reset" "0: No effect,1: Reset IO port B"
|
|
newline
|
|
bitfld.long 0x4 0. "GPIOARST,IO port A reset" "0: No effect,1: Reset IO port A"
|
|
line.long 0x8 "RCC_AHB3RSTR,AHB3 peripheral reset register"
|
|
bitfld.long 0x8 8. "QSPIRST,QUADSPI reset" "0: No effect,1: Reset QUADSPI"
|
|
bitfld.long 0x8 0. "FMCRST,Flexible static memory controller reset" "0: No effect,1: Reset FSMC"
|
|
group.long 0x38++0xB
|
|
line.long 0x0 "RCC_APB1RSTR1,APB1 peripheral reset register 1"
|
|
bitfld.long 0x0 31. "LPTIM1RST,Low Power Timer 1 reset" "0: No effect,1: Reset LPTIM1"
|
|
bitfld.long 0x0 30. "I2C3RST,I2C3 reset" "0: No effect,1: Reset I2C3 interface"
|
|
newline
|
|
bitfld.long 0x0 28. "PWRRST,Power interface reset" "0: No effect,1: Reset PWR"
|
|
bitfld.long 0x0 25. "FDCANRST,FDCAN reset" "0: No effect,1: Reset the FDCAN"
|
|
newline
|
|
bitfld.long 0x0 23. "USBRST,USB device reset" "0: No effect,1: Reset USB device"
|
|
bitfld.long 0x0 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
|
|
newline
|
|
bitfld.long 0x0 21. "I2C1RST,I2C1 reset" "0: No effect,1: Reset I2C1"
|
|
bitfld.long 0x0 20. "UART5RST,UART5 reset" "0: No effect,1: Reset UART5"
|
|
newline
|
|
bitfld.long 0x0 19. "UART4RST,UART4 reset" "0: No effect,1: Reset UART4"
|
|
bitfld.long 0x0 18. "USART3RST,USART3 reset" "0: No effect,1: Reset USART3"
|
|
newline
|
|
bitfld.long 0x0 17. "USART2RST,USART2 reset" "0: No effect,1: Reset USART2"
|
|
bitfld.long 0x0 15. "SPI3RST,SPI3 reset" "0: No effect,1: Reset SPI3"
|
|
newline
|
|
bitfld.long 0x0 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
|
|
bitfld.long 0x0 8. "CRSRST,CRS reset" "0: No effect,1: Reset CRS"
|
|
newline
|
|
bitfld.long 0x0 5. "TIM7RST,TIM7 timer reset" "0: No effect,1: Reset TIM7"
|
|
bitfld.long 0x0 4. "TIM6RST,TIM6 timer reset" "0: No effect,1: Reset TIM7"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM5RST,TIM5 timer reset" "0: No effect,1: Reset TIM5"
|
|
bitfld.long 0x0 2. "TIM4RST,TIM3 timer reset" "0: No effect,1: Reset TIM3"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM3RST,TIM3 timer reset" "0: No effect,1: Reset TIM3"
|
|
bitfld.long 0x0 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
|
|
line.long 0x4 "RCC_APB1RSTR2,APB1 peripheral reset register 2"
|
|
bitfld.long 0x4 8. "UCPD1RST,UCPD1 reset" "0: No effect,1: Reset UCPD1"
|
|
bitfld.long 0x4 1. "I2C4RST,I2C4 reset" "0: No effect,1: Reset I2C4"
|
|
newline
|
|
bitfld.long 0x4 0. "LPUART1RST,Low-power UART 1 reset" "0: No effect,1: Reset LPUART1"
|
|
line.long 0x8 "RCC_APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x8 26. "HRTIM1RST,HRTIM1 reset" "0: No effect,1: Reset HRTIM1"
|
|
bitfld.long 0x8 21. "SAI1RST,Serial audio interface 1 (SAI1) reset" "0: No effect,1: Reset SAI1"
|
|
newline
|
|
bitfld.long 0x8 20. "TIM20RST,TIM20 reset" "0: No effect,1: Reset TIM20"
|
|
bitfld.long 0x8 18. "TIM17RST,TIM17 timer reset" "0: No effect,1: Reset TIM17 timer"
|
|
newline
|
|
bitfld.long 0x8 17. "TIM16RST,TIM16 timer reset" "0: No effect,1: Reset TIM16 timer"
|
|
bitfld.long 0x8 16. "TIM15RST,TIM15 timer reset" "0: No effect,1: Reset TIM15 timer"
|
|
newline
|
|
bitfld.long 0x8 15. "SPI4RST,SPI4 reset" "0: No effect,1: Reset SPI4"
|
|
bitfld.long 0x8 14. "USART1RST,USART1 reset" "0: No effect,1: Reset USART1"
|
|
newline
|
|
bitfld.long 0x8 13. "TIM8RST,TIM8 timer reset" "0: No effect,1: Reset TIM8 timer"
|
|
bitfld.long 0x8 12. "SPI1RST,SPI1 reset" "0: No effect,1: Reset SPI1"
|
|
newline
|
|
bitfld.long 0x8 11. "TIM1RST,TIM1 timer reset" "0: No effect,1: Reset TIM1 timer"
|
|
bitfld.long 0x8 0. "SYSCFGRST,SYSCFG + COMP + OPAMP + VREFBUF reset" "0: No effect,1: Reset SYSCFG + COMP + OPAMP + VREFBUF"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "RCC_AHB1ENR,AHB1 peripheral clock enable register"
|
|
bitfld.long 0x0 12. "CRCEN,CRC clock enable" "0: CRC clock disable,1: CRC clock enable"
|
|
bitfld.long 0x0 8. "FLASHEN,Flash memory interface clock enable" "0: Flash memory interface clock disable,1: Flash memory interface clock enable"
|
|
newline
|
|
bitfld.long 0x0 4. "FMACEN,FMAC enable" "0: FMAC clock disabled,1: FMAC clock enabled"
|
|
bitfld.long 0x0 3. "CORDICEN,CORDIC clock enable" "0: CORDIC clock disabled,1: CORDIC clock enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "DMAMUX1EN,DMAMUX1 clock enable" "0: DMAMUX1 clock disabled,1: DMAMUX1 clock enabled"
|
|
bitfld.long 0x0 1. "DMA2EN,DMA2 clock enable" "0: DMA2 clock disable,1: DMA2 clock enable"
|
|
newline
|
|
bitfld.long 0x0 0. "DMA1EN,DMA1 clock enable" "0: DMA1 clock disable,1: DMA1 clock enable"
|
|
line.long 0x4 "RCC_AHB2ENR,AHB2 peripheral clock enable register"
|
|
bitfld.long 0x4 26. "RNGEN,RNG enable" "0: RNG disabled,1: RNG enabled"
|
|
bitfld.long 0x4 24. "AESEN,AES clock enable" "0: AES clock disabled,1: AES clock enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DAC4EN,DAC4 clock enable" "0: DAC4 clock disabled,1: DAC4 clock enabled"
|
|
bitfld.long 0x4 18. "DAC3EN,DAC3 clock enable" "0: DAC3 clock disabled,1: DAC3 clock enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "DAC2EN,DAC2 clock enable" "0: DAC2 clock disabled,1: DAC2 clock enabled"
|
|
bitfld.long 0x4 16. "DAC1EN,DAC1 clock enable" "0: DAC1 clock disabled,1: DAC1 clock enabled"
|
|
newline
|
|
bitfld.long 0x4 14. "ADC345EN,ADC345 clock enable" "0: ADC345 clock disabled,1: ADC345 clock enabled"
|
|
bitfld.long 0x4 13. "ADC12EN,ADC12 clock enable" "0: ADC12 clock disabled,1: ADC12 clock enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "GPIOGEN,IO port G clock enable" "0: IO port G clock disabled,1: IO port G clock enabled"
|
|
bitfld.long 0x4 5. "GPIOFEN,IO port F clock enable" "0: IO port F clock disabled,1: IO port F clock enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "GPIOEEN,IO port E clock enable" "0: IO port E clock disabled,1: IO port E clock enabled"
|
|
bitfld.long 0x4 3. "GPIODEN,IO port D clock enable" "0: IO port D clock disabled,1: IO port D clock enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "GPIOCEN,IO port C clock enable" "0: IO port C clock disabled,1: IO port C clock enabled"
|
|
bitfld.long 0x4 1. "GPIOBEN,IO port B clock enable" "0: IO port B clock disabled,1: IO port B clock enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "GPIOAEN,IO port A clock enable" "0: IO port A clock disabled,1: IO port A clock enabled"
|
|
line.long 0x8 "RCC_AHB3ENR,AHB3 peripheral clock enable register"
|
|
bitfld.long 0x8 8. "QSPIEN,QUADSPI memory interface clock enable" "0: QUADSPI clock disable,1: QUADSPI clock enable"
|
|
bitfld.long 0x8 0. "FMCEN,Flexible static memory controller clock enable" "0: FSMC clock disable,1: FSMC clock enable"
|
|
group.long 0x58++0xB
|
|
line.long 0x0 "RCC_APB1ENR1,APB1 peripheral clock enable register 1"
|
|
bitfld.long 0x0 31. "LPTIM1EN,Low power timer 1 clock enable" "0: LPTIM1 clock disabled,1: LPTIM1 clock enabled"
|
|
bitfld.long 0x0 30. "I2C3EN,I2C3 clock enable" "0: I2C3 clock disabled,1: I2C3 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "PWREN,Power interface clock enable" "0: Power interface clock disabled,1: Power interface clock enabled"
|
|
bitfld.long 0x0 25. "FDCANEN,FDCAN clock enable" "0: FDCAN clock disabled,1: FDCAN clock enabled"
|
|
newline
|
|
bitfld.long 0x0 23. "USBEN,USB device clock enable" "0: USB device clock disabled,1: USB device clock enabled"
|
|
bitfld.long 0x0 22. "I2C2EN,I2C2 clock enable" "0: I2C2 clock disabled,1: I2C2 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "I2C1EN,I2C1 clock enable" "0: I2C1 clock disabled,1: I2C1 clock enabled"
|
|
bitfld.long 0x0 20. "UART5EN,UART5 clock enable" "0: UART5 clock disabled,1: UART5 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "UART4EN,UART4 clock enable" "0: UART4 clock disabled,1: UART4 clock enabled"
|
|
bitfld.long 0x0 18. "USART3EN,USART3 clock enable" "0: USART3 clock disabled,1: USART3 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 17. "USART2EN,USART2 clock enable" "0: USART2 clock disabled,1: USART2 clock enabled"
|
|
bitfld.long 0x0 15. "SPI3EN,SPI3 clock enable" "0: SPI3 clock disabled,1: SPI3 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "SPI2EN,SPI2 clock enable" "0: SPI2 clock disabled,1: SPI2 clock enabled"
|
|
bitfld.long 0x0 11. "WWDGEN,Window watchdog clock enable" "0: Window watchdog clock disabled,1: Window watchdog clock enabled"
|
|
newline
|
|
bitfld.long 0x0 10. "RTCAPBEN,RTC APB clock enable" "0: RTC APB clock disabled,1: RTC APB clock enabled"
|
|
bitfld.long 0x0 8. "CRSEN,CRS Recovery System clock enable" "0: CRS clock disabled,1: CRS clock enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "TIM7EN,TIM7 timer clock enable" "0: TIM7 clock disabled,1: TIM7 clock enabled"
|
|
bitfld.long 0x0 4. "TIM6EN,TIM6 timer clock enable" "0: TIM6 clock disabled,1: TIM6 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM5EN,TIM5 timer clock enable" "0: TIM5 clock disabled,1: TIM5 clock enabled"
|
|
bitfld.long 0x0 2. "TIM4EN,TIM4 timer clock enable" "0: TIM4 clock disabled,1: TIM4 clock enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM3EN,TIM3 timer clock enable" "0: TIM3 clock disabled,1: TIM3 clock enabled"
|
|
bitfld.long 0x0 0. "TIM2EN,TIM2 timer clock enable" "0: TIM2 clock disabled,1: TIM2 clock enabled"
|
|
line.long 0x4 "RCC_APB1ENR2,APB1 peripheral clock enable register 2"
|
|
bitfld.long 0x4 8. "UCPD1EN,UCPD1 clock enable" "0: UCPD1 clock disable,1: UCPD1 clock enable"
|
|
bitfld.long 0x4 1. "I2C4EN,I2C4 clock enable" "0: I2C4 clock disabled,1: I2C4 clock enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "LPUART1EN,Low power UART 1 clock enable" "0: LPUART1 clock disable,1: LPUART1 clock enable"
|
|
line.long 0x8 "RCC_APB2ENR,APB2 peripheral clock enable register"
|
|
bitfld.long 0x8 26. "HRTIM1EN,HRTIM1 clock enable" "0: HRTIM1 clock disabled,1: HRTIM1 clock enable"
|
|
bitfld.long 0x8 21. "SAI1EN,SAI1 clock enable" "0: SAI1 clock disabled,1: SAI1 clock enabled"
|
|
newline
|
|
bitfld.long 0x8 20. "TIM20EN,TIM20 timer clock enable" "0: TIM20 clock disabled,1: TIM20 clock enabled"
|
|
bitfld.long 0x8 18. "TIM17EN,TIM17 timer clock enable" "0: TIM17 timer clock disabled,1: TIM17 timer clock enabled"
|
|
newline
|
|
bitfld.long 0x8 17. "TIM16EN,TIM16 timer clock enable" "0: TIM16 timer clock disabled,1: TIM16 timer clock enabled"
|
|
bitfld.long 0x8 16. "TIM15EN,TIM15 timer clock enable" "0: TIM15 timer clock disabled,1: TIM15 timer clock enabled"
|
|
newline
|
|
bitfld.long 0x8 15. "SPI4EN,SPI4 clock enable" "0: SPI4 clock disabled,1: SPI4 clock enabled"
|
|
bitfld.long 0x8 14. "USART1EN,USART1clock enable" "0: USART1clock disabled,1: USART1clock enabled"
|
|
newline
|
|
bitfld.long 0x8 13. "TIM8EN,TIM8 timer clock enable" "0: TIM8 timer clock disabled,1: TIM8 timer clock enabled"
|
|
bitfld.long 0x8 12. "SPI1EN,SPI1 clock enable" "0: SPI1 clock disabled,1: SPI1 clock enabled"
|
|
newline
|
|
bitfld.long 0x8 11. "TIM1EN,TIM1 timer clock enable" "0: TIM1 timer clock disabled,1: TIM1P timer clock enabled"
|
|
bitfld.long 0x8 0. "SYSCFGEN,SYSCFG + COMP + VREFBUF + OPAMP clock enable" "0: SYSCFG + COMP + VREFBUF + OPAMP clock disabled,1: SYSCFG + COMP + VREFBUF + OPAMP clock enabled"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "RCC_AHB1SMENR,AHB1 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x0 12. "CRCSMEN,CRC clocks enable during Sleep and Stop modes" "0: CRC clocks disabled by the clock gating during..,1: CRC clocks enabled by the clock.."
|
|
bitfld.long 0x0 9. "SRAM1SMEN,SRAM1 interface clocks enable during Sleep and Stop modes" "0: SRAM1 interface clocks disabled by the clock..,1: SRAM1 interface clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 8. "FLASHSMEN,Flash memory interface clocks enable during Sleep and Stop modes" "0: Flash memory interface clocks disabled by the..,1: Flash memory interface clocks enabled by the.."
|
|
bitfld.long 0x0 4. "FMACSMEN,FMACSM clock enable." "0: FMACSM clocks disabled by the clock..,1: FMACSM clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 3. "CORDICSMEN,CORDICSM clock enable." "0: CORDICSM clocks disabled.,1: CORDICSM clocks enabled."
|
|
bitfld.long 0x0 2. "DMAMUX1SMEN,DMAMUX1 clock enable during Sleep and Stop modes." "0: DMAMUX1 clocks disabled by the clock..,1: DMAMUX1 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 1. "DMA2SMEN,DMA2 clocks enable during Sleep and Stop modes" "0: DMA2 clocks disabled by the clock..,1: DMA2 clocks enabled by the clock.."
|
|
bitfld.long 0x0 0. "DMA1SMEN,DMA1 clocks enable during Sleep and Stop modes" "0: DMA1 clocks disabled by the clock..,1: DMA1 clocks enabled by the clock.."
|
|
line.long 0x4 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x4 26. "RNGEN,RNG enable" "0: RNG disabled,1: RNG enabled"
|
|
bitfld.long 0x4 24. "AESSMEN,AESM clocks enable" "0: AESM clocks disabled,1: AESM clocks enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DAC4SMEN,DAC4 clock enable" "0: DAC4 clock disabled,1: DAC4 clock enabled during sleep and stop modes"
|
|
bitfld.long 0x4 18. "DAC3SMEN,DAC3 clock enable" "0: DAC3 clock disabled,1: DAC3 clock enabled during sleep and stop modes"
|
|
newline
|
|
bitfld.long 0x4 17. "DAC2SMEN,DAC2 clock enable" "0: DAC2 clock disabled,1: DAC2 clock enabled during sleep and stop modes"
|
|
bitfld.long 0x4 16. "DAC1SMEN,DAC1 clock enable" "0: DAC1 clock disabled,1: DAC1 clock enabled during sleep and stop modes"
|
|
newline
|
|
bitfld.long 0x4 14. "ADC345SMEN,ADC345 clock enable" "0: ADC345 clock disabled,1: ADC345 clock enabled"
|
|
bitfld.long 0x4 13. "ADC12SMEN,ADC12 clocks enable during Sleep and Stop modes" "0: ADC12 clocks disabled by the clock gating during..,1: ADC12 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 10. "SRAM2SMEN,SRAM2 interface clocks enable during Sleep and Stop modes" "0: SRAM2 interface clocks disabled by the clock..,1: SRAM2 interface clocks enabled by the clock.."
|
|
bitfld.long 0x4 9. "CCMSRAMSMEN,CCM SRAM interface clocks enable during Sleep and Stop modes" "0: CCM SRAM interface clocks disabled by the clock..,1: CCM SRAM interface clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 6. "GPIOGSMEN,IO port G clocks enable during Sleep and Stop modes" "0: IO port G clocks disabled by the clock..,1: IO port G clocks enabled by the clock.."
|
|
bitfld.long 0x4 5. "GPIOFSMEN,IO port F clocks enable during Sleep and Stop modes" "0: IO port F clocks disabled by the clock..,1: IO port F clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 4. "GPIOESMEN,IO port E clocks enable during Sleep and Stop modes" "0: IO port E clocks disabled by the clock..,1: IO port E clocks enabled by the clock.."
|
|
bitfld.long 0x4 3. "GPIODSMEN,IO port D clocks enable during Sleep and Stop modes" "0: IO port D clocks disabled by the clock..,1: IO port D clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 2. "GPIOCSMEN,IO port C clocks enable during Sleep and Stop modes" "0: IO port C clocks disabled by the clock..,1: IO port C clocks enabled by the clock.."
|
|
bitfld.long 0x4 1. "GPIOBSMEN,IO port B clocks enable during Sleep and Stop modes" "0: IO port B clocks disabled by the clock..,1: IO port B clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 0. "GPIOASMEN,IO port A clocks enable during Sleep and Stop modes" "0: IO port A clocks disabled by the clock..,1: IO port A clocks enabled by the clock.."
|
|
line.long 0x8 "RCC_AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x8 8. "QSPISMEN,QUADSPI memory interface clock enable during Sleep and Stop modes" "0: QUADSPI clock disabled by the clock gating..,1: QUADSPI clock enabled by the clock.."
|
|
bitfld.long 0x8 0. "FMCSMEN,Flexible static memory controller clocks enable during Sleep and Stop modes" "0: FSMC clocks disabled by the clock..,1: FSMC clocks enabled by the clock.."
|
|
group.long 0x78++0xB
|
|
line.long 0x0 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1"
|
|
bitfld.long 0x0 31. "LPTIM1SMEN,Low power timer 1 clocks enable during Sleep and Stop modes" "0: LPTIM1 clocks disabled by the clock gating..,1: LPTIM1 clocks enabled by the clock.."
|
|
bitfld.long 0x0 30. "I2C3SMEN,I2C3 clocks enable during Sleep and Stop modes" "0: I2C3 clocks disabled by the clock..,1: I2C3 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 28. "PWRSMEN,Power interface clocks enable during Sleep and Stop modes" "0: Power interface clocks disabled by the clock..,1: Power interface clocks enabled by the clock.."
|
|
bitfld.long 0x0 25. "FDCANSMEN,FDCAN clocks enable during Sleep and Stop modes" "0: FDCAN clocks disabled by the clock..,1: FDCAN clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 23. "USBSMEN,USB device clocks enable during Sleep and Stop modes" "0: USB device clocks disabled by the clock..,1: USB device clocks enabled by the clock.."
|
|
bitfld.long 0x0 22. "I2C2SMEN,I2C2 clocks enable during Sleep and Stop modes" "0: I2C2 clocks disabled by the clock..,1: I2C2 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 21. "I2C1SMEN,I2C1 clocks enable during Sleep and Stop modes" "0: I2C1 clocks disabled by the clock..,1: I2C1 clocks enabled by the clock.."
|
|
bitfld.long 0x0 20. "UART5SMEN,UART5 clocks enable during Sleep and Stop modes" "0: UART5 clocks disabled by the clock..,1: UART5 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 19. "UART4SMEN,UART4 clocks enable during Sleep and Stop modes" "0: UART4 clocks disabled by the clock..,1: UART4 clocks enabled by the clock.."
|
|
bitfld.long 0x0 18. "USART3SMEN,USART3 clocks enable during Sleep and Stop modes" "0: USART3 clocks disabled by the clock..,1: USART3 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 17. "USART2SMEN,USART2 clocks enable during Sleep and Stop modes" "0: USART2 clocks disabled by the clock..,1: USART2 clocks enabled by the clock.."
|
|
bitfld.long 0x0 15. "SPI3SMEN,SPI3 clocks enable during Sleep and Stop modes" "0: SPI3 clocks disabled by the clock..,1: SPI3 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 14. "SPI2SMEN,SPI2 clocks enable during Sleep and Stop modes" "0: SPI2 clocks disabled by the clock..,1: SPI2 clocks enabled by the clock.."
|
|
bitfld.long 0x0 11. "WWDGSMEN,Window watchdog clocks enable during Sleep and Stop modes" "0: Window watchdog clocks disabled by the clock..,1: Window watchdog clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 10. "RTCAPBSMEN,RTC APB clock enable during Sleep and Stop modes" "0: RTC APB clock disabled by the clock..,1: RTC APB clock enabled by the clock.."
|
|
bitfld.long 0x0 8. "CRSSMEN,CRS timer clocks enable during Sleep and Stop modes" "0: CRS clocks disabled by the clock..,1: CRS clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 5. "TIM7SMEN,TIM7 timer clocks enable during Sleep and Stop modes" "0: TIM7 clocks disabled by the clock..,1: TIM7 clocks enabled by the clock.."
|
|
bitfld.long 0x0 4. "TIM6SMEN,TIM6 timer clocks enable during Sleep and Stop modes" "0: TIM6 clocks disabled by the clock..,1: TIM6 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIM5SMEN,TIM5 timer clocks enable during Sleep and Stop modes" "0: TIM5 clocks disabled by the clock..,1: TIM5 clocks enabled by the clock.."
|
|
bitfld.long 0x0 2. "TIM4SMEN,TIM4 timer clocks enable during Sleep and Stop modes" "0: TIM4 clocks disabled by the clock..,1: TIM4 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x0 1. "TIM3SMEN,TIM3 timer clocks enable during Sleep and Stop modes" "0: TIM3 clocks disabled by the clock..,1: TIM3 clocks enabled by the clock.."
|
|
bitfld.long 0x0 0. "TIM2SMEN,TIM2 timer clocks enable during Sleep and Stop modes" "0: TIM2 clocks disabled by the clock..,1: TIM2 clocks enabled by the clock.."
|
|
line.long 0x4 "RCC_APB1SMENR2,APB1 peripheral clocks enable in Sleep and Stop modes register 2"
|
|
bitfld.long 0x4 8. "UCPD1SMEN,UCPD1 clocks enable during Sleep and Stop modes" "0: UCPD1 clocks disabled by the clock gating during..,1: UCPD1 clocks enabled by the clock.."
|
|
bitfld.long 0x4 1. "I2C4SMEN,I2C4 clocks enable during Sleep and Stop modes" "0: I2C4 clocks disabled by the clock gating during..,1: I2C4 clock enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x4 0. "LPUART1SMEN,Low power UART 1 clocks enable during Sleep and Stop modes" "0: LPUART1 clocks disabled by the clock..,1: LPUART1 clocks enabled by the clock.."
|
|
line.long 0x8 "RCC_APB2SMENR,APB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x8 26. "HRTIM1SMEN,HRTIM1 timer clocks enable during Sleep and Stop modes" "0: HRTIM1 clocks disabled by the clock..,1: HRTIM1 clocks enabled by the clock.."
|
|
bitfld.long 0x8 21. "SAI1SMEN,SAI1 clocks enable during Sleep and Stop modes" "0: SAI1 clocks disabled by the clock..,1: SAI1 clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x8 20. "TIM20SMEN,TIM20 timer clocks enable during Sleep and Stop modes" "0: TIM20 clocks disabled by the clock..,1: TIM20 clocks enabled by the clock.."
|
|
bitfld.long 0x8 18. "TIM17SMEN,TIM17 timer clocks enable during Sleep and Stop modes" "0: TIM17 timer clocks disabled by the clock..,1: TIM17 timer clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x8 17. "TIM16SMEN,TIM16 timer clocks enable during Sleep and Stop modes" "0: TIM16 timer clocks disabled by the clock gating..,1: TIM16 timer clocks enabled by the clock.."
|
|
bitfld.long 0x8 16. "TIM15SMEN,TIM15 timer clocks enable during Sleep and Stop modes" "0: TIM15 timer clocks disabled by the clock..,1: TIM15 timer clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x8 15. "SPI4SMEN,SPI4 timer clocks enable during Sleep and Stop modes" "0: SPI4 clocks disabled by the clock..,1: SPI4 clocks enabled by the clock.."
|
|
bitfld.long 0x8 14. "USART1SMEN,USART1clocks enable during Sleep and Stop modes" "0: USART1clocks disabled by the clock..,1: USART1clocks enabled by the clock.."
|
|
newline
|
|
bitfld.long 0x8 13. "TIM8SMEN,TIM8 timer clocks enable during Sleep and Stop modes" "0: TIM8 timer clocks disabled by the clock..,1: TIM8 timer clocks enabled by the clock.."
|
|
bitfld.long 0x8 12. "SPI1SMEN,SPI1 clocks enable during Sleep and Stop modes" "0: SPI1 clocks disabled by the clock gating..,1: SPI1 clocks enabled by the clock gating.."
|
|
newline
|
|
bitfld.long 0x8 11. "TIM1SMEN,TIM1 timer clocks enable during Sleep and Stop modes" "0: TIM1 timer clocks disabled by the clock..,1: TIM1P timer clocks enabled by the clock.."
|
|
bitfld.long 0x8 0. "SYSCFGSMEN,SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes" "0: SYSCFG + COMP + VREFBUF + OPAMP clocks disabled..,1: SYSCFG + COMP + VREFBUF + OPAMP clocks enabled.."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "RCC_CCIPR,Peripherals independent clock configuration register"
|
|
bitfld.long 0x0 30.--31. "ADC345SEL,ADC3/4/5 clock source selection" "0: No clock selected,1: PLL P clock selected as ADC345 clock,2: System clock selected as ADC3/4/5 clock,3: Reserved."
|
|
bitfld.long 0x0 28.--29. "ADC12SEL,ADC1/2 clock source selection" "0: No clock selected,1: PLL P clock selected as ADC1/2 clock,2: System clock selected as ADC1/2 clock,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "CLK48SEL,48 MHz clock source selection" "0: HSI48 clock selected as 48 MHz clock,?,2: PLL Q clock (PLL48M1CLK) selected as 48 MHz clock,3: Reserved must be kept at reset value"
|
|
bitfld.long 0x0 24.--25. "FDCANSEL,None" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "I2S23SEL,clock source selection" "0: System clock selected as I2S23 clock,1: PLL Q clock selected as I2S23 clock,2: Clock provided on I2S_CKIN pin is selected as..,3: HSI16 clock selected as I2S23 clock."
|
|
bitfld.long 0x0 20.--21. "SAI1SEL,clock source selection" "0: System clock selected as SAI clock,1: PLL Q clock selected as SAI clock,2: Clock provided on I2S_CKIN pin selected as SAI..,3: HSI16 clock selected as SAI clock"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "LPTIM1SEL,Low power timer 1 clock source selection" "0: PCLK selected as LPTIM1 clock,1: LSI clock selected as LPTIM1 clock,2: HSI16 clock selected as LPTIM1 clock,3: LSE clock selected as LPTIM1 clock"
|
|
bitfld.long 0x0 16.--17. "I2C3SEL,I2C3 clock source selection" "0: PCLK selected as I2C3 clock,1: System clock (SYSCLK) selected as I2C3 clock,2: HSI16 clock selected as I2C3 clock,?"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "I2C2SEL,I2C2 clock source selection" "0: PCLK selected as I2C2 clock,1: System clock (SYSCLK) selected as I2C2 clock,2: HSI16 clock selected as I2C2 clock,?"
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK selected as I2C1 clock,1: System clock (SYSCLK) selected as I2C1 clock,2: HSI16 clock selected as I2C1 clock,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0: PCLK selected as LPUART1 clock,1: System clock (SYSCLK) selected as LPUART1 clock,2: HSI16 clock selected as LPUART1 clock,3: LSE clock selected as LPUART1 clock"
|
|
bitfld.long 0x0 8.--9. "UART5SEL,UART5 clock source selection" "0: PCLK selected as UART5 clock,1: System clock (SYSCLK) selected as UART5 clock,2: HSI16 clock selected as UART5 clock,3: LSE clock selected as UART5 clock"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "UART4SEL,UART4 clock source selection" "0: PCLK selected as UART4 clock,1: System clock (SYSCLK) selected as UART4 clock,2: HSI16 clock selected as UART4 clock,3: LSE clock selected as UART4 clock"
|
|
bitfld.long 0x0 4.--5. "USART3SEL,USART3 clock source selection" "0: PCLK selected as USART3 clock,1: System clock (SYSCLK) selected as USART3 clock,2: HSI16 clock selected as USART3 clock,3: LSE clock selected as USART3 clock"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "USART2SEL,USART2 clock source selection" "0: PCLK selected as USART2 clock,1: System clock (SYSCLK) selected as USART2 clock,2: HSI16 clock selected as USART2 clock,3: LSE clock selected as USART2 clock"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK selected as USART1 clock,1: System clock (SYSCLK) selected as USART1 clock,2: HSI16 clock selected as USART1 clock,3: LSE clock selected as USART1 clock"
|
|
group.long 0x90++0xF
|
|
line.long 0x0 "RCC_BDCR,RTC domain control register"
|
|
bitfld.long 0x0 25. "LSCOSEL,Low speed clock output selection" "0: LSI clock selected,1: LSE clock selected"
|
|
bitfld.long 0x0 24. "LSCOEN,Low speed clock output enable" "0: Low speed clock output (LSCO) disable,1: Low speed clock output (LSCO) enable"
|
|
newline
|
|
bitfld.long 0x0 16. "BDRST,RTC domain software reset" "0: Reset not activated,1: Reset the entire RTC domain"
|
|
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: RTC clock disabled,1: RTC clock enabled"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: No clock,1: LSE oscillator clock used as RTC clock,2: LSI oscillator clock used as RTC clock,3: HSE oscillator clock divided by 32 used as RTC.."
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure Detection" "0: No failure detected on LSE (32 kHz oscillator),1: Failure detected on LSE (32 kHz oscillator)"
|
|
newline
|
|
bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0: CSS on LSE (32 kHz external oscillator) OFF,1: CSS on LSE (32 kHz external oscillator) ON"
|
|
bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive capability" "0: Xtal mode lower driving capability,1: Xtal mode medium low driving capability,2: Xtal mode medium high driving capability,3: Xtal mode higher driving capability"
|
|
newline
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed,1: LSE oscillator bypassed"
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready,1: LSE oscillator ready"
|
|
newline
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0: LSE oscillator OFF,1: LSE oscillator ON"
|
|
line.long 0x4 "RCC_CSR,Control/status register"
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0: No illegal mode reset occurred,1: Illegal mode reset occurred"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0: No window watchdog reset occurred,1: Window watchdog reset occurred"
|
|
newline
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0: No independent watchdog reset occurred,1: Independent watchdog reset occurred"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred"
|
|
newline
|
|
rbitfld.long 0x4 27. "BORRSTF,BOR flag" "0: No BOR occurred,1: BOR occurred"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0: No reset from NRST pin occurred,1: Reset from NRST pin occurred"
|
|
newline
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0: No reset from Option Byte loading occurred,1: Reset from Option Byte loading occurred"
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flag" "0: No effect,1: Clear the reset flags"
|
|
newline
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI oscillator not ready,1: LSI oscillator ready"
|
|
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: LSI oscillator OFF,1: LSI oscillator ON"
|
|
line.long 0x8 "RCC_CRRCR,Clock recovery RC register"
|
|
hexmask.long.word 0x8 7.--15. 1. "HSI48CAL,HSI48 clock calibration"
|
|
rbitfld.long 0x8 1. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 oscillator not ready,1: HSI48 oscillator ready"
|
|
newline
|
|
bitfld.long 0x8 0. "HSI48ON,HSI48 clock enable" "0: HSI48 oscillator OFF,1: HSI48 oscillator ON"
|
|
line.long 0xC "RCC_CCIPR2,Peripherals independent clock configuration register"
|
|
bitfld.long 0xC 20.--21. "QSPISEL,QUADSPI clock source selection" "0: system clock selected as QUADSPI kernel clock,1: HSI16 clock selected as QUADSPI kernel clock,2: PLL Q clock selected as QUADSPI kernel clock,?"
|
|
bitfld.long 0xC 0.--1. "I2C4SEL,I2C4 clock source selection" "0: PCLK selected as I2C4 clock,1: System clock (SYSCLK) selected as I2C4 clock,2: HSI16 clock selected as I2C4 clock,?"
|
|
tree.end
|
|
tree "RNG (Random Number Generator)"
|
|
base ad:0x50060800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0,1"
|
|
bitfld.long 0x0 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "RNGEN,Random number generator enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0,1"
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0,1"
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
|
|
rbitfld.long 0x4 0. "DRDY,Data ready" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DR,data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
tree.end
|
|
tree "RTC (Real-Time Counter)"
|
|
base ad:0x40002800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "ICSR,initialization and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0,1"
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x4 "PRER,prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1"
|
|
bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0,1"
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0,1,2,3"
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0,1"
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0,1"
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0,1"
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0,1"
|
|
bitfld.long 0xC 15. "TSIE,Time-stamp interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0,1"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0,1"
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0,1"
|
|
bitfld.long 0xC 11. "TSE,Time stamp enable" "0,1"
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0,1"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0,1"
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0,1"
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0,1"
|
|
bitfld.long 0xC 4. "REFCKON,Reference clock detection enable (50 or 60 Hz)" "0,1"
|
|
bitfld.long 0xC 3. "TSEDGE,Time-stamp event active edge" "0,1"
|
|
bitfld.long 0xC 0.--2. "WCKSEL,Wakeup clock selection" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "ALRMBR,alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1"
|
|
bitfld.long 0x0 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,WUTF" "0,1"
|
|
bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1"
|
|
line.long 0x4 "MISR,status register"
|
|
bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1"
|
|
bitfld.long 0x4 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1"
|
|
bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "SCR,status register"
|
|
bitfld.long 0x0 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1"
|
|
bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1"
|
|
tree.end
|
|
tree "SAI (Serial Audio Interface)"
|
|
base ad:0x40015400
|
|
group.long 0x24++0x13
|
|
line.long 0x0 "BCR1,BConfiguration register 1"
|
|
bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1"
|
|
bitfld.long 0x0 26. "OSR,OSR" "0,1"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
bitfld.long 0x0 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 16. "SAIBEN,Audio block B enable" "0,1"
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x0 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x0 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
line.long 0x4 "BCR2,BConfiguration register 2"
|
|
bitfld.long 0x4 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x4 13. "CPL,Complement bit" "0,1"
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
bitfld.long 0x4 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x4 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x4 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x4 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "BFRCR,BFRCR"
|
|
bitfld.long 0x8 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x8 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x8 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FRL,Frame length"
|
|
line.long 0xC "BSLOTR,BSlot register"
|
|
hexmask.long.word 0xC 16.--31. 1. "SLOTEN,Slot enable"
|
|
hexmask.long.byte 0xC 8.--11. 1. "NBSLOT,Number of slots in an audio frame"
|
|
bitfld.long 0xC 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x10 "BIM,BInterrupt mask register2"
|
|
bitfld.long 0x10 6. "LFSDETIE,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x10 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "BSR,BStatus register"
|
|
bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x0 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x0 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x0 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "BCLRFR,BClear flag register"
|
|
bitfld.long 0x0 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x0 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x0 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x0 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x0 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "BDR,BData register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
group.long 0x4++0x1F
|
|
line.long 0x0 "ACR1,AConfiguration register 1"
|
|
bitfld.long 0x0 27. "MCKEN,MCKEN" "0,1"
|
|
bitfld.long 0x0 26. "OSR,OSR" "0,1"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MCJDIV,Master clock divider"
|
|
bitfld.long 0x0 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x0 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x0 16. "SAIAEN,Audio block A enable" "0,1"
|
|
bitfld.long 0x0 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x0 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x0 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
bitfld.long 0x0 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
line.long 0x4 "ACR2,AConfiguration register 2"
|
|
bitfld.long 0x4 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x4 13. "CPL,Complement bit" "0,1"
|
|
hexmask.long.byte 0x4 7.--12. 1. "MUTECN,Mute counter"
|
|
bitfld.long 0x4 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x4 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x4 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x4 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x4 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "AFRCR,AFRCR"
|
|
bitfld.long 0x8 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x8 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x8 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x8 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FRL,Frame length"
|
|
line.long 0xC "ASLOTR,ASlot register"
|
|
hexmask.long.word 0xC 16.--31. 1. "SLOTEN,Slot enable"
|
|
hexmask.long.byte 0xC 8.--11. 1. "NBSLOT,Number of slots in an audio frame"
|
|
bitfld.long 0xC 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "FBOFF,First bit offset"
|
|
line.long 0x10 "AIM,AInterrupt mask register2"
|
|
bitfld.long 0x10 6. "LFSDET,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x10 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x10 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x10 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x10 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
line.long 0x14 "ASR,AStatus register"
|
|
bitfld.long 0x14 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x14 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x14 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x14 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x14 2. "WCKCFG,Wrong clock configuration flag. This bit is read only" "0,1"
|
|
bitfld.long 0x14 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x14 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
line.long 0x18 "ACLRFR,AClear flag register"
|
|
bitfld.long 0x18 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x18 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x18 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x18 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x18 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x18 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
line.long 0x1C "ADR,AData register"
|
|
hexmask.long 0x1C 0.--31. 1. "DATA,Data"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PDMCR,PDM control register"
|
|
bitfld.long 0x0 11. "CKEN4,CKEN4" "0,1"
|
|
bitfld.long 0x0 10. "CKEN3,CKEN3" "0,1"
|
|
bitfld.long 0x0 9. "CKEN2,CKEN2" "0,1"
|
|
bitfld.long 0x0 8. "CKEN1,CKEN1" "0,1"
|
|
bitfld.long 0x0 4.--5. "MICNBR,MICNBR" "0,1,2,3"
|
|
bitfld.long 0x0 0. "PDMEN,PDMEN" "0,1"
|
|
line.long 0x4 "PDMDLY,PDM delay register"
|
|
bitfld.long 0x4 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface/Inter-IC Sound)"
|
|
base ad:0x0
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40003C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
sif (cpuis("STM32G471*"))
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2SMOD" "0,1"
|
|
bitfld.long 0x0 10. "I2SE,I2SE" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2SCFG" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCMSYNC" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,I2SSTD" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,DATLEN" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,CHLEN" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,MCKOE" "0,1"
|
|
bitfld.long 0x4 8. "ODD,ODD" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2SDIV"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "MEMRMP,Remap Memory register"
|
|
bitfld.long 0x0 8. "FB_mode,User Flash Bank mode" "0,1"
|
|
bitfld.long 0x0 0.--2. "MEM_MODE,Memory mapping selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CFGR1,peripheral mode configuration register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "FPU_IE,FPU Interrupts Enable"
|
|
bitfld.long 0x4 23. "I2C4_FMP,I2C1 FM+ drive capability enable" "0,1"
|
|
bitfld.long 0x4 22. "I2C3_FMP,I2C1 FM+ drive capability enable" "0,1"
|
|
bitfld.long 0x4 21. "I2C2_FMP,I2C1 FM+ drive capability enable" "0,1"
|
|
bitfld.long 0x4 20. "I2C1_FMP,I2C1 FM+ drive capability enable" "0,1"
|
|
bitfld.long 0x4 19. "I2C_PB9_FMP,FM+ drive capability on PB6" "0,1"
|
|
bitfld.long 0x4 18. "I2C_PB8_FMP,FM+ drive capability on PB6" "0,1"
|
|
bitfld.long 0x4 17. "I2C_PB7_FMP,FM+ drive capability on PB6" "0,1"
|
|
bitfld.long 0x4 16. "I2C_PB6_FMP,FM+ drive capability on PB6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch control voltage selection" "0,1"
|
|
bitfld.long 0x4 8. "BOOSTEN,BOOSTEN" "0,1"
|
|
line.long 0x8 "EXTICR1,external interrupt configuration register 1"
|
|
hexmask.long.byte 0x8 12.--15. 1. "EXTI3,EXTI x configuration (x = 0 to 3)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "EXTI2,EXTI x configuration (x = 0 to 3)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "EXTI1,EXTI x configuration (x = 0 to 3)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "EXTI0,EXTI x configuration (x = 0 to 3)"
|
|
line.long 0xC "EXTICR2,external interrupt configuration register 2"
|
|
hexmask.long.byte 0xC 12.--15. 1. "EXTI7,EXTI x configuration (x = 4 to 7)"
|
|
hexmask.long.byte 0xC 8.--11. 1. "EXTI6,EXTI x configuration (x = 4 to 7)"
|
|
hexmask.long.byte 0xC 4.--7. 1. "EXTI5,EXTI x configuration (x = 4 to 7)"
|
|
hexmask.long.byte 0xC 0.--3. 1. "EXTI4,EXTI x configuration (x = 4 to 7)"
|
|
line.long 0x10 "EXTICR3,external interrupt configuration register 3"
|
|
hexmask.long.byte 0x10 12.--15. 1. "EXTI11,EXTI x configuration (x = 8 to 11)"
|
|
hexmask.long.byte 0x10 8.--11. 1. "EXTI10,EXTI10"
|
|
hexmask.long.byte 0x10 4.--7. 1. "EXTI9,EXTI x configuration (x = 8 to 11)"
|
|
hexmask.long.byte 0x10 0.--3. 1. "EXTI8,EXTI x configuration (x = 8 to 11)"
|
|
line.long 0x14 "EXTICR4,external interrupt configuration register 4"
|
|
hexmask.long.byte 0x14 12.--15. 1. "EXTI15,EXTI x configuration (x = 12 to 15)"
|
|
hexmask.long.byte 0x14 8.--11. 1. "EXTI14,EXTI x configuration (x = 12 to 15)"
|
|
hexmask.long.byte 0x14 4.--7. 1. "EXTI13,EXTI x configuration (x = 12 to 15)"
|
|
hexmask.long.byte 0x14 0.--3. 1. "EXTI12,EXTI x configuration (x = 12 to 15)"
|
|
line.long 0x18 "SCSR,CCM SRAM control and status register"
|
|
rbitfld.long 0x18 1. "CCMBSY,CCM SRAM busy by erase operation" "0,1"
|
|
bitfld.long 0x18 0. "CCMER,CCM SRAM Erase" "0,1"
|
|
line.long 0x1C "CFGR2,configuration register 2"
|
|
bitfld.long 0x1C 8. "SPF,SRAM Parity Flag" "0,1"
|
|
bitfld.long 0x1C 3. "ECCL,ECC Lock" "0,1"
|
|
bitfld.long 0x1C 2. "PVDL,PVD Lock" "0,1"
|
|
bitfld.long 0x1C 1. "SPL,SRAM Parity Lock" "0,1"
|
|
bitfld.long 0x1C 0. "CLL,Core Lockup Lock" "0,1"
|
|
line.long 0x20 "SWPR,SRAM Write protection register 1"
|
|
bitfld.long 0x20 31. "Page31_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 30. "Page30_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 29. "Page29_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 28. "Page28_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 27. "Page27_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 26. "Page26_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 25. "Page25_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 24. "Page24_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 23. "Page23_WP,Write protection" "0,1"
|
|
newline
|
|
bitfld.long 0x20 22. "Page22_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 21. "Page21_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 20. "Page20_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 19. "Page19_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 18. "Page18_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 17. "Page17_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 16. "Page16_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 15. "Page15_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 14. "Page14_WP,Write protection" "0,1"
|
|
newline
|
|
bitfld.long 0x20 13. "Page13_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 12. "Page12_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 11. "Page11_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 10. "Page10_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 9. "Page9_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 8. "Page8_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 7. "Page7_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 6. "Page6_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 5. "Page5_WP,Write protection" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "Page4_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 3. "Page3_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 2. "Page2_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 1. "Page1_WP,Write protection" "0,1"
|
|
bitfld.long 0x20 0. "Page0_WP,Write protection" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "SKR,SRAM2 Key Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,SRAM2 Key for software erase"
|
|
tree.end
|
|
tree "TAMP (Tamper and Backup Registers)"
|
|
base ad:0x40002400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
bitfld.long 0x0 2. "TAMP3E,TAMP2E" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1"
|
|
bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1"
|
|
bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1"
|
|
line.long 0x4 "MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1MF:" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,CITAMP6F" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1"
|
|
bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
group.long 0x100++0x7F
|
|
line.long 0x0 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,BKP"
|
|
line.long 0x8 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,BKP"
|
|
line.long 0xC "BKP3R,TAMP backup register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,BKP"
|
|
line.long 0x10 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,BKP"
|
|
line.long 0x14 "BKP5R,TAMP backup register"
|
|
hexmask.long 0x14 0.--31. 1. "BKP,BKP"
|
|
line.long 0x18 "BKP6R,TAMP backup register"
|
|
hexmask.long 0x18 0.--31. 1. "BKP,BKP"
|
|
line.long 0x1C "BKP7R,TAMP backup register"
|
|
hexmask.long 0x1C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x20 "BKP8R,TAMP backup register"
|
|
hexmask.long 0x20 0.--31. 1. "BKP,BKP"
|
|
line.long 0x24 "BKP9R,TAMP backup register"
|
|
hexmask.long 0x24 0.--31. 1. "BKP,BKP"
|
|
line.long 0x28 "BKP10R,TAMP backup register"
|
|
hexmask.long 0x28 0.--31. 1. "BKP,BKP"
|
|
line.long 0x2C "BKP11R,TAMP backup register"
|
|
hexmask.long 0x2C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x30 "BKP12R,TAMP backup register"
|
|
hexmask.long 0x30 0.--31. 1. "BKP,BKP"
|
|
line.long 0x34 "BKP13R,TAMP backup register"
|
|
hexmask.long 0x34 0.--31. 1. "BKP,BKP"
|
|
line.long 0x38 "BKP14R,TAMP backup register"
|
|
hexmask.long 0x38 0.--31. 1. "BKP,BKP"
|
|
line.long 0x3C "BKP15R,TAMP backup register"
|
|
hexmask.long 0x3C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x40 "BKP16R,TAMP backup register"
|
|
hexmask.long 0x40 0.--31. 1. "BKP,BKP"
|
|
line.long 0x44 "BKP17R,TAMP backup register"
|
|
hexmask.long 0x44 0.--31. 1. "BKP,BKP"
|
|
line.long 0x48 "BKP18R,TAMP backup register"
|
|
hexmask.long 0x48 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4C "BKP19R,TAMP backup register"
|
|
hexmask.long 0x4C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x50 "BKP20R,TAMP backup register"
|
|
hexmask.long 0x50 0.--31. 1. "BKP,BKP"
|
|
line.long 0x54 "BKP21R,TAMP backup register"
|
|
hexmask.long 0x54 0.--31. 1. "BKP,BKP"
|
|
line.long 0x58 "BKP22R,TAMP backup register"
|
|
hexmask.long 0x58 0.--31. 1. "BKP,BKP"
|
|
line.long 0x5C "BKP23R,TAMP backup register"
|
|
hexmask.long 0x5C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x60 "BKP24R,TAMP backup register"
|
|
hexmask.long 0x60 0.--31. 1. "BKP,BKP"
|
|
line.long 0x64 "BKP25R,TAMP backup register"
|
|
hexmask.long 0x64 0.--31. 1. "BKP,BKP"
|
|
line.long 0x68 "BKP26R,TAMP backup register"
|
|
hexmask.long 0x68 0.--31. 1. "BKP,BKP"
|
|
line.long 0x6C "BKP27R,TAMP backup register"
|
|
hexmask.long 0x6C 0.--31. 1. "BKP,BKP"
|
|
line.long 0x70 "BKP28R,TAMP backup register"
|
|
hexmask.long 0x70 0.--31. 1. "BKP,BKP"
|
|
line.long 0x74 "BKP29R,TAMP backup register"
|
|
hexmask.long 0x74 0.--31. 1. "BKP,BKP"
|
|
line.long 0x78 "BKP30R,TAMP backup register"
|
|
hexmask.long 0x78 0.--31. 1. "BKP,BKP"
|
|
line.long 0x7C "BKP31R,TAMP backup register"
|
|
hexmask.long 0x7C 0.--31. 1. "BKP,BKP"
|
|
tree.end
|
|
tree "TIM (Timers)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G471*"))
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
endif
|
|
tree "TIM1"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM2"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM4"
|
|
base ad:0x40000800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
bitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM6"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIM7"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIM8"
|
|
base ad:0x40013400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM15"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time generator setup"
|
|
group.long 0x5C++0xB
|
|
line.long 0x0 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x4 "AF1,TIM alternate function option register 1"
|
|
bitfld.long 0x4 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x4 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x4 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x4 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x4 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x4 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
bitfld.long 0x4 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x4 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x4 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x4 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x4 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x4 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x8 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM16"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time generator setup"
|
|
group.long 0x5C++0xF
|
|
line.long 0x0 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x4 "AF1,TIM alternate function option register 1"
|
|
bitfld.long 0x4 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x4 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x4 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x4 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x4 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x4 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
bitfld.long 0x4 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x4 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x4 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x4 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x4 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x4 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x8 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0. "HSE32EN,HSE Divided by 32 enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable register"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x0 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x0 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTGF,Dead-time generator setup"
|
|
group.long 0x5C++0xF
|
|
line.long 0x0 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x4 "AF1,TIM alternate function option register 1"
|
|
bitfld.long 0x4 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x4 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x4 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x4 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x4 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x4 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
bitfld.long 0x4 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x4 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x4 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x4 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x4 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x4 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x8 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x8 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "OR1,TIM option register 1"
|
|
bitfld.long 0xC 0. "HSE32EN,HSE Divided by 32 enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree "TIM20"
|
|
base ad:0x40015000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 12. "DITHEN,Dithering Enable" "0,1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "MMS_3,Master mode selection - bit 3" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 15. "OIS4N,Output Idle state 4 (OC4N output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 25. "SMSPS,SMS Preload Source" "0,1"
|
|
bitfld.long 0x8 24. "SMSPE,SMS Preload Enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit 4:3" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 23. "TERRIE,Transition Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 22. "IERRIE,Index Error interrupt enable" "0,1"
|
|
bitfld.long 0xC 21. "DIRIE,Direction Change interrupt enable" "0,1"
|
|
bitfld.long 0xC 20. "IDXIE,Index interrupt enable" "0,1"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 23. "TERRF,Transition Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 22. "IERRF,Index Error interrupt flag" "0,1"
|
|
bitfld.long 0x10 21. "DIRF,Direction Change interrupt flag" "0,1"
|
|
bitfld.long 0x10 20. "IDXF,Index interrupt flag" "0,1"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 14. "CC4NE,Capture/Compare 4 complementary output enable" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,BK2ID" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,BKBID" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,BK2DSRM" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,BKDSRM" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 Enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x2C 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x2C 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x2C 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x30 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x30 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x34 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x34 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x34 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x34 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x34 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x34 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x34 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x38 "DTR2,timer Deadtime Register 2"
|
|
bitfld.long 0x38 17. "DTPE,Deadtime Preload Enable" "0,1"
|
|
bitfld.long 0x38 16. "DTAE,Deadtime Asymmetric Enable" "0,1"
|
|
hexmask.long.byte 0x38 0.--7. 1. "DTGF,Dead-time falling edge generator setup"
|
|
line.long 0x3C "ECR,DMA control register"
|
|
bitfld.long 0x3C 24.--26. "PWPRSC,Pulse Width prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PW,Pulse width"
|
|
bitfld.long 0x3C 6.--7. "IPOS,Index Positioning" "0,1,2,3"
|
|
bitfld.long 0x3C 5. "FIDX,First Index" "0,1"
|
|
bitfld.long 0x3C 3.--4. "IBLK,Index Blanking" "0,1,2,3"
|
|
bitfld.long 0x3C 1.--2. "IDIR,Index Direction" "0,1,2,3"
|
|
bitfld.long 0x3C 0. "IE,Index Enable" "0,1"
|
|
line.long 0x40 "TISEL,TIM timer input selection register"
|
|
hexmask.long.byte 0x40 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input selection"
|
|
hexmask.long.byte 0x40 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x40 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x40 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
line.long 0x44 "AF1,TIM alternate function option register 1"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 13. "BKCMP4P,BRK COMP4 input polarity" "0,1"
|
|
bitfld.long 0x44 12. "BKCMP3P,BRK COMP3 input polarity" "0,1"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 7. "BKCMP7E,BRK COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "BKCMP6E,BRK COMP6 enable" "0,1"
|
|
bitfld.long 0x44 5. "BKCMP5E,BRK COMP5 enable" "0,1"
|
|
bitfld.long 0x44 4. "BKCMP4E,BRK COMP4 enable" "0,1"
|
|
bitfld.long 0x44 3. "BKCMP3E,BRK COMP3 enable" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,TIM alternate function option register 2"
|
|
bitfld.long 0x48 16.--18. "OCRSEL,OCREF_CLR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x48 13. "BK2CMP4P,BRK2 COMP4 input polarity" "0,1"
|
|
bitfld.long 0x48 12. "BK2CMP3P,BRK2 COMP3 input polarity" "0,1"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 7. "BK2CMP7E,BRK2 COMP7 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 6. "BK2CMP6E,BRK2 COMP6 enable" "0,1"
|
|
bitfld.long 0x48 5. "BK2CMP5E,BRK2 COMP5 enable" "0,1"
|
|
bitfld.long 0x48 4. "BK2CMP4E,BRK2 COMP4 enable" "0,1"
|
|
bitfld.long 0x48 3. "BK2CMP3E,BRK2 COMP3 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x3DC++0x7
|
|
line.long 0x0 "DCR,control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x4 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
tree.end
|
|
tree.end
|
|
tree "UCPD (USB Type-C/USB Power Delivery Controller)"
|
|
base ad:0x4000A000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CFG1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1"
|
|
bitfld.long 0x0 30. "RXDMAEN,RXDMAEN" "0,1"
|
|
bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN"
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV"
|
|
line.long 0x4 "CFG2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1"
|
|
bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1"
|
|
bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1"
|
|
bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1"
|
|
group.long 0xC++0x1B
|
|
line.long 0x0 "CR,UCPD configuration register 2"
|
|
bitfld.long 0x0 21. "CC2TCDIS,CC2TCDIS" "0,1"
|
|
bitfld.long 0x0 20. "CC1TCDIS,CC1TCDIS" "0,1"
|
|
bitfld.long 0x0 18. "RDCH,RDCH" "0,1"
|
|
bitfld.long 0x0 17. "FRSTX,FRSTX" "0,1"
|
|
bitfld.long 0x0 16. "FRSRXEN,FRSRXEN" "0,1"
|
|
bitfld.long 0x0 10.--11. "CCENABLE,CCENABLE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9. "ANAMODE,ANAMODE" "0,1"
|
|
bitfld.long 0x0 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3"
|
|
bitfld.long 0x0 6. "PHYCCSEL,PHYCCSEL" "0,1"
|
|
bitfld.long 0x0 5. "PHYRXEN,PHYRXEN" "0,1"
|
|
bitfld.long 0x0 4. "RXMODE,RXMODE" "0,1"
|
|
bitfld.long 0x0 3. "TXHRST,TXHRST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXSEND,TXSEND" "0,1"
|
|
bitfld.long 0x0 0.--1. "TXMODE,TXMODE" "0,1,2,3"
|
|
line.long 0x4 "IMR,UCPD Interrupt Mask Register"
|
|
bitfld.long 0x4 20. "FRSEVTIE,FRSEVTIE" "0,1"
|
|
bitfld.long 0x4 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1"
|
|
bitfld.long 0x4 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1"
|
|
bitfld.long 0x4 12. "RXMSGENDIE,RXMSGENDIE" "0,1"
|
|
bitfld.long 0x4 11. "RXOVRIE,RXOVRIE" "0,1"
|
|
bitfld.long 0x4 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXORDDETIE,RXORDDETIE" "0,1"
|
|
bitfld.long 0x4 8. "RXNEIE,RXNEIE" "0,1"
|
|
bitfld.long 0x4 6. "TXUNDIE,TXUNDIE" "0,1"
|
|
bitfld.long 0x4 5. "HRSTSENTIE,HRSTSENTIE" "0,1"
|
|
bitfld.long 0x4 4. "HRSTDISCIE,HRSTDISCIE" "0,1"
|
|
bitfld.long 0x4 3. "TXMSGABTIE,TXMSGABTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1"
|
|
bitfld.long 0x4 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1"
|
|
bitfld.long 0x4 0. "TXISIE,TXISIE" "0,1"
|
|
line.long 0x8 "SR,UCPD Status Register"
|
|
bitfld.long 0x8 20. "FRSEVT,FRSEVT" "0,1"
|
|
bitfld.long 0x8 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3"
|
|
bitfld.long 0x8 15. "TYPECEVT2,TYPECEVT2" "0,1"
|
|
bitfld.long 0x8 14. "TYPECEVT1,TYPECEVT1" "0,1"
|
|
bitfld.long 0x8 13. "RXERR,RXERR" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "RXMSGEND,RXMSGEND" "0,1"
|
|
bitfld.long 0x8 11. "RXOVR,RXOVR" "0,1"
|
|
bitfld.long 0x8 10. "RXHRSTDET,RXHRSTDET" "0,1"
|
|
bitfld.long 0x8 9. "RXORDDET,RXORDDET" "0,1"
|
|
bitfld.long 0x8 8. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x8 6. "TXUND,TXUND" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "HRSTSENT,HRSTSENT" "0,1"
|
|
bitfld.long 0x8 4. "HRSTDISC,HRSTDISC" "0,1"
|
|
bitfld.long 0x8 3. "TXMSGABT,TXMSGABT" "0,1"
|
|
bitfld.long 0x8 2. "TXMSGSENT,TXMSGSENT" "0,1"
|
|
bitfld.long 0x8 1. "TXMSGDISC,TXMSGDISC" "0,1"
|
|
bitfld.long 0x8 0. "TXIS,TXIS" "0,1"
|
|
line.long 0xC "ICR,UCPD Interrupt Clear Register"
|
|
bitfld.long 0xC 20. "FRSEVTCF,FRSEVTCF" "0,1"
|
|
bitfld.long 0xC 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1"
|
|
bitfld.long 0xC 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1"
|
|
bitfld.long 0xC 12. "RXMSGENDCF,RXMSGENDCF" "0,1"
|
|
bitfld.long 0xC 11. "RXOVRCF,RXOVRCF" "0,1"
|
|
bitfld.long 0xC 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "RXORDDETCF,RXORDDETCF" "0,1"
|
|
bitfld.long 0xC 6. "TXUNDCF,TXUNDCF" "0,1"
|
|
bitfld.long 0xC 5. "HRSTSENTCF,HRSTSENTCF" "0,1"
|
|
bitfld.long 0xC 4. "HRSTDISCCF,HRSTDISCCF" "0,1"
|
|
bitfld.long 0xC 3. "TXMSGABTCF,TXMSGABTCF" "0,1"
|
|
bitfld.long 0xC 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1"
|
|
line.long 0x10 "TX_ORDSET,UCPD Tx Ordered Set Type Register"
|
|
hexmask.long.tbyte 0x10 0.--19. 1. "TXORDSET,TXORDSET"
|
|
line.long 0x14 "TX_PAYSZ,UCPD Tx Paysize Register"
|
|
hexmask.long.word 0x14 0.--9. 1. "TXPAYSZ,TXPAYSZ"
|
|
line.long 0x18 "TXDR,UCPD Tx Data Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TXDATA,TXDATA"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1"
|
|
bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RX_PAYSZ,UCPD Rx Paysize Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,RXPAYSZ"
|
|
line.long 0x8 "RXDR,UCPD Rx Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,RXDATA"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension Register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1"
|
|
line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension Register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2"
|
|
tree.end
|
|
tree "USART (Universal Synchronous Asynchronous Receiver/Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G471*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G473*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G474*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G483*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G484*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G491*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G4A1*"))
|
|
tree "UART5"
|
|
base ad:0x40005000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*")||cpuis("STM32G473*")||cpuis("STM32G474*")||cpuis("STM32G483*")||cpuis("STM32G484*")||cpuis("STM32G491*")||cpuis("STM32G4A1*"))
|
|
tree "UART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,M1" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,SLVEN" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "DIV_Mantissa,DIV_Mantissa"
|
|
hexmask.long.byte 0xC 0.--3. 1. "DIV_Fraction,DIV_Fraction"
|
|
line.long 0x10 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,UDR" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFECF" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
endif
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1"
|
|
bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,TXFRQ" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER"
|
|
tree.end
|
|
tree.end
|
|
tree "USB_FS (Universal Serial Bus Full-Speed Device Interface)"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "EP0R,USB endpoint n register"
|
|
bitfld.long 0x0 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x0 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x0 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x0 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x0 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x0 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x0 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x0 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x0 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "EA,EA"
|
|
line.long 0x4 "EP1R,USB endpoint n register"
|
|
bitfld.long 0x4 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x4 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x4 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x4 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x4 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x4 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x4 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x4 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x4 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EA,EA"
|
|
line.long 0x8 "EP2R,USB endpoint n register"
|
|
bitfld.long 0x8 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x8 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x8 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x8 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x8 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x8 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x8 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x8 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x8 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x8 0.--3. 1. "EA,EA"
|
|
line.long 0xC "EP3R,USB endpoint n register"
|
|
bitfld.long 0xC 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0xC 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0xC 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0xC 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0xC 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0xC 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0xC 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0xC 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0xC 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--3. 1. "EA,EA"
|
|
line.long 0x10 "EP4R,USB endpoint n register"
|
|
bitfld.long 0x10 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x10 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x10 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x10 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x10 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x10 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x10 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x10 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x10 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--3. 1. "EA,EA"
|
|
line.long 0x14 "EP5R,USB endpoint n register"
|
|
bitfld.long 0x14 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x14 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x14 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x14 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x14 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x14 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x14 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x14 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x14 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x14 0.--3. 1. "EA,EA"
|
|
line.long 0x18 "EP6R,USB endpoint n register"
|
|
bitfld.long 0x18 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x18 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x18 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x18 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x18 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x18 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x18 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x18 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x18 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x18 0.--3. 1. "EA,EA"
|
|
line.long 0x1C "EP7R,USB endpoint n register"
|
|
bitfld.long 0x1C 15. "CTR_RX,CTR_RX" "0,1"
|
|
bitfld.long 0x1C 14. "DTOG_RX,DTOG_RX" "0,1"
|
|
bitfld.long 0x1C 12.--13. "STAT_RX,STAT_RX" "0,1,2,3"
|
|
bitfld.long 0x1C 11. "SETUP,SETUP" "0,1"
|
|
bitfld.long 0x1C 9.--10. "EP_TYPE,EP_TYPE" "0,1,2,3"
|
|
bitfld.long 0x1C 8. "EP_KIND,EP_KIND" "0,1"
|
|
bitfld.long 0x1C 7. "CTR_TX,CTR_TX" "0,1"
|
|
bitfld.long 0x1C 6. "DTOG_TX,DTOG_TX" "0,1"
|
|
bitfld.long 0x1C 4.--5. "STAT_TX,STAT_TX" "0,1,2,3"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "EA,EA"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CNTR,USB control register"
|
|
bitfld.long 0x0 15. "CTRM,CTRM" "0,1"
|
|
bitfld.long 0x0 14. "PMAOVRM,PMAOVRM" "0,1"
|
|
bitfld.long 0x0 13. "ERRM,ERRM" "0,1"
|
|
bitfld.long 0x0 12. "WKUPM,WKUPM" "0,1"
|
|
bitfld.long 0x0 11. "SUSPM,SUSPM" "0,1"
|
|
bitfld.long 0x0 10. "RESETM,RESETM" "0,1"
|
|
bitfld.long 0x0 9. "SOFM,SOFM" "0,1"
|
|
bitfld.long 0x0 8. "ESOFM,ESOFM" "0,1"
|
|
bitfld.long 0x0 7. "L1REQM,L1REQM" "0,1"
|
|
bitfld.long 0x0 5. "L1RESUME,L1RESUME" "0,1"
|
|
bitfld.long 0x0 4. "RESUME,RESUME" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FSUSP,FSUSP" "0,1"
|
|
bitfld.long 0x0 2. "LP_MODE,LP_MODE" "0,1"
|
|
bitfld.long 0x0 1. "PDWN,PDWN" "0,1"
|
|
bitfld.long 0x0 0. "FRES,FRES" "0,1"
|
|
line.long 0x4 "ISTR,USB interrupt status register"
|
|
bitfld.long 0x4 15. "CTR,CTR" "0,1"
|
|
bitfld.long 0x4 14. "PMAOVR,PMAOVR" "0,1"
|
|
bitfld.long 0x4 13. "ERR,ERR" "0,1"
|
|
bitfld.long 0x4 12. "WKUP,WKUP" "0,1"
|
|
bitfld.long 0x4 11. "SUSP,SUSP" "0,1"
|
|
bitfld.long 0x4 10. "RESET,RESET" "0,1"
|
|
bitfld.long 0x4 9. "SOF,SOF" "0,1"
|
|
bitfld.long 0x4 8. "ESOF,ESOF" "0,1"
|
|
bitfld.long 0x4 7. "L1REQ,L1REQ" "0,1"
|
|
bitfld.long 0x4 4. "DIR,DIR" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "EP_ID,EP_ID"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "FNR,USB frame number register"
|
|
bitfld.long 0x0 15. "RXDP,RXDP" "0,1"
|
|
bitfld.long 0x0 14. "RXDM,RXDM" "0,1"
|
|
bitfld.long 0x0 13. "LCK,LCK" "0,1"
|
|
bitfld.long 0x0 11.--12. "LSOF,LSOF" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--10. 1. "FN,FN"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "DADDR,USB device address"
|
|
bitfld.long 0x0 7. "EF,EF" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ADD,ADD"
|
|
line.long 0x4 "BTABLE,Buffer table address"
|
|
hexmask.long.word 0x4 3.--15. 1. "BTABLE,BTABLE"
|
|
tree.end
|
|
sif (cpuis("STM32G431*")||cpuis("STM32G441*")||cpuis("STM32G471*")||cpuis("STM32G473*")||cpuis("STM32G474*")||cpuis("STM32G483*")||cpuis("STM32G484*")||cpuis("STM32G491*")||cpuis("STM32G4A1*"))
|
|
tree "VREFBUF (Voltage Reference Buffer)"
|
|
base ad:0x40010030
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREF_BUF Control and Status Register"
|
|
bitfld.long 0x0 4.--5. "VRS,Voltage reference scale" "0,1,2,3"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0,1"
|
|
bitfld.long 0x0 1. "HIZ,High impedence mode for the VREF_BUF" "0,1"
|
|
bitfld.long 0x0 0. "ENVR,Enable Voltage Reference" "0,1"
|
|
line.long 0x4 "VREFBUF_CCR,VREF_BUF Calibration Control Register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
tree.end
|
|
endif
|
|
tree "WWDG (Window Watchdog)"
|
|
base ad:0x40002C00
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1"
|
|
tree.end
|
|
AUTOINDENT.OFF
|